JPH05275532A - Method of lsi wiring design - Google Patents

Abstract

PURPOSE:To provide the title method of LSI wiring design without lowering the mounting density by a method wherein the wiring kinds differentiated by line width, etc., are allotted to respective wiring layers at arbitrary rates to be set up at the intervals exceeding the wiring adjacency forbidden interval according to the wiring kind allotting wiring lattice intervals of respective wiring layers. CONSTITUTION:The wiring design method of LSI allotting wiring layer per line width is characterized by the composition of an allotting means 3 per wiring kind and a wiring lattice data collecting means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI for multi-layer wiring.
Related to the wiring design method.

[0002]

2. Description of the Related Art In the conventional LSI wiring design method, the problem is standardized by setting the widths of all the wirings and the intervals between the wirings to constant values in consideration of the worst case. As a reference, "CAD of logic device", published by IPSJ, published on March 20, 1981.

[0003]

DISCLOSURE OF THE INVENTION The conventional LSI described above
The wiring processing method of (1) has a drawback that the mounting density is lowered because the widths of all the wirings and the intervals between the wirings are set to constant values.

An object of the present invention is to allocate different wiring types depending on the line width and the like to each wiring layer at an arbitrary ratio, and set the wiring grid interval of each wiring layer to a wiring adjoining prohibition interval or more in accordance with the allocated wiring type, and implement it. An object of the present invention is to provide an LSI wiring design method in which the density does not decrease.

[0005]

The LSI wiring design method of the present invention is a wiring design of an LSI having a multi-layer wiring layer, and wiring rule information for storing information of wiring adjoining prohibition intervals which differ depending on the wiring line width and the like. The storage means, the initial grid spacing information storage means for storing the wiring spacing information in the horizontal and vertical directions of each layer depending on the underlying layer, and the wiring rule information read from the wiring rule information storage means, and the wiring type that differs depending on the line width or the like To each wiring layer at an arbitrary ratio, a wiring type layer allocating means for storing information obtained by the wiring type layer allocating means, and a wiring rule read from the wiring rule information storing means. The information and the wiring type layer allocation information read from the wiring type layer allocation information storage means are read from the initial lattice spacing information storage means. Wiring grid information generating means for deleting the grid information below the wiring adjoining prohibition interval assigned to each layer from the outputted initial grid spacing information for each layer, and wiring grid information storing means for storing the information generated by the wiring grid information generating means. And connection information storing means for storing a connection relation between terminals, wiring type layer allocation information read from the wiring type layer allocation information storage means, and wiring grid information read from the wiring grid information storage means. Wiring means for performing wiring for connection between terminals read from the storage means according to wiring grid information in a layer allocated based on the type of wiring.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an example of an LSI wiring design method of the present invention. As shown in FIG. 1, the wiring rule information storage unit 1 stores wiring adjacency prohibition interval information that varies depending on the line width of the wiring. The initial lattice spacing information storage means 2 stores horizontal and vertical wiring spacing information of each layer depending on the base.

Therefore, the wiring type layer allocating means 3 allocates the wiring types, which differ depending on the line width and the like, to the respective wiring layers at an arbitrary ratio based on the wiring rule information read from the wiring rule information storing means 1. The wiring type layer allocation information storage means 4 stores the information obtained by the wiring type layer allocation means 3.

Then, the wiring grid information generation means 5 stores the initial grid spacing information by the wiring rule information read from the wiring rule information storage means 1 and the wiring type layer allocation information read from the wiring type layer allocation information storage means 4. Means 2
From the initial lattice spacing information of each layer read from, the lattice information below the adjacent forbidden spacing assigned to each layer is deleted.

The wiring grid information storage means 6 stores the information generated by the wiring grid information generation means 5. The connection information storage means 7 stores the connection relationship between terminals. The wiring means 8 uses the wiring type layer allocation information read from the wiring type layer allocation information storage means 4 and the wiring grid information read from the wiring grid information storage means 6 to connect the terminals read from the connection information storage means 7. Wiring is performed according to the wiring grid information in the layer allocated based on the type of wiring.

Next, the operation of the wiring design system of the present embodiment thus constructed will be described.

FIG. 2 is a diagram for explaining an example of information stored in the initial lattice spacing information storage means 2. As shown in FIG. 2, the lattice spacing information 2A-1 is information stored in the initial lattice spacing information storage means 2, is a description example of the horizontal and vertical wiring spacing information of each layer, A detailed description is given in the grid spacing information detailed description 2A-2. Metal 1 and 2 layers 2B-1 and Metal 3 and 4 layers 2B
Reference numeral -2 indicates a graphic image of the lattice described in the lattice spacing information 2A-1.

FIG. 3 is a diagram for explaining an example of information stored in the wiring rule information storage means 1. As shown in FIG. 3, the wiring rule information 3A-1 is a description example of information of the adjacency prohibition interval which is different depending on the line width of the wiring stored in the wiring rule information storage means 1 and the detailed description of each information. Is described in Wiring Rule Description 3A-2.

FIG. 4 is a diagram showing an example of information obtained by the operation of the wiring type layer allocating means 3 and stored in the wiring type layer allocating information storage means 4. As shown in FIG. 4, the wiring type layer allocating means 3 uses the wiring rule information read from the wiring rule information storage means 1 to determine the wiring types “LIN1” and “LIN2” at a ratio of (1: 1). Allocate to the layer and set the metal 1 layer and the metal 2 layer to "LIN
"LIN2" for metal 3 layer and metal 4 layer for 1 "
And the result is stored in the wiring type layer allocation information storage means 4 as the wiring type layer allocation information of FIG. Further, in the case of the wiring that does not use the wiring type “LIN2”, no layer allocation is performed for the wiring type “LIN2”, and all the wiring layers are allocated to the wiring type “LIN1”.

FIG. 5 is a diagram for explaining an example of the operation of the wiring grid information generation means 5 in association with the initial grid spacing information storage means 2, the wiring rule information storage means 1, and the wiring type layer allocation information storage means 4. As shown in FIG. 5, in order to first perform the wiring grid information generation processing for the first metal layer, the wiring type assigned to this layer is “LI”.
Wiring type layer allocation information storage means 4 is N1 "
Further, after obtaining from the wiring rule information storage means 1 that the adjacency prohibition interval of the wiring type “LIN1” is 5, it is compared with the initial lattice spacing of the metal 1 layer read from the initial lattice spacing information storage means 2. It is confirmed that the initial lattice spacing satisfies the adjoining prohibition spacing, and the wiring lattice information of the metal 1 layer is generated. The result is the metal 1 layer 5A. The metal 2 layer is processed in the same manner as the metal 1 layer.

In the wiring grid information generation process for the third metal layer, the wiring type "LIN2" is obtained from the wiring type layer allocation information storage means 4, and the wiring type "LIN" is obtained.
After obtaining from the wiring rule information storage means 1 that the 2 ″ adjoining prohibition interval is 10, a comparison is made with the initial grid spacing of the metal 3 layer read from the initial grid spacing information storage means 2,
Confirm that the initial grid spacing does not satisfy the adjacent spacing, and delete the grid information in the horizontal directions 5, 15, and 25.
Shape the grid so that all the grid spacing is 10 or more,
The result of generating the wiring grid information of the metal 3 layer is metal 3.
It is the layer 5B. The metal 4 layer is processed in the same manner as the metal 3 layer. All the wiring grid information created by this processing is stored in the wiring grid information storage means 6.

The wiring means 8 uses the wiring grid information stored in the wiring grid information storage means 6,
It is possible to process a connection of a wiring type having a narrow adjacent prohibition interval in a wiring layer having a narrow wiring grid interval and a connection of a wiring type having a wide adjacent prohibition interval in a wiring layer having a wide wiring grid interval.

[0017]

As described above, according to the LSI wiring design method of the present invention, the wiring types that differ depending on the line width are assigned to each wiring layer at an arbitrary ratio, and the wiring grid spacing of each wiring layer is assigned. Setting the wiring adjacency prohibition interval or more according to the type has an effect that the mounting density does not decrease.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an LSI wiring design method of the present invention.

FIG. 2 is a diagram illustrating an example of information stored in an initial lattice spacing information storage unit 2.

FIG. 3 is a diagram illustrating an example of information stored in a wiring rule information storage unit 1.

FIG. 4 is a diagram showing an example of information obtained by the operation of the wiring type layer allocating means 3 and stored in the wiring type layer allocating information storage means 4;

5 is a diagram for explaining the operation of the wiring grid information generation means 5 in association with the initial grid spacing information storage means 2, the wiring rule information storage means 1, and the wiring type layer allocation information storage means 4. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring rule information storage means 2 Initial grid spacing information storage means 3 Wiring layer allocation means 4 Wiring layer allocation information storage means 5 Wiring grid information generation means 6 Wiring grid information storage means 7 Connection information storage means 8 Wiring means

Claims (1)

[Claims] 1. In a wiring design of an LSI having a plurality of wiring layers, wiring rule information storage means for storing information on a wiring adjoining prohibition interval which varies depending on a wiring line width and the like, and horizontal and vertical directions of each layer depending on a base. Initial grid spacing information storage means for storing wiring spacing information of the wiring, and wiring type layer allocation for allocating wiring types that differ according to line width etc. to each wiring layer at an arbitrary ratio based on the wiring rule information read from the wiring rule information storage means Means, wiring type layer allocation information storage means for storing information obtained by the wiring type layer allocation means, wiring rule information read from the wiring rule information storage means and wiring read from the wiring type layer allocation information storage means Based on the type layer allocation information, the initial lattice spacing information of each layer read from the initial lattice spacing information storage means is assigned to each layer. Wiring grid information generation means for deleting grid information below the specified wiring adjacency prohibition interval, wiring grid information storage means for storing the information generated by the wiring grid information generation means, and connection for storing the connection relation between terminals Wiring for the connection between the terminals read from the connection information storage means by the information storage means and the wiring type layer allocation information read from the wiring type layer allocation information storage means and the wiring grid information read from the wiring grid information storage means A wiring design method for an LSI, comprising: wiring means for performing wiring according to wiring grid information in a layer allocated based on the type of wiring.