JPH05275513A - Semiconductor wafer retaining device - Google Patents

Semiconductor wafer retaining device

Info

Publication number
JPH05275513A
JPH05275513A JP7142992A JP7142992A JPH05275513A JP H05275513 A JPH05275513 A JP H05275513A JP 7142992 A JP7142992 A JP 7142992A JP 7142992 A JP7142992 A JP 7142992A JP H05275513 A JPH05275513 A JP H05275513A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
thin film
wafer retaining
silicon carbide
holding device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7142992A
Other languages
Japanese (ja)
Other versions
JP2854453B2 (en
Inventor
Kazuhiko Mishima
和彦 三嶋
Satoru Okada
哲 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7142992A priority Critical patent/JP2854453B2/en
Publication of JPH05275513A publication Critical patent/JPH05275513A/en
Application granted granted Critical
Publication of JP2854453B2 publication Critical patent/JP2854453B2/en
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  • Gripping Jigs, Holding Jigs, And Positioning Jigs (AREA)
  • Manipulator (AREA)
  • Feeding Of Articles By Means Other Than Belts Or Rollers (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To easily treat a semiconductor wafer in a less contaminated state and, at the same time, to prevent the wafer from being electrostatically charged with electricity by forming the semiconductor wafer retaining surface of a semiconductor wafer retaining device formed of ceramics of a conductive hard thin film. CONSTITUTION:The semiconductor wafer retaining surface of a semiconductor wafer retaining device formed of ceramics having 10<5>-OMEGA.cm volume resistivity is coated with a hard thin film having 10<5>-OMEGA.cm volume resistivity and >=2,000kg/mm<2> Vickers hardness. When the wafer retaining surface is coated with such a hard thin film, the surface can be made smoother by filling up voids on the surface of the base material, namely, ceramics and, at the same time, since the thin film itself is conductive and is not electrostatically charged with electricity, adhesion of dust to the wafer retaining surface can be extremely reduced. In addition, since the thin film is hard having Vickers hardness of >=2,000kg/mm<2>, the wear resistance of the wafer retaining surface can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体ウェハ保持装置
に関し、特に、半導体ウェハを吸着して搬送し、あるい
は半導体ウェハを固定するものについてである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer holding device, and more particularly to a device for sucking and transporting a semiconductor wafer or fixing a semiconductor wafer.

【0002】[0002]

【従来の技術】従来より、半導体ウェハ保持装置として
は、金属あるいは樹脂を使用していたが、剛性、精度、
耐食性、耐熱性、クリーン度の点から問題があって、金
属あるいは樹脂からセラミックの使用へ移行している。
また、実開昭62-72062号公報、特開昭53-96762号公報に
示すように、半導体ウェハを真空吸着して搬送する真空
ピンセットや搬送用アーム、あるいは半導体ウェハを真
空吸着により固定して半導体ウェハを加工、測定する半
導体ウェハ保持装置の材料としてセラミックが用いられ
ている。
2. Description of the Related Art Conventionally, metal or resin has been used as a semiconductor wafer holding device.
There are problems in terms of corrosion resistance, heat resistance, and cleanliness, and the shift from metal or resin to the use of ceramics.
In addition, as disclosed in Japanese Utility Model Laid-Open No. 62-72062 and Japanese Patent Laid-Open No. 53-96762, vacuum tweezers or a transfer arm for vacuum suction and transfer of a semiconductor wafer, or a semiconductor wafer fixed by vacuum suction is used. Ceramic is used as a material of a semiconductor wafer holding device that processes and measures a semiconductor wafer.

【0003】従来は半導体ウェハ保持装置の真空吸着面
にアルミナ、ジルコニア、窒化ケイ素、石英といった材
料を使用しており、特に、炭化ケイ素(SiC)は、半導体
ウェハに対する汚染の少ない材料として多く使用されて
いる。
Conventionally, materials such as alumina, zirconia, silicon nitride, and quartz have been used for the vacuum suction surface of a semiconductor wafer holding device. In particular, silicon carbide (SiC) is often used as a material with less pollution for semiconductor wafers. ing.

【0004】[0004]

【発明が解決しようとする課題】半導体ウェハ保持装置
に用いられるセラミックは、機械加工の容易さと、材料
が安価な点から、アルミナが主に使用されている。これ
に対し、上述の炭化ケイ素SiCは半導体ウェハを汚染し
ない材料であるものの、焼結後の硬度が高く、アルミナ
の約1.25倍の硬度があって難研削材料である。そのた
め、炭化ケイ素SiCを用いた複雑形状の半導体ウェハ保
持装置の加工は非常に困難で、加工コストはアルミナと
比較すると数倍で、炭化ケイ素SiCは材料コストもアル
ミナの数倍〜数十倍となり、総合すると非常に高価なも
のになり、炭化ケイ素SiCを用いた半導体ウェハ保持装
置を製品化することは困難であった。
Alumina is mainly used as the ceramic used in the semiconductor wafer holding device because it is easily machined and the material is inexpensive. On the other hand, although the above-mentioned silicon carbide SiC is a material that does not contaminate a semiconductor wafer, it has a high hardness after sintering, and has a hardness about 1.25 times that of alumina, which makes it difficult to grind. Therefore, it is very difficult to process a semiconductor wafer holding device with a complicated shape using silicon carbide SiC, the processing cost is several times that of alumina, and the material cost of silicon carbide SiC is several times to several tens of times that of alumina. In total, it became very expensive and it was difficult to commercialize a semiconductor wafer holding device using silicon carbide SiC.

【0005】また、半導体ウェハ保持装置にセラミック
が使用されているが、半導体ウェハ保持装置内で半導体
ウェハが静電気によって帯電し、その静電気がセラミッ
クに蓄えられ、ついには、セラミックとの接触時に半導
体ウェハ上の回路が静電破壊を起こしたり、静電力によ
り半導体ウェハがセラミックに静電吸着されてしまい、
行程に支障をきたしたり、さらに、静電気は半導体ウェ
ハに好ましくないパーティクルをセラミックに吸着して
しまう。
Further, although a ceramic is used in the semiconductor wafer holding device, the semiconductor wafer is charged by static electricity in the semiconductor wafer holding device, and the static electricity is stored in the ceramic, and finally, the semiconductor wafer is brought into contact with the ceramic. The upper circuit causes electrostatic breakdown, or the electrostatic force causes the semiconductor wafer to be electrostatically attracted to the ceramic.
The process is hindered, and static electricity adsorbs particles unfavorable to the semiconductor wafer to the ceramic.

【0006】[0006]

【課題を解決するための手段】そこで、第一発明は、上
記の事情に鑑み、汚染が少なく加工を容易にし、かつ静
電気の帯電を防止すべく、半導体ウェハ保持装置にセラ
ミックを用い、その保持面に炭化ケイ素などの体積固有
抵抗105Ω・cm以下の硬質薄膜で被覆するようにした。
In view of the above-mentioned circumstances, the first invention uses ceramics for a semiconductor wafer holding device in order to facilitate the processing with less contamination and to prevent electrostatic charging, and holds the semiconductor wafer holding device. The surface was covered with a hard thin film such as silicon carbide having a volume resistivity of 10 5 Ω · cm or less.

【0007】また、第二発明は、静電気による帯電を防
止するために導電性をもたらすべく、体積固有抵抗が10
5Ω・cm以下の抵抗を有するセラミックを素材とした。
The second invention has a volume resistivity of 10 in order to provide conductivity to prevent electrostatic charge.
Made of ceramics with a resistance of 5 Ω · cm or less.

【0008】[0008]

【作用】第一発明は、セラミックで形成した半導体ウェ
ハ保持装置の半導体ウェハの保持面を炭化ケイ素などの
導電性をもった硬質薄膜で形成したので、所要の硬度が
得られ、その上、加工も可能となり、静電気による帯電
を防止して表面にゴミの付着も少なくなる。
According to the first aspect of the present invention, since the holding surface of the semiconductor wafer of the semiconductor wafer holding device made of ceramic is formed of a hard thin film having conductivity such as silicon carbide, the required hardness can be obtained and further It is also possible to prevent static electricity from being charged and to reduce dust on the surface.

【0009】第二発明は、体積固有抵抗を105Ω・cm以
下の抵抗に設定し、導電性を持たせて静電気による帯電
を防止する。
According to the second aspect of the invention, the volume resistivity is set to a resistance of 10 5 Ω · cm or less, and conductivity is imparted to prevent electrostatic charge.

【0010】[0010]

【実施例】第一発明を添付する図面の具体的な実施例に
基づいて、以下詳細に説明する。図1および図2に示す
半導体ウェハ搬送アーム1は、概略帯板状で、図の左側
が半導体ウェハの吸着面2で、吸着面2に開口した吸着
開口3から導出孔4を経て裏面側に流出開口5が設けら
れている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description will be given below with reference to specific embodiments of the accompanying drawings of the first invention. A semiconductor wafer transfer arm 1 shown in FIGS. 1 and 2 has a substantially band-like shape, and a suction surface 2 of a semiconductor wafer is shown on the left side of the drawing, and a suction opening 3 formed in the suction surface 2 extends from a suction hole 3 to a rear surface side. An outflow opening 5 is provided.

【0011】また、図3および図4に示す真空チャック
11は、概略円盤状で、図3の上面が吸着面12で、吸着面
12に開口した吸着開口13は中心から外周面に流出開口15
を有する導出孔14にそれぞれ連通させる。吸着面12は半
導体ウェハを十分に吸着できるように、吸着面12に円環
状リブ16を膨出させてある。ここで、半導体ウェハ搬送
アーム1および真空チャック11の真空保持装置は、Al2O
3純度99%および99.5%のアルミナセラミックで形成す
る。図中7・17はアルミナセラミックである。そのアル
ミナセラミック7・17の表面には硬質薄膜としてCVD法
で純度99%以上の炭化ケイ素(SiC)の薄膜8・18を形成
した。
Further, the vacuum chuck shown in FIG. 3 and FIG.
11 is a substantially disc shape, and the upper surface of FIG.
The suction opening 13 opened in 12 flows out from the center to the outer peripheral surface 15
The lead-out holes 14 having An annular rib 16 is bulged on the suction surface 12 so that the semiconductor wafer can be sufficiently sucked. Here, the vacuum holding device for the semiconductor wafer transfer arm 1 and the vacuum chuck 11 is made of Al 2 O.
3 Formed from 99% and 99.5% pure alumina ceramics. In the figure, 7 and 17 are alumina ceramics. As a hard thin film, a thin film 8.18 of silicon carbide (SiC) having a purity of 99% or more was formed as a hard thin film on the surface of the alumina ceramics 7.17.

【0012】本実施例においては、炭化ケイ素SiCの薄膜
8・18の膜厚を2〜3μmとした。比較用として、炭化
ケイ素SiCのコーティングなしの99%および99.5%のア
ルミナセラミックの真空保持装置、ステンレス鋼SUS製
の真空保持装置、炭化ケイ素セラミックの真空保持装
置、石英の真空保持装置を用い、アルミナセラミックに
炭化ケイ素の薄膜8・18を形成した本発明の真空保持装
置と共に、半導体ウェハに対するパーティクル検査、す
なわち、ゴミの付着数の測定を行った。
In this embodiment, the film thickness of the silicon carbide SiC thin films 8 and 18 is set to 2 to 3 μm. For comparison, a vacuum holder of 99% and 99.5% alumina ceramics without coating of silicon carbide SiC, a stainless steel SUS vacuum holder, a silicon carbide ceramic vacuum holder, and a quartz vacuum holder were used. With the vacuum holding apparatus of the present invention in which the silicon carbide thin films 8 and 18 were formed on the ceramic, particle inspection was performed on the semiconductor wafer, that is, the number of adhered dust particles was measured.

【0013】実験は、クリーンルーム内とし、半導体ウ
ェハを載置した半導体ウェハ搬送アーム1あるいは真空
チャック11から空気を吸引して半導体ウェハを10秒間吸
着後、空気の吸引を止めて半導体ウェハを5秒間脱着
し、そのサイクルを10回繰り返し、その後、ゴミ検査機
(パーティクル検出機) にてゴミの付着数を測定した。
付着数の基準値を石英へのゴミの付着数とし、その石英
を◎とし、○を石英の1.2倍、△を 1.5倍、×を2倍以
上の付着数とした。それによると、次のような結果とな
り、炭化ケイ素(SiC)の薄膜8・18を形成した本発明実
施例は、ゴミの付着数が極めて少なかった。
The experiment was carried out in a clean room in which air was sucked from the semiconductor wafer transfer arm 1 or the vacuum chuck 11 on which the semiconductor wafer was placed to suck the semiconductor wafer for 10 seconds, and then the suction of the air was stopped to hold the semiconductor wafer for 5 seconds. Detach and repeat the cycle 10 times, then the dust inspection machine
The number of adhering dust particles was measured with a (particle detector).
The reference value of the number of adhered substances was the number of adhered dust particles on the quartz, the quartz was marked as ⊚, the circle was 1.2 times that of quartz, the triangle was 1.5 times, and the mark was twice or more. According to this, the following results were obtained, and in the example of the present invention in which the silicon carbide (SiC) thin films 8.18 were formed, the number of adhered dust was extremely small.

【0014】[0014]

【表1】 [Table 1]

【0015】なお、硬質薄膜として、炭化ケイ素(SiC)
の他、炭化チタン(TiC)、窒化チタン(TiN)を用いること
ができ、その物性は次のとおりである。 このように、本発明における硬質薄膜とは体積固有抵抗
105Ω・cm以下で、ビッカース硬度2000kg/mm2以上のも
のを用いる。この硬質薄膜を被覆することにより、母材
であるセラミックス表面のボイドを埋めて滑らかな面と
することができ、かつ硬質薄膜自体が導電性を有し静電
気の帯電がないためゴミの付着を極めて少なくできる。
しかも、硬質薄膜はビッカース硬度2000kg/mm2以上と高
硬度であり耐磨耗性を高くできる。
As the hard thin film, silicon carbide (SiC)
Besides, titanium carbide (TiC) and titanium nitride (TiN) can be used, and their physical properties are as follows. Thus, the hard thin film in the present invention means the volume resistivity
Use a Vickers hardness of 2000 kg / mm 2 or more at 10 5 Ω · cm or less. By coating this hard thin film, it is possible to fill the voids on the ceramic surface of the base material to form a smooth surface, and because the hard thin film itself has conductivity and is not charged with static electricity, dust adhesion is extremely high. Can be reduced.
Moreover, the hard thin film has a high Vickers hardness of 2000 kg / mm 2 or more, and can have high abrasion resistance.

【0016】また、この硬質薄膜は、PVD法、CVD法など
により母材上に被覆し、その薄膜は0.1〜50μmとす
る。また、母材としてアルミナセラミックの他、ジルコ
ニア、炭化ケイ素、窒化ケイ素などさまざまなセラミッ
クを用いることができる。次に、第二発明について述べ
る。体積固有抵抗が105Ω・cm以下のセラミックは、導
電性を有し静電気を帯電しない。それには、次のような
ものがある。
The hard thin film is coated on the base material by the PVD method, the CVD method or the like, and the thin film has a thickness of 0.1 to 50 μm. In addition to alumina ceramics, various ceramics such as zirconia, silicon carbide, and silicon nitride can be used as the base material. Next, the second invention will be described. Ceramics with a volume resistivity of 10 5 Ω · cm or less have conductivity and do not charge static electricity. These include the following:

【0017】(1) 炭化ケイ素を主成分とするもの。すな
わち、炭化ケイ素(SiC)を主成分とし、ホウ素 (B) 、
炭素 (C) を助剤として固相焼結したもので、体積固有
抵抗は103Ω・cmである。また、炭化ケイ素(SiC)を主成
分とし、Al2O3・Y2O3を助剤として液相焼結したもの
は、体積固有抵抗は8×104Ω・cmで、ビッカース硬度2
400kg/mm2である。
(1) A material containing silicon carbide as a main component. That is, silicon carbide (SiC) as a main component, boron (B),
It is solid-phase sintered with carbon (C) as an auxiliary agent and has a volume resistivity of 10 3 Ω · cm. Moreover, the liquid phase sintered product containing silicon carbide (SiC) as a main component and Al 2 O 3 · Y 2 O 3 as an auxiliary agent has a volume resistivity of 8 × 10 4 Ω · cm and a Vickers hardness of 2
It is 400 kg / mm 2 .

【0018】このようにして高硬度で導電性を高められ
る。 (2) アルミニウム化合物0.1〜10重量%、IIa 族元素とI
IIa族元素の化合物の1種以上が0.1〜10重量%、炭化チ
タン(TiC)、窒化チタン(TiN)などの導電性付与剤が0.1
〜10重量%、残りが炭化ケイ素(SiC)からなる導電性炭
化ケイ素焼結体を素材として、半導体ウェハの検査用装
置の真空チャックを作成した。但し、炭化ケイ素焼結体
は半導体ウェハに悪影響をおよぼす重金属を含まない
か、あるいはごく微量の重金属しか含まれないようにす
る。
In this way, it is possible to enhance the conductivity with high hardness. (2) Aluminum compound 0.1 to 10% by weight, Group IIa element and I
0.1 to 10% by weight of one or more compounds of Group IIa elements, 0.1% by weight of conductivity imparting agents such as titanium carbide (TiC) and titanium nitride (TiN).
A vacuum chuck of an apparatus for inspecting a semiconductor wafer was prepared by using a conductive silicon carbide sintered body composed of ˜10 wt% and the rest being silicon carbide (SiC). However, the silicon carbide sintered body does not contain a heavy metal that adversely affects the semiconductor wafer, or contains a very small amount of heavy metal.

【0019】真空チャックはセラミック製であるので、
その平面度は1μm以上の加工が可能であり、また耐磨
耗性があるため繰り返し使用されても高精度に平面度を
維持できる。この体積固有抵抗は10〜102Ω・cmであ
る。 (3) アルミナ(Al2O3)20〜80重量%、炭化チタン(TiC)80
〜20重量%のアルティックを用いる。例えば、純度90
%以上で平均粒径10μm以下のアルミナ粉末を65重量
%、酸化チタンを含む平均粒径10μm以下の炭化チタン
TiC粉末を28重量%、その他の成分7重量%を混合し、
高純度アルミナボール、高純度ジルコニアボール、高純
度炭化ケイ素SiCボールなどを使用して粒度は10μm以
下、平均粒子径1μm以下に粉砕し混合し原料混合物を
得た。
Since the vacuum chuck is made of ceramic,
The flatness can be processed to 1 μm or more, and since it has abrasion resistance, the flatness can be maintained with high accuracy even if it is repeatedly used. This volume resistivity is 10 to 10 2 Ω · cm. (3) Alumina (Al 2 O 3 ) 20 to 80% by weight, titanium carbide (TiC) 80
Use ~ 20 wt% Altic. For example, purity 90
% Of 65% by weight of alumina powder having an average particle size of 10 μm or less and titanium oxide containing titanium oxide having an average particle size of 10 μm or less
28% by weight of TiC powder and 7% by weight of other components are mixed,
High-purity alumina balls, high-purity zirconia balls, high-purity silicon carbide SiC balls and the like were used to pulverize and mix to a particle size of 10 μm or less and an average particle size of 1 μm or less to obtain a raw material mixture.

【0020】この原料混合物を焼成し、HiP処理を施
し、板状のアルティックを得た。このアルティックの板
材に、図5に示すように、裏面から穴23、穴25、導出溝
24を設け、裏面にSUS板29を張設して半導体ウェハ搬送
用治具21を作成した。この場合、体積固有抵抗は2×10
-2Ω・cmで、ビッカース硬度は1900kg/mm2である。
This raw material mixture was fired and subjected to HiP treatment to obtain a plate-shaped AlTiC. As shown in FIG. 5, the holes 23, the holes 25, and the lead-out grooves are formed on the plate of this Altik from the back surface.
24 was provided, and a SUS plate 29 was stretched on the back surface to prepare a semiconductor wafer transfer jig 21. In this case, the volume resistivity is 2 × 10
It has a Vickers hardness of 1900 kg / mm 2 at -2 Ω · cm.

【0021】図6に示す半導体ウェハ搬送用治具31は、
本体部分40をアルミナなどで作成し、半導体ウェハとの
接触部41のみにアルティックを付する構造とした。アル
ティックはアルミナなどに接着し、本体部分に内蔵した
アース線 (図示せず) に接続する。本体部分40は金属で
構成させてもよいが、比剛性の点からセラミックが好ま
しい。
The semiconductor wafer transfer jig 31 shown in FIG.
The main body portion 40 is made of alumina or the like, and the structure is such that only the contact portion 41 with the semiconductor wafer is provided with the altic. Altic is adhered to alumina or the like and connected to a ground wire (not shown) built in the main body. The body portion 40 may be made of metal, but ceramic is preferable from the viewpoint of specific rigidity.

【0022】体積固有抵抗は2×10-2Ω・cmで、ビッカ
ース硬度1900kg/mm2である。 (4) サーメット 4a、5a族元素の炭化物、窒化物、炭窒化物(TiC、Ti
N、 NbC、 TiCN)50重量%以上と鉄族金属 (Fe、Ni、Co) か
らなる焼結体であって、体積固有抵抗は10-4Ω・cmで、
ビッカース硬度は1650kg/mm2である。
The volume resistivity is 2 × 10 −2 Ω · cm and the Vickers hardness is 1900 kg / mm 2 . (4) Cermet 4a, 5a group carbides, nitrides, carbonitrides (TiC, Ti
N, NbC, TiCN) 50% by weight or more and an iron group metal (Fe, Ni, Co), which has a volume resistivity of 10 -4 Ωcm.
The Vickers hardness is 1650 kg / mm 2 .

【0023】[0023]

【発明の効果】第一発明は、上述のように、セラミック
で形成した半導体ウェハ保持装置において、半導体ウェ
ハの保持面を炭化ケイ素などの体積固有抵抗105Ω・cm
以下の硬質薄膜で被覆した半導体ウェハ保持装置であ
る。アルミナセラミック製の半導体ウェハ保持装置と比
較すると、第一発明の半導体ウェハ保持装置は、パーテ
ィクルの数は減少し、また、炭化ケイ素単体の半導体ウ
ェハ保持装置と同じレベルであった。
As described above, according to the first invention, in the semiconductor wafer holding device formed of ceramic, the holding surface of the semiconductor wafer has a volume resistivity of 10 5 Ω · cm such as silicon carbide.
A semiconductor wafer holding device coated with the following hard thin film. Compared to the semiconductor wafer holding device made of alumina ceramic, the semiconductor wafer holding device of the first invention reduced the number of particles and was at the same level as the semiconductor wafer holding device of silicon carbide alone.

【0024】第一発明の半導体ウェハ保持装置は、炭化
ケイ素単体の半導体ウェハ保持装置と比較して母材がア
ルミナであるため、焼結後の加工も容易で、複雑形状加
工も可能であり、製作が安価となった。第一発明の半導
体ウェハ保持装置は、導電性を有する硬質薄膜を被覆し
ているので、半導体ウェハ搬送などで発生する静電気の
チャージアップの問題も同時に解決された。
Since the base material of the semiconductor wafer holding apparatus of the first invention is alumina as compared with the semiconductor wafer holding apparatus of silicon carbide alone, the processing after sintering is easy and the complicated shape processing is possible. Manufacturing is cheaper. Since the semiconductor wafer holding device of the first invention is coated with a hard thin film having electrical conductivity, the problem of charge-up of static electricity generated during semiconductor wafer transportation etc. was solved at the same time.

【0025】よって、第一発明によって半導体ウェハを
搬送および固定する半導体ウェハ保持装置として優れた
特性の製品が提供できる。第二発明は、上述のように、
体積固有抵抗が105Ω・cm以下の抵抗を有するセラミッ
クを素材としたので、従来のアルミナなどの導電性を有
しないセラミックチャックの場合、検査の前行程の状況
によっては 100枚程度の半導体ウェハを検査しただけで
半導体ウェハの静電吸着が起こり、行程がストップして
しまうが、導電性セラミック製真空チャックを使うこと
により、静電気がチャックに蓄えられることがないた
め、静電吸着されることがなく行程が止まることがな
い。
Therefore, the first invention can provide a product having excellent characteristics as a semiconductor wafer holding device for transporting and fixing a semiconductor wafer. The second invention is, as described above,
Since a ceramic with a volume resistivity of 10 5 Ω · cm or less is used as the material, in the case of a conventional ceramic chuck that does not have conductivity, such as alumina, about 100 semiconductor wafers may be used depending on the situation before the inspection. The electrostatic chuck of the semiconductor wafer will occur just by inspecting the process, and the process will stop, but by using the conductive ceramic vacuum chuck, static electricity will not be stored in the chuck, so it will be electrostatically chucked. There is no end to the process.

【0026】また、従来、スピンドライなど半導体ウェ
ハに静電気が溜まりやすい行程の後の半導体ウェハは、
しばしば半導体ウェハ上の回路が静電破壊されることが
あったため、その防止が必要があったが、第二発明によ
りその必要がなくなった。さらに、露光行程のように、
パーティクルを好まない行程では、特に半導体ウェハ裏
面のパーティクルは避けねばならないが、従来の半導体
ウェハ保持装置では静電気により保持装置上にパーティ
クルを吸着してしまうことがあったが、第二発明ではそ
れがなくなり、パーティクルの減少に役立つ。
Further, conventionally, the semiconductor wafer after the process such as the spin dry where static electricity is likely to be accumulated on the semiconductor wafer is
Since the circuit on the semiconductor wafer was often electrostatically destroyed, it was necessary to prevent it, but the second invention eliminated the need. Furthermore, like the exposure process,
In the process that does not like particles, particles on the back surface of the semiconductor wafer must be avoided in particular, but in the conventional semiconductor wafer holding device, particles may be adsorbed on the holding device by static electricity, but in the second invention it is Helps reduce particles.

【図面の簡単な説明】[Brief description of drawings]

【図1】第一発明の半導体ウェハ搬送アームの平面図で
ある。
FIG. 1 is a plan view of a semiconductor wafer transfer arm of the first invention.

【図2】図1の縦断面図である。FIG. 2 is a vertical sectional view of FIG.

【図3】第一発明の真空チャックの平面図である。FIG. 3 is a plan view of the vacuum chuck of the first invention.

【図4】図3の縦断面図である。4 is a vertical cross-sectional view of FIG.

【図5】第二発明の半導体ウェハ保持装置の斜視図であ
る。
FIG. 5 is a perspective view of a semiconductor wafer holding device according to a second invention.

【図6】第二発明の他の例の半導体ウェハ保持装置の斜
視図である。
FIG. 6 is a perspective view of a semiconductor wafer holding device of another example of the second invention.

【符号の説明】[Explanation of symbols]

1…搬送アーム 11…真空チャック 21…半導体ウェハ搬送用治具 31…半導体ウェハ搬送用治具 7・17…アルミナ 8・18…炭化ケイ素SiC の薄膜 1 ... Transfer arm 11 ... Vacuum chuck 21 ... Semiconductor wafer transfer jig 31 ... Semiconductor wafer transfer jig 7/17 ... Alumina 8.18 ... Silicon carbide SiC thin film

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年3月22日[Submission date] March 22, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0016[Correction target item name] 0016

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0016】また、この硬質薄膜は、PVD法によるイ
オンプレーティング法(蒸着)法やスパッタ法、あるい
は熱、プラズマ、または光によるCVD法などにより母材
上に被覆し、その薄膜は0.1〜50μmとする。また、母
材としてアルミナセラミックの他、ジルコニア、炭化ケ
イ素、窒化ケイ素などさまざまなセラックを用いること
ができる。例えば、母材として炭化ケイ素を使用して、
800℃以上の高温下で熱CVD法により炭化ケイ素を母材上
に被覆することができる。実際に熱CVD法により薄膜を
形成すると、結晶配向性はβ−SiC(111)となり、50μ
m程度またはそれ以上の膜厚が可能であり、母材表面の
ボイドを完全に埋めることができた。また、形成後の薄
膜は、母材と同一材質であるために密着強度が非常に強
く高温時でも剥がれることがなく、緻密であり、しかも
SiC含有量が99.9%さらには99.9999%以上の高純度であ
り、表面を研磨加工した後は平面度が0.3μm以下、ボ
イド率が0となることがわかった。なお、母材も炭化ケ
イ素であるために導電性が非常に良くなり、電気抵抗が
104Ω・cm以下となる。また、熱伝導率も0.04/℃と高
く、半導体ウェハ上での発熱に対して熱を逃がすことが
できる。次に、第二発明について述べる。体積固有抵抗
が105Ω・cm以下のセラミックは、導電性を有し静電気
を帯電しない。それには、次のようなものがある。
The hard thin film is coated on the base material by an ion plating method (vapor deposition) method by the PVD method or a sputtering method, or a CVD method by heat, plasma, or light, and the thin film is 0.1 to 50 μm. And In addition to alumina ceramics, various shellacs such as zirconia, silicon carbide, and silicon nitride can be used as the base material. For example, using silicon carbide as the base material,
Silicon carbide can be coated on a base material by a thermal CVD method at a high temperature of 800 ° C. or higher. When a thin film is actually formed by the thermal CVD method, the crystal orientation becomes β-SiC (111), which is 50μ.
A film thickness of about m or more was possible, and voids on the surface of the base material could be completely filled. Further, since the thin film after formation is the same material as the base material, the adhesion strength is very strong, does not peel off even at high temperature, and is dense, and
It was found that the SiC content was 99.9% or even 99.9999% or higher, and the surface had a flatness of 0.3 μm or less and a void ratio of 0 after polishing. Since the base material is also silicon carbide, the conductivity is very good and the electrical resistance is
10 4 Ω · cm or less. Further, the thermal conductivity is as high as 0.04 / ° C., and the heat can be released to the heat generated on the semiconductor wafer. Next, the second invention will be described. Ceramics with a volume resistivity of 10 5 Ω · cm or less have conductivity and do not charge static electricity. These include the following:

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // B25B 11/00 Z ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display part // B25B 11/00 Z

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミックで形成した半導体ウェハ保持
装置において、半導体ウェハの保持面を体積固有抵抗が
105Ω・cm以下の硬質薄膜で被覆したことを特徴とする
半導体ウェハ保持装置。
1. In a semiconductor wafer holding device formed of ceramic, the holding surface of the semiconductor wafer has a volume resistivity of
A semiconductor wafer holding device characterized by being coated with a hard thin film of 10 5 Ω · cm or less.
【請求項2】 体積固有抵抗が105Ω・cm以下のセラミ
ックで形成したことを特徴とする半導体ウェハ保持装
置。
2. A semiconductor wafer holding device characterized by being formed of a ceramic having a volume resistivity of 10 5 Ω · cm or less.
JP7142992A 1992-03-27 1992-03-27 Semiconductor wafer holding device Expired - Lifetime JP2854453B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7142992A JP2854453B2 (en) 1992-03-27 1992-03-27 Semiconductor wafer holding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7142992A JP2854453B2 (en) 1992-03-27 1992-03-27 Semiconductor wafer holding device

Publications (2)

Publication Number Publication Date
JPH05275513A true JPH05275513A (en) 1993-10-22
JP2854453B2 JP2854453B2 (en) 1999-02-03

Family

ID=13460270

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2854453B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151555A (en) * 1992-11-12 1994-05-31 Mitsui Eng & Shipbuild Co Ltd Semiconductor transfer jig
JPH0745315A (en) * 1993-07-30 1995-02-14 Asahi Glass Co Ltd Static electricity removing member
US5530616A (en) * 1993-11-29 1996-06-25 Toto Ltd. Electrostastic chuck
JP2002015977A (en) * 2000-06-29 2002-01-18 Kyocera Corp Wafer holder
WO2005061188A1 (en) * 2003-12-19 2005-07-07 Matsushita Electric Industrial Co., Ltd. Part mounting head, pick-up nozzle, pick-up nozzle manufacturing method
JP2005255491A (en) * 2004-03-12 2005-09-22 Kyocera Corp Tool for firing and method of manufacturing sintered compact using the same
JP2008263175A (en) * 2007-03-19 2008-10-30 Kyocera Corp Vacuum adsorption nozzle
WO2008133324A1 (en) * 2007-04-25 2008-11-06 Kyocera Corporation Vacuum suction nozzle
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JPS60109859U (en) * 1983-12-28 1985-07-25 株式会社 デイスコ Semiconductor wafer surface grinding equipment
JPH02114441U (en) * 1989-02-28 1990-09-13
JPH0360014A (en) * 1989-07-27 1991-03-15 Kyocera Corp Conductive base substance for picturing device
JPH0415845U (en) * 1990-05-30 1992-02-07
JP3128944U (en) * 2005-11-16 2007-02-01 廖永強 Stand lamp structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109859U (en) * 1983-12-28 1985-07-25 株式会社 デイスコ Semiconductor wafer surface grinding equipment
JPH02114441U (en) * 1989-02-28 1990-09-13
JPH0360014A (en) * 1989-07-27 1991-03-15 Kyocera Corp Conductive base substance for picturing device
JPH0415845U (en) * 1990-05-30 1992-02-07
JP3128944U (en) * 2005-11-16 2007-02-01 廖永強 Stand lamp structure

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JPH06151555A (en) * 1992-11-12 1994-05-31 Mitsui Eng & Shipbuild Co Ltd Semiconductor transfer jig
JPH0745315A (en) * 1993-07-30 1995-02-14 Asahi Glass Co Ltd Static electricity removing member
US5530616A (en) * 1993-11-29 1996-06-25 Toto Ltd. Electrostastic chuck
JP2002015977A (en) * 2000-06-29 2002-01-18 Kyocera Corp Wafer holder
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WO2005061188A1 (en) * 2003-12-19 2005-07-07 Matsushita Electric Industrial Co., Ltd. Part mounting head, pick-up nozzle, pick-up nozzle manufacturing method
JPWO2005061188A1 (en) * 2003-12-19 2007-12-13 松下電器産業株式会社 Component mounting head, suction nozzle, and manufacturing method of suction nozzle
US7886427B2 (en) 2003-12-19 2011-02-15 Panasonic Corporation Component mounting head
JP2005255491A (en) * 2004-03-12 2005-09-22 Kyocera Corp Tool for firing and method of manufacturing sintered compact using the same
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US8112875B2 (en) 2007-04-25 2012-02-14 Kyocera Corporation Vacuum suction nozzle for component mounting apparatus
JPWO2008133324A1 (en) * 2007-04-25 2010-07-29 京セラ株式会社 Vacuum suction nozzle
JP4852645B2 (en) * 2007-04-25 2012-01-11 京セラ株式会社 Vacuum suction nozzle
WO2008133324A1 (en) * 2007-04-25 2008-11-06 Kyocera Corporation Vacuum suction nozzle
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