JPH05274168A - Data processing system controller - Google Patents

Abstract

PURPOSE:To transmit the information on the abnormality detected when one of 1st and 2nd CPU units is started to another CPU with high reliability by providing a communication means consisting of a device different from the device used for the normal communication between both CPU units. CONSTITUTION:A command input part 11 and a system controller 12 are electrically connected to each other by the signal lines 20 and 21 through the ports of the parallel I/O system circuits 5A and 5B respectively. Both CPU 1A and 1B carry out the starting check processing procedures when the power supply is applied. Thus the ROM 2a and 2B, the RAM 3A and 3B, a dual port RAM 4, and the buses 6A and 6B are successively checked. The CPU 1A and 1B perform the mutual communication via the lines 20 and 21 every time the check of each circuit is complete. Thus one of both CPUs transmits the information on the abnormality detected in its starting state to the other CPU.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 5) Problem to be Solved by the Invention (FIG. 5) Means for Solving the Problem (FIG. 5) Action (FIG. 5) Example (FIGS. 1 to 4) effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system control device, and is particularly suitable for application to a data processing system having a plurality of central processing units (CPU).

[0003]

2. Description of the Related Art Conventionally, a central processing unit (CPU) 1A
In 1 and 1B, as shown in FIG.
Only Memory) 2A or 2B and RAM (Randum Acc)
(Ess Memory) A device having CPUs 1A and 1B while forming control signals by using peripheral circuits such as 3A or 3B and communicating with other CPUs 1B or 1A through a communication circuit such as dual port RAM 4 and the like. It is designed to control the movement of.

Therefore, a plurality of Cs such as VTRs are used.
In a device whose operation is controlled by a control system composed of a PU, each CPU 1A and 1B has its own peripheral circuit at the time of reset or power-on of the device in order to prevent malfunction due to an abnormality of the CPU system 7 or 8. Is checked and the communication state with other CPU 1B or 1A is checked, that is, a so-called rising check is performed.

The normal start-up check is, in consideration of the protection of the device when an abnormality is detected and the significance of the check, the ROM 2A or 2B, a partial area of the RAM 3A or 3B used as a stack area, and the dual port RAM 4 in order. And the communication device such as the bus 6A or 6B and the area other than the stack area of the RAM 3A or 3B are checked, respectively.
A and 1B are designed to be able to detect abnormalities in their CPU systems 7 and 8.

[0006]

However, the CPU 1A
And 1B, if there is an abnormality in the dual port RAM 4 or the buses 6A and 6B, which are communication devices even if an abnormality is detected in the startup check, information indicating that the own CPU system 7 or 8 has an abnormality, It is impossible to reliably transmit information (hereinafter, referred to as abnormality detection information) indicating whether an abnormality is detected in the circuit to the CPU 1B or 1A on the partner side.

Therefore, in this case, the CPU 1B of the other party
Alternatively, 1A can only determine that the CPU system 7 or 8 is abnormal, and there is a problem that the check result by the CPU 1A or 1B cannot be used for the subsequent error processing.

The present invention has been made in consideration of the above points, and in a control device configured by connecting a plurality of CPUs by a device used for normal communication, the abnormality detection information at the start-up of each CPU is normally detected. An object of the present invention is to propose a data processing system control device that can reliably transmit to another CPU regardless of whether the device used for communication is good or bad.

[0009]

In order to solve such a problem, according to the present invention, a data processing system control unit 30 constituted by a plurality of central processing units connected by devices 4A, 6A and 6B used for normal communication. , The first and second central processing units 1A and 1B of the plurality of central processing units are the devices 4A, 6A and 6
In addition to the communication means by devices 20 and 21 different from B, each peripheral circuit 2A, 3A,
4A and 6A or 2B, 3B, 4A and 6B are communicated with each other through the communication means 20 and 21 each time the check is completed, so that the abnormality detection information at the rising edge is transmitted to the second or first central processing unit of the other party. It was transmitted to 1B or 1A.

[0010]

Operation: First and second central processing units 1A and 1B
By making each of the peripheral circuits 2A, 3A, 4A and 6A or 2B, 3B, 4A and 6B communicate with each other at the rising edge, the first and second central processing units 1A and 1B are normally operated. Regardless of whether the devices 4A, 6A and 6B used for communication are good or bad, the abnormality detection information can be reliably transmitted to the second or first central processing unit 1B or 1A on the partner side, thus It is possible to realize a data processing system control device capable of performing more appropriate error processing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIGS. 1 and 2 in which parts corresponding to those in FIG. 5 are designated by the same reference numerals, reference numeral 10 generally indicates a control system of a video tape recorder (VTR), each of which is a CPU.
And a command input section 11, a system controller 12, a servo circuit 13, and a signal processing processor 14.

The command input section 11 analyzes a command input by operating a remote controller (not shown) or an operation switch (not shown) arranged on an operation panel, and an operation control signal based on the analysis result. S1 via the dual port RAM 4A to the system controller 12
To send to.

The system controller 12 uses the operation control signal S1 to output the dual port RAM 4B as required.
And 4C, control signals S2 and S3 are sent to the servo circuit 13 and the signal processing processor 14, respectively, thereby controlling the operations of the servo circuit 13 and the signal processing processor 14. The servo circuit 13 and the signal processing processor 14 control the operation of a drive system (not shown) such as a motor and the respective signal processing circuits (not shown) according to the control signal S2 or S3.

In the case of this embodiment, the command input section 11 and the system controller 12 are electrically connected by two signal lines 20 and 21 at the ports of the parallel input / output circuits 5A and 5B as shown in FIG. Has been done.

As the parallel input / output circuits 5A and 5B, programmable ones whose outputs are high impedance when the VTR is turned on are used, and the signal lines 20 and 21 are pulled up by resistors (not shown),
As a result, the signal line 20 when the VTR is powered on
The initial value of the voltage supplied to the parallel input / output circuit 5B or 5A via the output terminals 21 and 21 is set to a predetermined level value H.

In this state, the CPUs 1A and 1B execute the rise check processing procedure RT0 shown in FIG. 3 when the VTR is turned on, and execute the checks of the ROMs 2A and 2B in step SP1.

If no abnormality is detected at this step SP1, the CPU 1A proceeds to step SP2 to set the signal lines 20 and 21 as the output and input lines, respectively, and then proceeds to step SP3 and proceeds to step SP3 of FIG. ), The level of the signal P output from the signal line 20 is converted into a predetermined level value L lower than the H level (time t1). After this, the CPU 1A proceeds to step SP4,
It waits for the level of the signal Q supplied via the signal line 21 to be inverted to the L level.

Similarly, the CPU 1B has this step S
If there is no abnormality at P1, proceed to step SP2 to set the signal lines 20 and 21 as input and output lines respectively, and at the subsequent step SP3, set the signal Q to L.
After converting to the level, the process proceeds to step SP4 and waits for the signal P to be inverted to the L level.

Therefore, the CPUs 1A and 1B are
If there is no abnormality in the OM2B or 2A or the parallel input / output circuits 5B and 5A, it can be confirmed in this step SP4 that the signal P or Q is inverted to the L level, respectively. move on. Subsequently, the CPUs 1A and 1B are respectively connected to the RAM 3A or 3B in this step SP5.
Check the stack area, and if there is no abnormality, proceed to step SP6 to invert the level of the signal P or Q to H level (time t2), and then proceed to step SP7 to invert the level of signal Q or P to H level. Wait to do.

Thus, if there is no abnormality in the stack area of the other side RAM 3B or 3A, the CPUs 1A and 1B can
In this step SP7, the signal P or Q is H, respectively.
You can see it flipping over to the level and thus CP at this time
U1A and 1B proceed to step SP8 to check the dual-pole RAM 4A.

After this, the CPUs 1A and 1B set the step S
In P8 to SP13, the same procedure as the check in the stack area of the RAM 3A or 3B (steps SP5 to SP
7) according to the dual port RAM 4A and R respectively
Areas other than the stack area of AM3A or 3B are sequentially checked. As a result, if no abnormality is detected in any of the check areas, the rising check is ended in step SP14.

On the other hand, when the CPUs 1A and 1B detect an abnormality in the circuit check at step SP1, SP5, SP8 or SP11, as shown in FIG. 4B, the level of the signal P or Q after that is detected. Do not reverse. Therefore, at this time, the other CPU 1B or 1A
Is the next step SP4, SP7, SP10 or SP1
No change in the level of the signal Q or P can be confirmed in the input level check at 3.

Incidentally, in the CPUs 1A and 1B, a predetermined time limit is set for the input level check. Therefore, in this case, the time limit is exceeded (timeout).
Occurs (time t3 + T). Further CPUs 1A and 1
In B, each of them counts and stores the number of level inversions of the input signal (signal Q or P), so that it is possible to know in which circuit check the timeout has occurred.

Thus, at this time, the CPU 1 of the other party concerned
B or 1A stores the rise time check processing procedure RT after memorizing which circuit check has timed out.
Return to 0 and execute this again, then step SP14
At the end of the rising check in, the abnormality detection information is sent to a CPU (not shown) having a display circuit to display it, and the circuit controlled by the CPU 1A or 1B having the abnormality circuit is protected. By V
The TR is controlled so as not to malfunction.

In the above configuration, the CPUs 1A and 1B
When the power of the VTR is turned on, the rising check processing procedure RT0 is executed, and the ROM 2A or 2
Check B (step SP1), and if there is no abnormality, C
The PU 1A sets the signals P and Q to the output line and the input line, respectively, and the CPU 1B sets the signal lines 20 and 21 to the input line and the output line, respectively (step SP2).

Subsequently, the CPUs 1A and 1B invert the output level of the signal P or Q output from the signal lines 20 and 21, respectively, to the L level (step SP3), and at the same time, input the signal P or Q from the signal line 21 or 20. Input level is checked (step SP4), and when it is confirmed that it has been inverted to the L level, the process proceeds to the check of the stack area of the RAM 2A or 2B (step SP5).

If no abnormality is detected here, the CPU 1
A and 1B respectively invert the output level of the signal P or Q to the H level (step SP6) and check the input level of the signal Q or P (step SP7). After that, the CPUs 1A and 1B perform the same procedure (step SP5
~ SP7), dual port RAM4A and RA
The areas other than the stack area of M3A or 3B are sequentially checked (steps SP9 to SP13), and if no abnormality is detected in any of the circuits, the rising check is ended (step SP14).

On the other hand, the CPUs 1A and 1B have one of the circuit checks (steps SP1, SP5, SP8).
Alternatively, when an abnormality is detected in SP11), the output level of the signal P or Q is not changed, and at this time, the partner CPU 1B or 1A stores which circuit is abnormal after a timeout occurs, and then continues the rising check. ..

After this, the CPU 1B or 1A of the other party concerned
Sends an abnormality detection signal to the CPU having a display circuit after all the rising checks are finished to display the abnormality content on a display panel (not shown).

Further, at this time, the counterpart CPU 1B or 1A protects a circuit or the like controlled by the CPU 1A or 1B as necessary, thereby preventing the malfunction of the VTR.

According to the above configuration, the CPUs 1A and 1B
Is a dual port RAM at the start-up check
The abnormality detection information can be reliably transmitted to the CPU 1B or 1A on the other side regardless of whether the communication system such as 4 is good or bad, and when the abnormality is detected, the content of the abnormality is displayed and the VTR concerned due to the abnormality. It is possible to realize a control device capable of performing more detailed measures such as prevention of malfunction of the above.

In the above embodiment, the present invention is applied to V
Although the case where the present invention is applied to the TR control system has been described, the present invention is not limited to this, and in short, can be widely applied to a data processing system having a plurality of CPUs. Further, in the above-described embodiment, the command input unit 11 and the system controller 12
However, the present invention is not limited to this, and may be applied between arbitrary control circuits such as between the system controller 12 and the servo circuit 13 or between the servo circuit 13 and the signal processing processor 14, for example.

Further, in the above embodiment, the signal line P
The case where the initial values of the levels of Q and Q when the power is turned on is the H level has been described. However, the present invention is not limited to this, and
It may be a level.

Further, in the above embodiment, each CPU
Although the case where 1A and 1B execute the rising check at the time of turning on the power of the VTR has been described, the present invention is not limited to this, and each CPU 1A and 1B may execute the rising check processing procedure RT0 at the time of reset.

Further, in the above embodiment, the parallel input / output circuit 6A is used as the communication line for the rising check.
6 and 6B are connected by two signal lines and one input line and one output line are provided.
The present invention is not limited to this, and the point is that if an input line and an output line are provided, the numbers may be two or more, respectively. Furthermore, in the above-described embodiments, the case where the parallel input / output circuit is used has been described, but the present invention is not limited to this, and a serial input / output circuit may be used.

Further, in the above embodiment, the CPU 1
The case where A and 1B receive the abnormality detection information from the CPU 1B or 1A of the other party and performs processing such as transmitting the content of the abnormality to the CPU having the display circuit after the rise check is finished is described. The error processing is not limited to this, and various other processing may be performed.

[0038]

As described above, according to the present invention, in a control device composed of a plurality of central processing units, normal communication is performed between the first and second central processing units of the plurality of central processing units. By providing a communication means by a device different from the device used for the above, and by communicating with each other through the communication means each time the check of each peripheral circuit is completed at the start-up, the first and second central processings are performed. The unit can reliably transmit the abnormality detection information to the second or first central processing unit regardless of whether the device used for normal communication is good or bad at the time of start-up, and thus the abnormality content in the case of the abnormality is detected. It is possible to realize a data processing system control device capable of more appropriately performing error processing such as prevention of malfunction of the entire device due to display and abnormality.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a VTR control system according to an embodiment.

FIG. 2 is a block diagram showing a connection relationship between a command input unit and a system controller shown in FIG.

FIG. 3 is a flow chart showing a rising check processing procedure.

FIG. 4 is a time chart showing changes in the levels of signals P and Q.

FIG. 5 is a block diagram showing a conventional 2CPU control device.

[Explanation of symbols]

1A, 1B ... Central processing unit (CPU), 2A, 2
B ... ROM, 3A, 3B ... RAM, 4, 4A, 4
B, 4C ... Dual port RAM, 5A, 5B ... Parallel input / output circuit, 6A, 6B ... Bus, 10 ... Control system, 11 ... Command input section, 12 ... System controller, 20, 21 ... Signal line, P, Q ... Signal.

Claims (1)

[Claims] 1. A data processing system controller comprising a plurality of central processing units connected by devices used for normal communication, wherein the first and second central processing units of the plurality of central processing units are the above-mentioned ones. The communication means is provided by a device different from the device, and communicates with each other via the communication means each time the check of each peripheral circuit is completed at the start-up, so that the abnormality detection information at the start-up can be transmitted to the other party. A data processing system control device, characterized in that the data is transmitted to the second or first central processing unit.