JPH05268410A - Linear sensor - Google Patents

Abstract

PURPOSE:To obtain a linear sensor by which an invalid signal period between lines is minimized when an output signal is continuously read and shortening the shortest storage time to the same degree of time as the read time of a signal charge from a sensor section. CONSTITUTION:Drain diffusion regions 41-43 are provided on an opposite side of HCCD 21-23 with respect to sensor arrays 11-13 and transfer gates 51-53 are provided between the sensor arrays 11-13 and the drain diffusion regions 41-43 at every line. Lateral shutter structure is adopted at every line, in which an undesired charge stored in each picture element of the sensor arrays 11-13 is swept out respectively to the drain diffusion regions 41-43. Furthermore, each driving timing of shift gates 31-33 and the transfer gates 51-53 is set independently between lines and an exposed time is optionally set between lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear sensor, and more particularly to a linear sensor having a so-called horizontal shutter function.

[0002]

2. Description of the Related Art As a linear sensor, a linear sensor in which a plurality of lines, for example, three lines, which are used in an image information input section of a color image scanner, a digital color copying machine or the like, is known is known. In this 3-line linear sensor, it is better to derive the output signal of each line from one location, because it is necessary to use 3 lines for each line in order to simplify the signal processing system.
It is advantageous over deriving the output signal from the location.

FIG. 5 shows a conventional example of a linear sensor in which each output signal of three lines is derived from one location. In the figure, three analog shift registers 2 ₁ to 2 ₃
On the output side of the switch for each line SW1-S
W3 is arranged, and these changeover switches SW1 to SW1
By sequentially controlling the switching of SW3, the signal of each line is sequentially derived. 2 in FIG.
Phase transfer clocks φ1, φ2, shift gates 3 _{1 to} 3
₃ shows the timing relationship between the _three read pulses φrog1 to φlog3 and the output signal Vout. The period t
_int is a signal charge storage time for each line.

[0004]

In the above-described conventional 3-line linear sensor, the analog shift registers 2 ₁ ...
When the transfer clocks φ1 and φ2 of 2 ₃ are made common, the analog shift registers 2 ₁ to 2 ₃ can be used to sweep away the unnecessary charges accumulated in the sensor section when the output signal is continuously read. Therefore, if it is necessary to shorten the accumulation time of the optical signal charges, the transfer clock φ1,
High-speed transfer by φ2 is required. As a result, no signal can be output during the unnecessary charge sweep-out period, and an invalid signal period between lines is generated. In this invalid signal period, a photo signal charge accumulation time and unnecessary charge transfer time are required. In other words, the photo signal charge accumulation time t _int and the unnecessary charge transfer time become an invalid signal period between the lines.

Further, the transfer clocks .phi.1, the clock frequency at the time of high-speed transfer of .phi.2, for thereby determined the shortest storage time, the shortest storage time increases the number of pixels the sensor array 1 ₁ to 1 ₃ is large, a wide range of It becomes impossible to deal with the amount of light. For example, the sensor array ₁ 1 to 1 ₃ of each line is 1000
In the case of a linear sensor consisting of pixels, high-speed transfer is 10 MHz
Even in the case of z, the transfer time of 100 μsec is required for the unnecessary charge transfer, and the shortest accumulation time is as long as 100 μsec.

The present invention has been made in view of the above points, and when an output signal is continuously read,
An object of the present invention is to provide a linear sensor in which the invalid signal period between lines can be minimized and the shortest storage time can be made as small as the readout time of signal charges from the sensor unit.

[0007]

A linear sensor according to the present invention is provided with a plurality of sensor rows each consisting of a predetermined number of pixels arranged one-dimensionally in the horizontal direction and a signal provided in correspondence with the plurality of sensor rows. A plurality of horizontal transfer registers for transferring charges in the horizontal direction, a plurality of shift gates for transferring signal charges accumulated in each pixel of a plurality of sensor columns to a plurality of horizontal transfer registers, and a plurality of sensor gates for a plurality of sensor columns. , A plurality of drain diffusion regions provided on the opposite side of the horizontal transfer register, and a plurality of transfer gates for sweeping unnecessary charges accumulated in each pixel of a plurality of sensor columns to the plurality of drain diffusion regions, respectively. A structure having a structure of a plurality of lines on the same substrate and including a drive circuit capable of independently setting each drive timing of a shift gate and a transfer gate among a plurality of lines Going on.

[0008]

In a linear sensor having a plurality of lines on the same substrate, a horizontal transfer register for each line is commonly driven for all lines, and a final output from the substrate is derived from one place, a so-called horizontal shutter structure is provided. Is provided for each line, the invalid signal period between the lines can be minimized, and the shortest accumulation time can be shortened because it is determined by the signal charge read time from the sensor unit. In addition, by setting the drive timings of the shift gates and transfer gates of each line independently among multiple lines,
The exposure time (optical signal charge storage time) can be set for each line, and in the case of a 3-line linear sensor, each line must correspond to each of the three primary colors (R, G, B). Thus, the sensitivity difference between the R, G, and B filters can be corrected.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and shows a case where the present invention is applied to a 3-line linear sensor used in an image information input unit of a color image scanner, a digital color copying machine or the like. In the figure, a sensor array 1 is composed of a predetermined number of pixels that are arranged one-dimensionally in the horizontal direction (H direction) and is arranged in three lines in the vertical direction (V direction).
A ₁ to 1 _3, CCD for transferring signal charges in the H direction (CHARG
analog shift register (hereinafter referred to as HCCD) 2 ₁ to 2 _{3 including an} e-coupled device and a sensor array 1
The ₁ to 1 ₃ of the signal charge accumulated in each pixel HCCD2 ₁
The shift gates 3 ₁ to _{3 3} which are respectively transferred to 2 to 2 ₃ compose the basic structure of a 3-line linear sensor.

In the present invention, in addition to this basic structure, the drain diffusion region 41 _{to 3} provided to the sensor array ₁ 1 to 1 ₃ opposite the HCCD2 ₁ to 2 _3, further sensor array 1 ₁ to 1 ₃ and the drain diffusion region 4 _{1-4 3}
Between, the sensor array 1 ₁ to 1 drain diffusion region the accumulated unnecessary charge in each pixel of ₃ 41 _{to 3} in sweeping each transfer gate 5 ₁ to 5 ₃ are provided. With the above configuration, the linear sensor according to the present invention has a structure in which three lines of the linear sensor with a horizontal shutter function are provided on the same substrate.

[0011] HCCD2 ₁ ~2 ₃ signal charges transferred respectively in, into a voltage by the charge / voltage converter ₆₁ through ₃ of the provided with e.g. a floating diffusion amplifier structure on the output side of the HCCD2 ₁ ~2 ₃ Converted (or reset). The output signal of each line is continuously read out for each line by switching control of the changeover switches SW1 to SW3, and is derived as a signal output Vout from one location via the amplifier 7.

HCCD 2 _{1 to} 2 ₃ and shift gate 3 ₁ to
A drive circuit 8 including a timing generator (not shown) is provided to drive 3 ₃ and the transfer gates 5 _{1 to} 5 ₃ . This drive circuit 8 is a 3-line HCCD
The transfer clocks φ1 and φ2 of a plurality of phases (two phases in this example) are commonly used for all the lines 2 _{1 to} 2 _{3 and the} read gate pulse φrog ₁ to the shift gates 3 ₁ to ₃ 3 of the _three lines. the ～Fairog3, respectively supply transfer gate pulse φs1~φs3 for transfer gate 5 ₁ to 5 ₃ 3 line. Furthermore, the drain diffusion region 4 _{1-4 3,} DC bias Vsd is applied.

FIG. 2 shows a cross section taken along the line XY in FIG. In this example, the N-type silicon substrate 11 and the P well 12 are
In order to improve the sensitivity and reduce the dark current, the sensor section 13 has a hole accumulating structure of the P ⁺ type region in the NP photodiode. This sensor unit 13
A shift gate 3 ₁ formed of an N ⁻ type region is formed adjacent to, and a gate electrode 14 to which a read gate pulse φrog1 is applied is arranged above the shift gate 3 ₁ via an insulating film (not shown). Further, an HCCD 2 ₁ composed of an N-type region is formed adjacent to the shift gate 3 _1, and a transfer electrode 15 to which a transfer gate pulse φs 1 is applied is arranged above the HCCD 2 ₁ via an insulating film.

On the other hand, a transfer gate 5 ₁ formed of an N ⁻ type region is formed on the side opposite to the shift gate 3 ₁ with respect to the sensor portion 13, and above the gate electrode 16 to which a transfer gate pulse φs 1 is applied. Are arranged via an insulating film.
Further, the transfer gate 5 ₁ has a drain diffusion region 4 ₁ formed of an N ⁺ region, and a DC bias Vsd is applied to the drain diffusion region 4 ₁ .

Next, the operation of the 3-line linear sensor having the above structure will be described with reference to the potential diagram of FIG. 3 and the timing chart of FIG. Note that the potential diagram of FIG. 3 is the time t ₁ of the timing chart of FIG.
The potential corresponding to the sectional structure of FIG. ₂ at t ₂ is shown. First, when the transfer gate pulse φs1 is generated to sweep away the unnecessary charges at time t ₁ and the potential of the transfer gate 5 ₁ becomes high level, the potential under the transfer gate 5 ₁ becomes deep as shown by the solid line in FIG. Therefore, the sensor unit 1
Charges accumulated in the 3, is transferred to the drain diffusion region 4 ₁ as shown by the solid line in FIG. 3.

Next, at time t ₂ , the transfer gate 5 ₁
While the potential of the lower becomes shallower as shown by a dotted line in FIG. 3, the read gate pulse φrog1 occurs, shift gate 3 ₁ potential becomes high, the shift gate 3 ₁ below the potential becomes deeper as shown by a dotted line in FIG. 3 Therefore, the sensor unit 1
The optical signal charge accumulated in 3 is H as shown by the dotted line in FIG.
Transferred to CCD2 ₁ .

Here, the accumulation time tint of the optical signal charge is
The time from the fall of the transfer gate pulse φs1 to the fall of the read gate pulse φrog1 is independent of the frequencies of the transfer clocks φ1 and φ2 and the number of pixels in each line. Regarding the shortest storage time, read gate pulse φro
The pulse width of g1 can be reduced to the same extent as the readout time of the optical signal charge from the sensor unit 13.

As described above, since the horizontal shutter function is provided for each line, when the output signal of each line is to be read continuously, unnecessary charges are swept away by the shutter function for each line. Because you can
The high-speed transfer clock as in the past becomes unnecessary,
As is clear from the waveform of the output Vout in FIG. 4, it is possible to make the invalid signal period between the lines almost zero. In addition, the low level of the transfer gate pulses φs1 to φs3 (Vs-L
It is also possible to control the overflow level at the sensor unit 13 by adjusting o).

Further, the read gate pulse φrog1 is applied to the shift gates 3 _{1 to} 3 ₃ and the transfer gates 5 _{1 to} 5 _3.
.About..phi.rog3 and transfer gate pulses .phi.s1 to .phi.s3 are individually supplied, and the driving timings can be set independently for each line, so that the accumulation time tint of the optical signal charge, that is, the exposure time can be set for each line. It can be set arbitrarily. Further, since the exposure time can be set for each line, when applied to a 3-line color linear sensor in which each of the sensor rows 1 ₁ to ₁₃ is associated with each of the _three primary colors (R, G, B), It is also possible to correct the sensitivity difference between the R, G, B color filters.

In the above embodiment, the HCCD 2
_{The case} where the charge / voltage detectors 6 _{1 to} 6 ₃ are provided on the respective output sides of _{1 to} 2 _{3 and} the respective output signals are derived by the switching control by the changeover switches SW _{1 to} SW ₃ has been described. construction of parts are not limited to, for example, the VCCD for transferring signal charges by the transfer of HCCD2 ₁ ~2 ₃ vertically HC
Provided on the output side of the CD2 ₁ to 2 _3, also it is applied as a structure for deriving an output signal from one location provided single charge / voltage conversion unit to the output side of the VCCD.

In the above embodiment, the read gate pulses φrog1 to φrog3 and the transfer gate pulses φs1 to φs3 are supplied from the external drive circuit 8. However, only one read gate pulse and one transfer gate pulse are externally supplied. Alternatively, the gate pulses φrog1 to φrog3 and φs1 to φs3 for three lines may be supplied by the internal logic circuit or the like.

[0022]

As described above, according to the present invention,
In a linear sensor with multiple lines on the same substrate, the horizontal transfer register for each line is commonly driven for all lines, and the final output from the substrate is derived from one location, a horizontal shutter structure is provided for each line. Since it is not necessary to use a horizontal transfer register to sweep away unnecessary charges accumulated in the sensor section, the invalid signal period between each line can be minimized and the shortest accumulation time can be achieved. Also has the effect that it can be made as small as the reading time of the signal charge from the sensor section.

Furthermore, since the drive timings of the shift gates and transfer gates of each line are set independently for a plurality of lines, the exposure time can be set for each line, and accordingly, the exposure time can be set to 3 In the case of a line linear sensor, each line is made to correspond to each color of R, G, and B, and there is also an effect that the sensitivity difference of each filter can be corrected.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to a 3-line linear sensor.

FIG. 2 is a sectional view taken along line XY in FIG.

FIG. 3 is a potential diagram corresponding to the sectional structure of FIG.

FIG. 4 is a timing chart for explaining the operation of the present invention.

FIG. 5 is a configuration diagram showing a conventional example.

FIG. 6 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

1 ₁ to 1 ₃ sensor array 2 ₁ to 2 ₃ CCD analog shift register (HCC
D) 3 _{1 to} 3 ₃ shift gate 4 ₁ to 4 ₃ drain diffusion region 5 _{1 to} 5 ₃ transfer gate 6 charge / voltage conversion unit 8 drive circuit 11 N-type silicon substrate 13 sensor unit 15 transfer electrode

Claims (2)

[Claims] 1. A plurality of sensor rows each composed of a predetermined number of pixels arranged one-dimensionally in the horizontal direction, and a plurality of horizontal transfers provided corresponding to the plurality of sensor rows to transfer signal charges in the horizontal direction. A register, a plurality of shift gates for respectively transferring the signal charges accumulated in each pixel of the plurality of sensor rows to the plurality of horizontal transfer registers, and a side opposite to the plurality of horizontal transfer registers for the plurality of sensor rows A plurality of drain diffusion regions, and a plurality of transfer gates for sweeping unnecessary charges accumulated in each pixel of the plurality of sensor columns into the plurality of drain diffusion regions A driving circuit which is provided on the same substrate and is capable of independently setting drive timings of the shift gate and the transfer gate among a plurality of lines. Linear sensor that. 2. The linear sensor according to claim 1, wherein the plurality of lines are three lines, and each sensor row of the three lines corresponds to each of the three primary colors.