JPH0269082A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To reduce burdens of shift registers and, at the same time, to constitute an output signal process circuit on one chip by providing plural horizontal shift registers and plural output signal lines to each horizontal shift register so that signal charges can be read out alternately from each horizontal shift register. CONSTITUTION:Photodiodes, for example, photodiodes 11-15 associated with a vertical selection line selected by a vertical shift register 2 are scanned by a horizontal shift register 3 and the signal charge of the photodiode 11 is outputted to a output signal line 5. The the photodiode 12 on the 2nd row is scanned by a horizontal shift register 4 and the signal charge of the photodiode 12 is outputted to a signal output line 7. The signal charge outputted to the signal output line 7 is shifted in phase by 90 deg. against the output signal line 5. Similar operations are also performed to the 3rd and 4th rows. As a result, when the drive frequency of each horizontal shift register 3 and 4 is reduced to 1/4, the burden to each horizontal shift register can be reduced and circuit design can be made simpler.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a solid-state image sensor, and more specifically, it suppresses the increase in operating frequency when increasing the number of pixels, and reduces the burden on shift registers. The present invention relates to a MOS solid-state image sensor.

(Prior art) Conventionally, MOS type solid-state image sensors have been used as X-Y address type devices that read out photoelectric conversion signals accumulated in photodiodes in time series through two-dimensionally arranged MOS transistors (hereinafter abbreviated as MO3Tr). It is well known. Compared to other types of elements, this element is able to turn on the MOS Tr,
Since an output is obtained when the device is off, it can be driven at a low voltage, and has operational features such as a small load and easy driving.

The present inventors previously disclosed in Japanese Patent Application No. 61-84038, in order to measure the three-color density of a color original with high precision,
We proposed a MOS type photometric sensor that allows the charge accumulation time of each pixel to be set for each color. This sensor has a configuration in which a plurality of vertical signal lines attached to each column of photodiodes are provided, and a plurality of vertical scanning circuits are connected to drive each vertical signal line at different drive timings.

(Problems to be Solved by the Invention) By the way, a configuration in which a plurality of output signal lines are provided instead of the vertical signal line can also be considered. However, in the case of the output signal line, the operating frequency has increased due to an increase in the number of pixels or a faster horizontal readout speed, which has increased the burden on the shift register. Further, this resulted in a decrease in the gain of the preamplifier or a deterioration in S/N.

The present inventors also considered an element whose performance can be improved by providing output signal processing circuits such as integration and amplification within one chip. However, considering the conventional readout rate elements, the operating frequency is high, making the output signal processing circuit complex for color separation and the like.

The purpose of the present invention was made in view of the above circumstances, and it is possible to suppress the increase in operating frequency even when the number of pixels increases, reduce the burden on the shift register, and also enable integration with the output signal processing circuit into a single chip. The object of the present invention is to provide a solid-state imaging device that has a

(Means and effects for solving the problem) That is, the object of the present invention is to provide a plurality of photoelectric conversion elements arranged in a matrix, vertical switches attached to these photoelectric conversion elements, and a plurality of vertical switches attached to one row of vertical switches. In an MO3 surface gymnastics image element consisting of a horizontal switch, a vertical shift register that controls the vertical switch, and a horizontal shift register that controls the horizontal switch, the horizontal shift register is composed of a plurality of shift registers that are shifted by clock signals having different phases. Each of the plurality of shift registers has a plurality of output signal lines and selectively selects each column of vertical signal lines connected to the vertical switch, and each selected vertical signal line has a plurality of output signal lines. This is achieved by a solid-state imaging device characterized by being sequentially distributed and connected to a plurality of output signal lines.

According to the above configuration, since a plurality of horizontal shift registers are provided and each horizontal shift register has a plurality of output signal lines, for example, by reading out signal charges from each horizontal shift register alternately, Even in pixelization, it is possible to read out signals at the same data rate by slowing down the driving frequency of each horizontal shift register.

Note that, for example, when two shift registers are provided and each shift register is provided with two output signal lines, the shift registers can be driven at an operating frequency that is 1/4 of the data read rate.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In this embodiment, a case will be explained in which there are two horizontal shift registers and four output signal lines.

FIG. 1 schematically shows the configuration of a solid-state image sensor according to the present invention, in which a light receiving section 1, a vertical shift register 2, and horizontal shift registers 3 and 4 are each shown as one block. The horizontal shift registers 3 and 4 are connected to the light receiving section 1
The two output signal lines 5, 6 and 7, 8 are disposed at opposite positions with the two output signal lines 5, 6, and 7, 8 being provided, respectively.

The horizontal shift registers 3 and 4 receive clock signals H,
,, H, □ and H2+1 H2□, and the driving is started by start pulses Hinl and Hin2, respectively.

FIG. 2 equivalently shows the circuit of the solid-state image sensor of the present invention shown in FIG.

In the figure, photodiodes 11 to 15, 21 to 25, and 31 to 35 forming photoelectric conversion elements are arranged in a matrix, and in order to read out the signal charges accumulated in these photodiodes, MOS FETs are formed. vertical switch 51~55°61~65.71~7
5 are connected in series to each photodiode.

In order to turn on the vertical switches 51 to 55 in the first row, their gates are connected to a vertical selection line 101 connected to the output terminal D1 of the first stage of the vertical shift register 2.

Further, in order to turn on the vertical switches 61 to 65 in the second row, their gates are connected to the vertical selection line 102 connected to the output terminal D2 of the second stage of the vertical shift register 2.
It is connected to the. Since the third and subsequent lines are similar to this, only the reference numerals are given and the explanation thereof will be omitted.

On the other hand, a vertical signal line 111 for each column of photodiodes
．． 112, 113, 114, and 115 are wired, respectively. That is, the first row of photodiodes 51,
A vertical signal line 111 is connected to the vertical signal line 61.71, and the drain of a vertical switch 51.61.71 corresponding to each photodiode is connected to the vertical signal line 111.

Further, a vertical signal line 112 is connected to the photodiode 52.62.72 in the second column, and a vertical switch 52.62.72 corresponding to each photodiode is connected to the vertical signal line 112. Drain is connected.

Similarly, the photodiode in the third row is 53.63°73
A vertical signal line 113 is connected to the vertical signal line 113, and the drains of vertical switches 53, 63, and 73 corresponding to the respective photodiodes are connected to the vertical signal line 113. The same applies to the fourth and subsequent columns, and the explanation will be omitted.

The signal charges transferred to the vertical signal lines 111-115 are read out to each output signal line 5.6, 7, and 8 via the horizontal switches 121-123, 131.132, respectively.

At this time, vertical signal lines 111 to 115 are connected to horizontal switches 121 to 12 attached to each vertical shift register 3, 4, respectively.
3 and 131, 132,
In addition, the vertical signal lines 111 to 115 selected by the same horizontal shift register 3 or 4 are connected to the respective output signal lines 5.
, 6 or 7°8. That is, a horizontal switch 121 controlled by the horizontal shift register 3 is connected in series to the vertical signal line 111 in the first column, and the drain of the horizontal switch 121 is connected to the output signal line 5.

Note that the gate of the horizontal switch 12 is connected to the first stage output terminal F1 of the horizontal shift register 3.

Furthermore, a horizontal switch 131 that is connected to and controlled by the output terminal G1 of the first stage of the horizontal shift register 4 is connected in series to the vertical signal line 112 of the second column. is connected to the output signal line 7.

Similarly, a horizontal switch 122 connected to and controlled by the output terminal F2 of the second stage of the horizontal shift register 3 is connected in series to the vertical signal line 113 in the third column. The drain is connected to the output signal line 6.

Further, a horizontal switch 132 connected to and controlled by the output terminal G2 of the second stage of the horizontal shift register 4 is connected in series to the vertical signal line 114 in the fourth column. is connected to the output signal line 8.

The vertical signal lines in the fifth and subsequent columns are provided by repeating the connections shown in the vertical signal lines 111 to 114 in the first to fourth columns.

Next, the read timing of the output signal will be explained with reference to FIG.

Note that FIG. 3 shows the current output from each signal output line 5, 6, 7.8 as having been subjected to integral processing by an external signal processing circuit. Further, each horizontal shift register 3, 4 receives clock signals H10, Hl 2 , H211H2 shown in FIG.
2, and each clock signal H11
and HI 2, H21 and H22 each have a phase of 18
It's off by 0°. Therefore, returning to FIG. 3, the photodiode attached to the vertical selection line selected by the vertical shift register 2, for example 11. 12. 13. 14.1
5 is further scanned by the horizontal shift register 3, and the signal charge of the photodiode 11 is output to the output signal line 5. Next, the photodiode 12 in the second column is scanned by the horizontal shift register 4, and the signal charge is transferred to the signal output line 7.
is output to. At this time, the phase of the signal charge output to the signal output line 7 is shifted by 90 degrees with respect to the output signal line 5. Further, the photodiodes 13 in the third column are scanned by the horizontal shift register 3, and signal charges are output to the signal output line 6. At this time, similarly, the phase of the signal charges output to the signal output line 6 is shifted by 90° with respect to the output signal line 7. Next, the photodiode 14 in the fourth column is scanned by the horizontal shift register 4, and the signal charge is output to the signal output line 8. Similarly, the signal charge output to the signal output line 8 is shifted in phase by 90° with respect to the output signal line 6. In this way, when the first row of vertical selection lines 101 are sequentially scanned, the second row of vertical selection lines 101 is sequentially scanned.
The vertical selection lines 102 in the row are sequentially scanned in the same manner.

When the entire light-receiving section 1 is scanned by repeating the above-mentioned scanning and the signal charges are outputted via each output signal line 5, 6°7.8, these signal charges are added by an external signal processing circuit, and the conventional element A signal charge similar to that is formed.

(Effects of the Invention) With the above configuration, the driving frequency of each horizontal shift register 3, 4 can be reduced to 1/4, and the load on each horizontal shift register 3, 4 can be reduced. Further, although the number of signal processing circuits is increased, the driving frequency is reduced to 1/4, which simplifies the circuit design.

Furthermore, these signal processing circuits can be formed within the same chip.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a solid-state image sensor according to an embodiment of the present invention, FIG. 2 is a circuit diagram of FIG. 1, FIG. 3 is a timing diagram explaining the correlation between the outputs of each signal output line, and FIG. The figure is a timing diagram showing clock signals of the horizontal shift register. l: Light receiving section, 2: Vertical shift register, 3
．． 4: Horizontal shift register, 5, 6. 7. 3: Output signal line, 11-15.21-25.31-35: Photodiode, 51-55.61-65.71-75: Vertical switch, 101-103: Vertical selection line, 111-115: Vertical signal line,

Claims (1)

[Claims] A plurality of photoelectric conversion elements arranged in a matrix, vertical switches attached to these photoelectric conversion elements, horizontal switches attached to one row of vertical switches, a vertical shift register that controls the vertical switches, and a horizontal shift register that controls the horizontal switches. In a MOS type solid-state image sensing device consisting of a register, a horizontal shift register consists of a plurality of shift registers shifted by clock signals having different phases,
Each of the plurality of shift registers has a plurality of output signal lines and selectively selects each column of vertical signal lines connected to the vertical switch, and each selected vertical signal line is connected to the plurality of output signal lines. What is claimed is: 1. A solid-state imaging device characterized in that the signals are sequentially distributed and connected to the output signal lines of the device.