JPH05268039A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To improve a problem in a conventional buffer circuit that a large current flows to the buffer circuit at charge/discharge of a load capacitance and a level of a power supply and a ground point GND is made unstable thereby causing malfunction because a gm of a transistor (TR) is selected larger to attain a high speed operation of an output. CONSTITUTION:A P-channel transistor(TR) 4 in current mirror connection with a P-channel TR 6 of the output buffer circuit is provided and N-channel TRs 1,3 to control a current flowing to the TRs 6,4 and P-channel TRs 5,2 and an N-channel TR 12 for cut off are provided. An N-channel TR 10 in current mirror connection with the TR 12 is provided, P-channel TRs 7,9 controlling the current flowing to them are provided and N-channel TRs 8,11 for cut off are provided. Furthermore, the buffer circuit acts like a tri-state buffer by adding a logic circuit to the input. Since the output current is controlled by the circuit as above, malfunction due to unstable states in the power supply/ GND level is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit having a circuit capable of controlling an output current value.

[0002]

2. Description of the Related Art In a conventional output buffer circuit, as shown in FIG. 3, an input signal IN is input to an inverter circuit 18, and its output is a P channel type transistor (PchTr) whose source is connected to a constant voltage VDD. 6 is an N-channel transistor (N
chTr) 12 and a common drain, and output to the outside.

The operation of the circuit shown in FIG. 3 will be described with reference to FIG.
3 and 5, when the input signal IN is at low level (hereinafter "L"), the output INB of the inverter circuit 18 is at high level (hereinafter "H"), PchTr6 is off, and Nch is
The Tr12 is in the ON state, and the output o of the external terminal 13 becomes "L".

Next, the input signal IN changes from "L" to "H".
Output INB of the inverter circuit 18 changes from “H” to “L”, PchTr6 changes from off to on, NchTr12 changes from on to off, and the output of the external terminal 13 charges the load capacitance CL. Meanwhile, it changes from "L" to "H". At this time, VDD to PchTr6
A large current Im transiently flows out from VDD to charge CL through. The output o holds "H" while the input signal IN holds "H".

When the input signal IN changes from "H" to "L", the output INB of the inverter circuit 18 changes from "L" to "H", the PchTr6 turns from ON to OFF, Nc.
When the hTr12 changes from off to on, the external terminal 1
The output o of 3 changes from “H” to “L” while discharging the charge of the load capacitance CL. At this time, the electric charge charged in CL is discharged to GND through the NchTr 12, and a large current In transiently flows into GND.

4 is different from the circuit of FIG. 3 described above, the NAND circuit 19 to which the input signal IN and the control signal C are input, the inverter circuit 20 for producing the control signal C (inverted value), and the input signal. A conventional output buffer circuit that operates as a three-state buffer by using a NOR circuit 21 to which IN and a control signal C (inverted value) are input instead of the inverter 18 and controlling PchTr6 and NchTr12 respectively Is an example.

The circuit operation of FIG. 4 operates as shown in the signal waveform diagram of FIG. 6, and like the circuit of FIG. 3, when the control signal C is "H", the input signal IN is from "L" to "H". , "H" to "L"
Output terminal 13 output changes from "L" to "H",
It changes from "H" to "L", and a large current transiently produces a constant voltage V
Flow from DD or to ground GND.

[0008]

In recent years, the output buffer tends to have a large gm in order to operate at high speed, and a large current transiently flows when the load capacitance of the external terminal is charged / discharged.

Further, it is ideal that the power supply line and the GND line have a resistance value of zero ohm, but in reality, there is a resistance of several ohms to tens of ohms.

Therefore, a large current flowing during charging / discharging of the output buffer causes a potential difference between the power supply line and the ground line. There is a problem that this potential difference causes a malfunction in a circuit including the output buffer circuit.

An object of the present invention is to solve the above problems and to provide an output buffer circuit in which malfunction of the circuit due to large current is not induced.

[0012]

According to the structure of the output buffer circuit of the present invention, the first input signal is input to the first current source and the second current source, and the first current source is the first current source. Connected to an external terminal of the first current mirror circuit, and a third current source for inputting the first input signal and an output signal of the external terminal is connected to the first current. A mirror circuit, the second current source is connected to a second current mirror circuit, the second current mirror circuit is connected to the external terminal, and the first input signal and the output of the external terminal are connected. A fourth current source for inputting a signal and is connected to the second current mirror circuit.

[0013]

1 is a circuit diagram showing an output buffer circuit according to a first embodiment of the present invention.

In FIG. 1, in the output buffer circuit of the first embodiment of the present invention, an input signal IN is input to the gates of N-channel type transistors (NchTr) 1 and NchTr3.

The drain of NchTr2 and the source of NchTr3 are connected, and the drain of NchTr1 and the NchTr3 are connected.
The drain of Tr2 is connected. The source of PchTr4 is connected to the power supply, and the gate and drain of NchT4 are connected.
connected to the drain of r1. The source of PchTr6 is connected to the power supply, and the gate is connected to the gate of PchTr4.

The drain of PchTr6 is the output terminal 1
3 is connected to the gate of NchTr3 at the same time. The input signal IN is input to the gate of PchTr5, the source is connected to the power supply, and the drain is connected to the gates of PchTr4 and Tr6. A current mirror circuit is configured by PchTr4 and PchTr6.

The input signal IN is PchTr7 and Pch.
It is also input to the gate of Tr8. The drain of PchTr8 and the source of PchTr9 are connected, and the drain of PchTr7 and the drain of PchTr9 are connected. or,
The source of the NchTr 10 is connected to GND, and the gate and the drain thereof are connected to the drain of the PchTr 7. or,
The NchTr 12 has a source connected to GND and a gate connected to the gate of the NchTr 10.

The drain of the NchTr 12 is connected to the output terminal 13 and, at the same time, connected to the gate of the PchTr 9. The input signal IN is input to the gate of the NchTr 11, the source is connected to GND, and the drain is connected to the gate of the NchTr 10. NchTr10 and NchTr12
And constitute a current mirror circuit.

At this time, the ratio of gm of PchTr4 and PchTr6 is set to 1: x, and NchTr10 and NchTr10 are set to Nm.
The ratio of gm with chTr12 is designed to be 1: y. PchTr5, NchTr2, PchTr8, Nc
Each hTr11 is designed with a sufficient size.

For example, to a load connected to the external terminal 13,
It is assumed that the current needs to be 60 mA through PchTr6. In addition, from the load connected to the external terminal 13, the NchT
If it is necessary to draw a current of 60 mA to GND through r12, gm of PchTr4 and PchTr6
Ratio of 1:10, gm of NchTr7 and NchTr9
The ratio of 1:10, and NchTr1 is a transistor that can carry a current of 1 mA, NchTr3 is 5 mA, and Pch is Pch.
When Tr7 is designed as a transistor that can flow 1 mA and PchTr9 is 5 mA, when the input signal IN changes from “L” to “H”, NchTr1 and Nch are changed.
The level of the contact A1 at which the Tr2 is turned on gradually becomes the GND level, so that the PchTr4 and the PchTr6 are turned on and the output o1 starts to change from "L" to "H".

At this time, the current flowing through NchTr1 is 1 mA.
Therefore, the current flowing through PchTr4 is 1mA, PchTr
The current flowing in 6 is obtained by changing the gm of PchTr4 to gm1 and Pc.
The current flowing through hTr4 is I1, gm of PchTr6 is g
g when the current flowing through m2 and PchTr6 is I2
Relational expression between m and current, I2 = gm2 · I1 / gm1 ...
Due to (1), the current I2 flowing through PchTr6 is 10 m
It becomes A.

Next, since the point o1 changes from "L" to "H", the NchTr3 is turned on, and the current flowing in the PchTr4 becomes 6 mA due to the current flowing in the NchTr1 of 1 mA and the current flowing in the NchTr3 of 5 mA.

From the above relational expression (1), the current flowing through the PchTr6 is 60 mA, and the current of 60 mA can flow from the power supply to the load connected to the external terminal 13 through the PchTr6.

When the input signal IN changes from "H" to "L", NchTr1 and NchTr2 are turned off, and Pc
Since the hTr5 is turned on, the point A1 is promptly set to the “H” level, the PchTr4 and PchTr6 are quickly turned off, and at the same time, the PchTr7 and PchTr8 are turned on. Since point A2 gradually changes to "H", Nch
Tr10 and NchTr12 are turned on. Point O1 is "H"
Begins to change from "L" to "L". At this time, since PchTr7 is a transistor capable of flowing a current of 1 mA, NchTr10 has a current of 1 mA. According to the relational expression (1) between gm and current, a current of 10 mA of NchTr12 flows.

Next, since the point O1 changes from "H" to "L", the PchTr9 is turned on. This is NchT
The current flowing through r10 is 6 mA, and according to the relational expression (1), Nc
The current flowing through hTr12 is 60mA, and the external terminal 1
GND from the load connected to 3 through NchTr12
A current of 60 mA can be drawn.

When the output terminal 13 changes from "L" to "H", first, the NchTr1 is turned on to set P
chTr6 is turned on. At this time, PchTr6 is 10
Since the current is mA, the external terminal 13 starts charging the load capacitance CL with this ability.

Next, when the output terminal 13 changes from "L" to "H", the NchTr3 is turned on, and a large amount of current gradually starts to flow, so that a large amount of current can also flow to the PchTr6. The charging of the load capacitance CL of the external terminal 13 is accelerated.

As described above, the output terminal O1 does not suddenly rise from "L" to "H", and the PchT from the power supply
The current for charging the load capacitance 14 does not transiently flow through r6. When the output terminal O1 changes from "H" to "L", the PchTr7 is turned on first, and
h12 is turned on. At this time, NchTr12 is 10m
Since the current of A is the ability to flow, the ability starts discharging the load capacitance CL of the external terminal 13.

Next, when the output terminal O1 changes from "H" to "L", the PchTr9 is turned on, and a large amount of current gradually starts to flow, so that a large amount of current can also flow in the NchTr12. Therefore, the discharge of the load capacity of the external terminal 13 is accelerated. As described above, the output terminal 1
3 does not suddenly fall from "H" to "L", and the discharge current flowing from the load capacitance CL to the GND through the NchTr 12 does not transiently flow.

FIG. 2 is a circuit diagram showing an output buffer circuit according to the second embodiment of the present invention. 2, in the present embodiment, the input signal IN and the control signal C (inversion value) are added to the circuit of FIG.
The NOR circuit 15 to which is input, the inverter circuit 16 that generates the control signal C, and the NAND circuit 17 to which the input signal IN and the control signal C are input are added as additional circuits.
The other circuit parts are the same as in FIG.

By adding this additional circuit, the present embodiment can also operate as a three-state buffer,
When the input signal IN changes, the external terminal 1
The charging / discharging current of the additional capacitance CL of 3 can be controlled so that a large amount of current can gradually flow.

[0032]

As described above, according to the present invention, the current value at the time of charging / discharging the external load capacity can be controlled, so that a transient current does not flow. , GND can be prevented, and malfunction due to fluctuations in the potential of the power supply and GND can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional output buffer circuit.

FIG. 4 is a circuit diagram showing a conventional three-state output buffer circuit.

FIG. 5 is a signal waveform diagram in a conventional output buffer circuit.

FIG. 6 is a signal waveform diagram in a conventional three-state output buffer circuit.

[Explanation of symbols]

IN input signal O External terminal output signal 1,2,3,10,11,12 N-channel transistor 4,5,6,7,8,9 P-channel transistor 13 External terminal CL load capacitance 15,21 NOR circuit 17,19 NAND circuit 16,18,20 Inverter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8941-5J H03K 19/00 101 F

Claims (2)

[Claims] 1. A first input signal is input to a first current source and a second current source, the first current source is connected to a first current mirror circuit, and the first current mirror is connected. A circuit is connected to an external terminal, a third current source for inputting the first input signal and an output signal of the external terminal is connected to the first current mirror circuit, and the second current source is a second current source. Second current mirror circuit, the second current mirror circuit is connected to the external terminal, and the fourth current source for inputting the first input signal and the output signal from the external terminal is connected to the second current source. An output buffer circuit characterized by being connected to the current mirror circuit of. 2. An inverter circuit to which a control signal is input,
A NOR circuit to which the control signal and the input signal are input, N
The output buffer circuit according to claim 1, wherein an AND circuit is provided in the input portion.