JPH05267662A - Complementary thin film semiconductor device and image processing equipment using the same - Google Patents

Abstract

PURPOSE:To restrain the increase of a photo resist process to a minimum and realize a high performance device at a low cost, by making the film thicknesses of semiconductor layers constituting an N-type transistor and a p-type transistor different from each other, in a complementary thin film semiconductor device composed of the N-type transistor and the P-type transistor formed on an insulating substrate. CONSTITUTION:The title semiconductor element consist of the following formed on a glass substrate 1; a gate electrode 10, a gate insulating film 20, an N<+> layer 31 doped with N-type impurities like phosphorus, a P<+> layer 33 doped with P-type impurities like boron, source/drain wiring electrodes 14 formed of Ti, and a protective film. A polycrystalline silicon layer 32 under the P<+> layer 33 is made thinner than the polycrystalline silicon layer 32 under the N<+> layer 31 by the amount nearly equal to the thickness of the P<+> layer 33. For example, when the thickness of the polycrystalline silicon layer 32 under the N<+> layer 31 is 200nm, and the thickness of the polycrystalline silicon layer 32 under the P<+> layer 33 is 50nm, the thickness of the polycrystalline silicon layer 32 under the P<+> layer 33 is 150nm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary thin film semiconductor device, and more particularly to the structure of a thin film semiconductor device used in an image display device, an image reading device and the like.

[0002]

2. Description of the Related Art As a thin film transistor (TFT) used in a liquid crystal display device, for example, an amorphous silicon (a-Si) TFT or a polycrystalline silicon (p-Si) TFT is formed on an insulating substrate such as glass. , For example, an active matrix drive liquid crystal display (L
In CD), these are used as semiconductor elements (pixel TFTs) in the image display area for driving the liquid crystal.

Further, it has been attempted to incorporate a drive circuit for driving these pixel TFTs on the same substrate by using these TFTs, and consequently reduce the price of the display device and the number of external connection lines. There is. The drive circuit (built-in drive circuit) formed on the substrate uses the following two methods in terms of circuit configuration. The first is a layer in which impurities are not added, a current source is taken out, a source,
A circuit type (N-type circuit) configured by an N-channel TFT in which phosphorus or antimony is added to a semiconductor layer in a contact region between the drain electrode terminal and the channel semiconductor layer to form an N-type semiconductor layer (N-type circuit). Is an N-channel type TFT, and the other TFT is a P-channel type by adding impurities such as boron to the source and drain semiconductor regions, and is composed of two complementary TFTs (C-type circuit). There is. These are, of course, called NMOS and CMOS circuits in the field of integrated circuits (ICs).
In the field of (2), an oxide film may not be used as a gate insulating film, so the above names are used below.

It goes without saying that the C-type circuit is superior in the performance of the circuit even if the knowledge in the IC field is not used.
It shows low power consumption characteristics. However, there is a drawback that the number of manufacturing steps is significantly increased to form a C-type circuit. This occurs due to the step of forming the C-type TFT, and, for example, in the order of steps, when adding (doping) N-type impurities to the channel semiconductor layer, the semiconductor layer to be the P-channel TFT is not formed. To prevent impurities from being doped, for example, a step of protecting with a photoresist,
When the P-type impurity is subsequently doped, a step of protecting the N-channel TFT with a photoresist and the like are necessary, and two extra photo steps are required for convenience.

As an example of a method of manufacturing a thin film semiconductor device for forming a built-in drive circuit of a liquid crystal display device by a C-type circuit,
985 Conference Record of International Display Research Conference (C
onference Record of International Display Research
Conference) Section 9

[0006]

In the above prior art, in order to realize a high-performance C-type built-in circuit, the number of manufacturing steps is significantly increased, and as a result, the cost of the liquid crystal display device is increased. was there.

An object of the present invention is to keep the high performance of the C-type drive circuit, that is, in the process of forming a thin film semiconductor device for the C-type drive circuit, while minimizing the increase of the photoresist process and making a final step. In other words, it is to provide a TFT structure and a method of manufacturing the same, and an image processing apparatus capable of incorporating and driving a peripheral circuit.

[0008]

In order to achieve the above object, the present invention provides, for example, in the case of a TFT having an inverted stagger structure,
The manufacturing method and structure are as follows. That is, after depositing a gate electrode and a gate insulating film, first, a p-Si or a-Si layer containing no impurities is formed, and then a semiconductor layer containing N-type impurities such as phosphorus is deposited or the surface of the Si layer is deposited. Then, an impurity for forming an N-type semiconductor layer is doped. After that, the region to be the N-type TFT is covered with a photoresist or the like, the N-type semiconductor layer in the region to be the P-type TFT is removed by etching, and then the impurities for forming the P-type semiconductor layer are doped. This allows the N-type T
A P-type TFT having a semiconductor layer thinner than the FT and the N-type TFT is formed.

[0009]

According to the method of manufacturing a TFT of the present invention, the conventional method 2
Since a C-type circuit, which requires an extra photo process, can be formed by adding one photo process, an inexpensive and high-performance image processing device formed using the semiconductor device of the present invention can be provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device for explaining the structure of the present invention.

The semiconductor device includes a gate electrode 10 formed on a glass substrate 1, a gate insulating film 20, an n + layer 31 doped with N-type impurities such as phosphorus, and a p + doped with P-type impurities such as boron. The layer 33 is composed of the source / drain wiring electrode 14 formed of Ti and the protective film 23. Here, the film thickness of the polycrystalline silicon layer 32 below the p + layer 33 is the same as the polycrystalline silicon layer 3 below the n + layer 31.
It is characterized in that it is thinner than the film thickness of 2 by about the film thickness of the p + layer 33. For example, if the film thickness of the polycrystalline silicon layer 32 below the n + layer 31 is 200 nm and the film thickness of the p + layer 33 is 50 nm, the film thickness of the polycrystalline silicon layer 32 below the p + layer 33 is about 150 nm. Has become.

2 to 5 are sectional views showing the outline of the manufacturing process of the first embodiment.

Cr on a glass substrate by sputtering
A film having a thickness of 300 nm is deposited and patterned into a predetermined shape to form the gate electrode 10. Next, the SiO ₂ film 20 as a gate insulating film is formed to 300 nm, the polycrystalline silicon film 30 is formed to 200 nm, and the n + layer 31 is formed to 50 nm by CVD, and patterned into a predetermined shape (FIG. 2). Here, the polycrystalline silicon film 30 may be formed by irradiating an amorphous silicon film with an excimer laser or the like. Next, the region to be the N-type TFT is covered with a photoresist, and the n + layer 31 in the region not covered with the photoresist is removed by a dry etching method using CF ₄ gas or the like (FIG. 3). Then, by ion implantation, the polycrystalline silicon film 30 in the region not covered with the photoresist is irradiated with an ion beam containing boron at an acceleration energy of about 2 keV to form a p + layer 33 (FIG. 4). After removing the photoresist, Ti is deposited by 40 nm by sputtering and patterned into a predetermined shape to form the source / drain wiring electrode 14. Finally CVD
Thus, the protective film 23 is formed to complete the complementary thin film semiconductor element (FIG. 5).

As is apparent from the above description, according to this embodiment, it is possible to form a complementary thin film semiconductor element which can be formed by adding one photo step.

Next, a second embodiment of the present invention will be described with reference to FIGS.
Will be explained.

In this embodiment, a video display terminal (VDT) having a diagonal display of 10 inches is realized. In this case, the number of pixels in the display section is 480 x 64.
0 × (3), the TFT used for the display section is an N-type TFT having an inverted stagger structure, and the TFT used for the built-in peripheral circuit
Are the N-type TFT and the P-type TFT.

FIG. 6 shows a sectional view of N-type and P-type TFTs used in the built-in peripheral circuit.

In this embodiment, the TF used in the built-in peripheral circuit
It is characterized in that the semiconductor layer forming T has a two-layer structure of polycrystalline silicon 32 and amorphous silicon 30.

7 to 10 are sectional views showing the outline of the manufacturing process of the second embodiment.

A Cr film is deposited to a thickness of 300 nm on the glass substrate 1 by a sputtering method and patterned to form a gate electrode 10.
And Next, the gate insulating film 2 is formed by the plasma CVD method.
A SiN film of 0 is 300 nm and an amorphous Si film is 30 n
m (FIG. 7).

Next, 200 mJ of XeCl excimer laser with a wavelength of 308 nm is formed on the portion of the substrate forming the peripheral circuit.
The amorphous Si film is irradiated with an intensity of 1 / cm ² to form a polycrystalline Si layer 3
Convert to 2 (Fig. 8).

Next, an amorphous film 30 to which impurities are not intentionally added is formed to a thickness of 200 nm and n + by plasma CVD.
Deposit layer 31 to 50 nm. Through the above steps, the semiconductor film in the peripheral circuit portion has a two-layer structure of polycrystalline Si / amorphous Si, and the semiconductor film in the pixel portion has a single layer structure of amorphous Si (FIG. 9).

After patterning the semiconductor layer by a photo-etching process, a region to be an N-type TFT is covered with a photoresist, and n of a region not covered with the photoresist is covered.
The + layer 31 is removed by a dry etching method using CF ₄ gas or the like (FIG. 10).

Next, an ion beam containing boron is applied to the polycrystalline silicon film 30 in the region not covered with the photoresist by an ion implantation method with an acceleration energy of about 2 keV.
And the p + layer 33 is formed (FIG. 11). After removing the photoresist, Ti is deposited by 40 nm sputtering and patterned into a predetermined shape to form the source / drain wiring electrode 14. Finally, a protective film 23 is formed by CVD to complete a complementary thin film semiconductor device (FIG. 12).

On the other hand, a polarizing plate, a color filter and a transparent electrode are formed on another glass substrate, and liquid crystal is sealed between the glass substrate and the above glass substrate to complete a 10 inch size VDT display device.

FIG. 13 shows the overall structure of a liquid crystal display device using the thin film semiconductor device. The device is composed of a TFT liquid crystal display unit 50, a scanning circuit 51, a switch matrix circuit 52 serving as a time function converting means, and a signal side circuit 53. It should be noted that a scanning signal from the scanning circuit 51 to each liquid crystal element of the liquid crystal display section 50 is transmitted through the scanning lines 71 to 73.
Signals are sent from the signal circuit 53 through the switch matrix circuit 52 and the signal lines 74 to 76. The N-type TFT of the present invention having the above structure is used for the switch 60a in the liquid crystal display unit 50 and 61 to 63 in the matrix circuit 52, and the switch in the scanning circuit 51 is the N-type TFT of the present invention.
It is composed of a complementary circuit configured by combining an FT and a P-type TFT.

Next, the operation of FIG. 13 will be briefly described.

The scanning circuit 51 outputs 2 as a timing signal.
The CKV signal of the phase clock and the input voltage Vin are input. On the other hand, the digital data signal data that determines the display state of the liquid crystal is input to the signal circuit 53, which is output as the color signal voltages V _{S1 to} V _Sm , which are distributed to the signal lines as matrix switches.

Next, the circuit configuration of the scanning circuit 51 will be described with reference to FIG. FIG. 14 shows a scanning circuit corresponding to one scanning line, which is composed of a shift register and a buffer circuit for amplifying a voltage as a function. 70 in the figure
Is an N-type TFT, and 71 is a P-type TFT. The operation of the scanning circuit will be described. The shift register takes timing with the two-phase clocks (Vc1, Vc2) and the respective inversion clocks (Vcn1, Vcn2), inverts (shifts) the input voltage Vin and transfers it to the buffer, and at the same time, this shifts corresponding to the next scanning line. It becomes the input voltage of the register. The buffer is amplified in phase with the inverted voltage,
A pulse voltage whose maximum voltage is Vdd2 is output, and this becomes the scanning voltage Vg of the liquid crystal display unit. Where Vdd1 and Vd
d2 is a DC voltage.

The complementary TFT shift register constructed by using the semiconductor device of the present invention has an operating frequency of a voltage 20 times faster than that of a conventional N-type TFT and consumes three orders of magnitude less power. Indicated. Further, particularly in the present embodiment, a TFT having a semiconductor layer having a two-layer structure of polycrystalline Si / amorphous Si is used for a driving circuit that requires high-speed operation, and a semiconductor is used for a pixel portion that requires low leakage current. By using a TFT whose layer is composed of a single layer of amorphous Si, the characteristics of polycrystalline Si and amorphous Si can be utilized, so that a liquid crystal display device having good performance can be realized.

Further, although the semiconductor layer of the driving circuit portion has a two-layer structure of polycrystalline Si / amorphous Si in the above-mentioned embodiment, the present invention is not limited to this example, and the semiconductor layer is made of polycrystalline Ge or poly-Si. crystal
The same applies to a laminated structure of SiGe and amorphous Si or amorphous SiGe.

In the above example, the semiconductor film thickness of the P-type TFT is smaller than that of the N-type TFT, but the N-type TF is replaced by switching the N-type and P-type in the above description.
It is also possible to make the semiconductor film thickness of T smaller, which does not impair the effects of the present invention.

[0033]

According to the present invention, it is possible to reduce the number of photo-processes in the manufacture of a semiconductor device for a layer complementary circuit while maintaining the characteristics of the layer complementary circuit that operates at high speed and consumes less power. There is. Finally, there is an effect that the peripheral drive circuit can be built in the liquid crystal display substrate or the image processing apparatus.

[Brief description of drawings]

FIG. 1 is a sectional view of an inverted stagger structure TFT according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a TFT showing the manufacturing procedure of the first embodiment of the present invention.

FIG. 3 is a sectional view of the same TFT.

FIG. 4 is a sectional view of a TFT of the same.

FIG. 5 is a sectional view of the same TFT.

FIG. 6 is a sectional view of a TFT showing a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a TFT showing the manufacturing procedure of the first embodiment of the present invention.

FIG. 8 is a sectional view of the same TFT.

FIG. 9 is a sectional view of the same TFT.

FIG. 10 is a sectional view of the same TFT.

FIG. 11 is a sectional view of the same TFT.

FIG. 12 is a sectional view of the same TFT.

FIG. 13 is an overall configuration diagram of a TFT liquid crystal panel.

FIG. 14 is an equivalent circuit diagram of a scanning circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 10 ... Gate electrode, 14 ... Source / drain wiring electrode, 20 ... Gate insulating film, 23 ... Protective film,
30 ... Amorphous silicon, 31 ... N + layer, 32 ... Polycrystalline silicon film, 33 ... P + layer.

Claims (6)

[Claims] 1. A complementary thin film semiconductor device comprising an n-type transistor and a p-type transistor formed on an insulating substrate, wherein a film thickness of a semiconductor layer forming the n-type transistor and a semiconductor layer forming the p-type transistor are A complementary thin film semiconductor device characterized in that the semiconductor layers forming an n-type transistor and a p-type transistor have different thicknesses. 2. The complementary thin film semiconductor device according to claim 1, wherein the semiconductor layer is formed on an upper layer of the gate electrode. 3. A complementary thin film semiconductor device according to claim 1, wherein the semiconductor layer has a laminated structure of two or more different materials. 4. The complementary thin film semiconductor device according to claim 3, wherein the semiconductor layer has a structure in which polycrystalline Si and amorphous Si are stacked in this order from the side closer to the gate insulating film. 5. The semiconductor layer according to claim 3, wherein the semiconductor layer has a structure in which polycrystalline SiGe or polycrystalline Ge, amorphous Si or amorphous SiGe are stacked in this order from the side closer to the gate insulating film. Characteristic complementary thin film semiconductor device. 6. A display device in which liquid crystal is sealed between transparent insulating substrates, and a driving switch group of a pixel region which is a display portion formed on one insulating substrate or a peripheral for driving pixels formed on one insulating substrate. An image information processing device, wherein a circuit is configured by using the complementary thin film semiconductor device according to claim 1.