JPH05267593A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize equipping a p-channel FET with a p-type gate to contrive to accelerate a device without increasing the number of production processes in a Bi-CMOS process. CONSTITUTION:A Bi-CMOS process for forming a bipolar transistor and CMOS device on the same substrate has a production process for sticking a conductive film on the substrate and simultaneously patterning the conductive film to form the base leading electrode 15 of the bipolar transistor and the gate 16 of a p-channel FET and a production process for simultaneously introducing a p-type impurity into the base-leading electrode and the gate under the same conditions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a Bi-CMOS process for forming a bipolar element and a CMOS element on the same substrate.

In recent years, as the speed and miniaturization of semiconductor devices have advanced, it has become very important to improve the performance of p-channel field effect transistor (FET) in the Bi-CMOS process. Therefore, the p-type gate electrode is adopted.
The present invention can be used for this process.

[0003]

2. Description of the Related Art Conventionally, n-type gates have been used as FET gates regardless of whether they are p-channel or n-channel. Also, Bi
-In the CMOS process, p-type impurities are diffused into the substrate to form the external base region in order to connect to the base extraction electrode of the bipolar transistor.

On the other hand, in the Bi-CMOS process that requires high speed, the p-channel which is the bottleneck of high speed
Improving FET performance is important. To improve the performance of the p-channel FET, there are methods such as reduction of the gate length and reduction of V _th , but the conventional n-type gate electrode is weak against the short channel effect and the variation of V _th becomes large. As one of the means, the threshold voltage V _th is strong enough to withstand the short channel effect.
A method called p-type gating that can be designed to be low is adopted.

[0005]

In the conventional Bi-CMOS process, in order to realize the p-type gate of the p-channel FET, the n-type gate of the n-channel FET and the p-type of the p-channel FET can be realized.
The mold gate had to be made in separate steps.

The present invention realizes a p-type gate of a p-channel FET without increasing the number of steps in the Bi-CMOS process,
The purpose is to speed up the device.

[0007]

[Means for Solving the Problems] To solve the above problems, in a Bi-CMOS process in which a bipolar transistor and a CMOS element are formed on the same substrate, a conductive film is deposited on the substrate and the conductive film is simultaneously formed. Manufacture of a semiconductor device including a step of patterning to form a base extraction electrode 15 of the bipolar transistor and a gate 16 of a p-channel FET, and a step of simultaneously introducing a p-type impurity into the base extraction electrode and the gate under the same conditions. Achieved by the method.

[0008]

In the present invention, the number of steps is reduced by diffusing the p-type impurity in the polysilicon film for drawing out the base of the bipolar transistor and by diffusing the gate of the p-channel FET under the same conditions using the same mask. ..

[0009]

1 (A), 1 (B), 2 (C) and 2 (D) are views for explaining an embodiment of the present invention. In FIG. 1 (A), 1 is a p-type silicon (Si) substrate, 3 is an n ⁺ buried layer for a bipolar transistor, 4 is a p ⁺ buried layer for element isolation, and 5 is a p-channel FET.
N ⁺ buried layer, 6 p ⁺ buried layer for n-channel FET, 7 undoped epitaxial Si layer, 8 p for element isolation
Type region, 9 is a silicon dioxide (SiO ₂ ) film by thermal oxidation between field insulations, 10 is a SiO ₂ film such as a gate insulation film, 11 is an n well for a bipolar transistor, 12 is a p-channel FE
N-well for T, 13 is p-well for n-channel FET, 14
Is an n ⁺ type collector contact region for the pattern transistor.

Up to this point, it is manufactured by the normal process of the Bi-CMOS process. In Fig. 1 (B), the thickness of 30
A non-doped polysilicon film of 00Å is grown and patterned to form a base extraction electrode 15, a gate 16 of a p-channel FET, a gate 17 of an n-channel FET, and a resist mask is used to form a base extraction electrode 15 and a p-channel FET. Boron ions (B ⁺ ) are implanted into the gate 16 as a p-type impurity, and activated by a heat treatment in a later step to become a p ⁺ type.

Here, an example of the B ⁺ implantation conditions is an energy of 35 KeV and a dose of 3E15 cm ^-2 . Then, using another resist mask, n
By introducing impurity to n ⁺ -type reduction.

Next, a SiO ₂ film 18 is formed as an interlayer insulating film by vapor phase epitaxy (CVD) on the base extraction electrode 15, the gate 16 of the p-channel FET and the gate 17 of the n-channel FET. In FIG. 2C, the interlayer insulating film 18 in the base formation region of the bipolar transistor is opened to form the base region 19, and the impurity is diffused from the p ⁺ -type base extraction electrode 15 by thermal diffusion to form the external base region 20. To do.

Next, the p-type source / drain region 21 of the p-channel FET is formed by self-alignment with the gate 16 by ion implantation. Then, the n-type source / drain region 22 of the n-channel FET is formed by self-alignment with the gate 17 by ion implantation. In this case, the LDD (offset) structure as shown in the drawing is usually formed by using the implantation method using the sidewall insulating film of the gate as a mask.

In FIG. 2 (D), a required portion of the oxide film on the substrate is opened, a 1000-Å-thick non-doped polysilicon film is grown, and patterned to form the emitter electrode 23, collector electrode 24, and n-channel FET. A source / drain electrode 25 is formed, and an n-type impurity is introduced to make it an n ⁺ type.

After this, similarly, the source and drain of the p-channel FET are pulled out. After that, through the normal process, Bi-C
Complete the MOS device.

[0016]

According to the present invention, the p-type gate of the p-channel FET can be realized without increasing the number of steps in the Bi-CMOS process, and the device speed can be increased.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention (1)

FIG. 2 is a diagram explaining an embodiment of the present invention (2)

[Explanation of symbols]

1 Si substrate 3 n ⁺ buried layer for bipolar transistor 4 p ⁺ buried layer for element isolation 5 ⁺ n ⁺ buried layer for p channel FET 6 p ⁺ buried layer for n channel FET 7 epitaxial Si layer 8 for element isolation p-type region 9 fields for p-well 14 pattern transistors for n-well 13 n-channel FET of the SiO ₂ film 11 for n-well 12 p-channel FET of the bipolar transistor in the SiO ₂ film 10 gate insulating film or the like between the insulating n ⁺ Type collector contact region 15 Base extraction electrode 16 p-channel FET gate 17 n-channel FET gate 18 Interlayer insulation film CVD SiO ₂ film 19 base region 20 external base region 21 p-channel FET p-type source / drain region 22 n-channel N-type source / drain region of FET 23 emitter electrode 24 collector electrode 25 source / drain electrode of n-channel FET

Claims (1)

[Claims] 1. In a Bi-CMOS process for forming a bipolar transistor and a CMOS device on the same substrate, a conductive film is deposited on the substrate, and the conductive film is simultaneously patterned to form a base lead electrode of the bipolar transistor. (1
5) and a step of forming a gate (16) of a p-channel FET, and a step of simultaneously introducing a p-type impurity into the base extraction electrode and the gate under the same condition.