JPH05267442A - Dielectric isolating substrate and its manufacture - Google Patents

Abstract

PURPOSE:To enable the wire breaking of wiring and micronization while materializing high breakdown strength. CONSTITUTION:A groove 10, where the angle theta between the sidewall 19 and the main surface is obtuse (>90 deg.C), is dug in the surface of a substrate where at least a lead wire 18 and an n<+>-buried layer 15 cross each other, and an oxide film 26 is made in the groove 10 and on the main surface of a single crystal Si island 12 so that the exposed face may be nearly flat. The oxide film 26 is a laminate consisting of the thick oxide film 26a made inside the groove 10 and the thin oxide film 26b made uniformly on the surface of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate and a method for manufacturing the same, and more particularly to a dielectric isolation substrate that achieves both high breakdown voltage and miniaturization and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 is a sectional view of a diode using a conventional dielectric isolation substrate 11.

This diode is a p ⁺ -type by a p-type dopant such as boron (B) in a Si single crystal island 12 embedded in a main surface of an n ⁻ -type polycrystalline Si supporting substrate 14 via a dielectric thin film 13. A region 81 is formed, and an n ⁺ -type region 82 is further formed by an n-type dopant such as phosphorus (P).

When a voltage is applied to the diode having such a structure as shown in the figure, a depletion layer spreads on the main surface of the Si single crystal island 12 due to the electric field effect of the lead wiring 18 formed on the oxide film 16 on the substrate surface. , This is the dielectric thin film 13
To form a channel (not shown).

As a result, in the above-mentioned conventional technique, there is a problem that the p-type region 81 is electrically connected to other regions by the channel, or electric field concentration is caused so that a high breakdown voltage cannot be obtained.

Therefore, in order to stop this channel, S
A structure is known in which an n ⁺ buried layer 15 having a high impurity concentration is formed on the bottom and side walls of the i single crystal island 12. However, when the n ⁺ buried layer 15 is formed, the n ⁺ buried layer 15
The electric field concentration occurs on the substrate surface where the lead wire 18 intersects with the lead wire 18, and the breakdown voltage is newly reduced.

In order to solve such a problem, the oxide film 1 is made so that the influence of the electric field effect by the wiring 18 can be ignored.
6 should be thickened. However, if the oxide film 16 is thickened, the steps on the surface of the substrate become large, so that there are problems that miniaturization becomes difficult, and that disconnection easily occurs at the steps and the reliability deteriorates.

To solve these problems, for example, in Japanese Patent Laid-Open No. 60-208842, as shown in FIG. 9, a thick oxide film 16a is formed on the surface of the oxide film 16 in another region. A structure has been proposed in which most of the thick oxide film 16a is embedded inside the substrate so as to be flush with each other.

FIG. 7 shows an oxide film when the thick oxide film 16a is embedded inside the substrate to flatten the substrate surface (solid line) and when the thick oxide film 16a is projected to the substrate surface (broken line). It is a figure showing the relationship between the film thickness of 16 and the minimum processing dimension.

As described above, by adopting the structure in which the thick oxide film 16a is buried inside the substrate, a substrate having a small surface step can be obtained while maintaining a sufficient breakdown voltage, and miniaturization and improvement of reliability are possible. Became.

[0011]

However, when the invention of the present invention was examined in more detail, in the above-described structure, the step between the thick portion and the thin portion of the oxide film 16 is the Si single crystal 1
2 and the side surface 19 of the step portion is perpendicular to the main surface of the substrate, the electric field is concentrated at the corner portion 20 (see FIG. 9) of the bottom portion of the oxide film 16 and a sufficient breakdown voltage is obtained. I found that I could not get it.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a dielectric isolation substrate capable of improving reliability and miniaturization while realizing a high breakdown voltage, and a manufacturing method thereof. To do.

[0013]

In order to achieve the above object, in the present invention, a semiconductor element is formed in a large number of single crystal islands embedded in a main surface of a semiconductor supporting substrate through a dielectric thin film. In the dielectric isolation substrate, the extraction wiring connected to the semiconductor element on the surface of the substrate and extended to the outside of the single crystal island and at least the extraction wiring intersects with the first-conductivity-type high-concentration buried layer. And a groove having an obtuse angle between the side wall and the substrate surface, and an insulating film formed on the substrate including the inside of the groove and having a substantially flat main surface.

[0014]

According to the above-mentioned structure, since a relatively thick insulating film is formed in the groove, it is possible to prevent the depletion layer from being generated by the electric field generated by the extraction electrode, and the thick insulating film is formed inside the single crystal island. The angle between the side surface of the substrate and the surface of the substrate becomes an obtuse angle, and the electric field concentration is relieved, so that the breakdown voltage is improved. Further, since the surface of the substrate is flattened and steps are eliminated, reliability is improved and miniaturization becomes possible.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a diode which is an embodiment of the present invention, and the same reference numerals as those used above represent the same or equivalent portions.

In this embodiment, a groove 10 having an obtuse angle (> 90 °) between the side wall 19 and the main surface is squeezed in the substrate surface where the lead wiring 18 and the n ⁺ buried layer 15 intersect. Thus, an oxide film 26 is formed in the groove 10 and on the main surface of the single crystal Si island 12 so that the exposed surface thereof is substantially flat.

According to the present embodiment, the electric field due to the lead wiring 18 is blocked by the thick portion 26a of the oxide film 26, and the electric field concentration generated in the n ⁺ buried layer 15 is relaxed, so that the breakdown voltage is improved. Further, since the oxide film 26a is embedded inside the substrate, the step on the surface of the substrate is eliminated, disconnection is less likely to occur, reliability is improved, and fine processing becomes possible.

Further, since the angle θ formed between the side wall 19 of the groove 10 and the main surface is an obtuse angle, the electric field concentration at the end of the oxide film 26 at the bottom of the groove 10 can be alleviated.

FIG. 2 is a sectional view of a diode which is a second embodiment of the present invention, and the same symbols as those used above represent the same or equivalent portions.

In this embodiment, the groove 10 having a depth of two steps is formed on the substrate surface where the lead wiring 18 and the n ⁺ buried layer 15 intersect.
a is formed in the groove 10a and the single crystal Si island 12 is formed.
An oxide film 36 whose exposed surface is substantially flat is formed on the main surface of the.

Such an oxide film 36 is, for example, LOCOS (Local Oxidation of) as will be described later in detail with reference to FIG.
This can be obtained by repeatedly forming an oxide film by the Silicon method to form a thick oxide film 36a and a relatively thick oxide film 36b, and then uniformly forming a thin oxide film 36c on the substrate surface.

In this embodiment, the n ⁺ diffusion layer 17 is formed in the single crystal island 12 under the lead wiring 18 to reduce the electric field concentration at the end of the single crystal island 12.

According to this embodiment, similarly to the above, relaxation of the electric field concentration by the wiring 18 and improvement of the reliability line due to the small step on the substrate surface are achieved. Further, according to the present embodiment, since the diffusion layer 17 is provided in particular, the electric field concentration on the end portion of the single crystal island 12 under the lead wiring 18 is relieved, so that the breakdown voltage is further improved.

FIG. 3 is a sectional view showing a method of manufacturing the dielectric isolation substrate described with reference to FIG. here,
A description of a conventional method for manufacturing a dielectric isolation substrate will be omitted, and description will be given from the step after the mirror polishing of the main surface of the Si single crystal island 12 is completed.

First, after forming an oxide film on the entire surface, the groove 1 is formed.
The mask pattern 3 is formed by removing the oxide film in the region where 0 is compressed.
1 is formed [(a) in the figure].

Next, the groove 10a is formed on the substrate surface by etching with an alkaline etching solution such as KOH.
To form. When the [100] substrate is used, the angle θ between the side wall 19 of the groove 10a and the main surface of the substrate is 125.3 °. The depth of the groove 10a is preferably about 55% or more of the film thickness of the oxide film 36 deposited in a later step.

After the etching, the oxide film 31 used as the mask material is removed. At this time, the end portion 1 of the dielectric thin film 13
The etching amount is controlled so that 3a remains. This is because if the end portion 13a of the dielectric thin film 13 is also etched, a difference in the growth rate of the oxide film will occur during the subsequent formation of the oxide film by the LOCOS method, resulting in a step on the substrate surface. ..

After the groove 10a is formed as described above, n-type impurities such as phosphorus are implanted and thermally diffused to form the n-type region 17
a is formed [(b) in the figure].

Next, an oxide film 34 for stress relaxation is formed on the entire surface in an oxygen atmosphere, and further, the substrate surface and the groove 10a are formed.
A nitride film 35 is formed as a protective film on the side wall 19 of the above, in other words, on the entire surface excluding the bottom of the groove 10a [FIG.
].

Then, a thick oxide film 36 is formed by the LOCOS method.
a is formed inside the groove 10a. By the oxidation for a long time, the implanted n-type impurities 17a are further diffused to form a diffusion layer 17 having a deep junction depth [(d) in the figure].

Next, an oxide film is further formed by the LOCOS method to form a relatively thick oxide film 36b [FIG.
].

After that, a thin oxide film 36c is formed on the entire surface similarly to the conventional technique, and then an opening is provided at a predetermined position to connect the lead wiring 18.

The substrate manufactured by the above process has a very small surface level difference and can be microfabricated although the thick oxide film 36a required to obtain a high breakdown voltage is formed. In the example produced by the above method, when the thickness of the thick oxide film 36a is about 4 μm and the thickness of the thin oxide film 36b is about 2 μm, the step on the substrate surface can be suppressed to 1 μm or less.

FIG. 4 is a sectional view of a third embodiment of the present invention, in which the same reference numerals as those used above denote the same or equivalent portions.

In this embodiment, the oxide film 42 is formed by repeating the formation of the oxide film by, for example, the LOCOS method, after forming the groove 10c which becomes deeper stepwise in the extension direction of the lead wiring 18. Obviously, the same effects as the above can be achieved by this embodiment as well.

FIG. 5 is a sectional view of the fourth embodiment of the present invention, in which the same reference numerals as those used above represent the same or equivalent portions.

In this embodiment, after the thick oxide film 51 is formed in the groove 10d by the LOCOS method, the insulating film 52 is deposited by the chemical vapor deposition method whose film formation rate is significantly higher than that of the thermal oxidation method. An insulating film is formed. According to this embodiment, since the manufacturing time is shortened, the productivity is improved.

FIG. 6 is a cross-sectional view of the fifth embodiment of the present invention, in which the same symbols as those used above represent the same or equivalent portions.

In this embodiment, the oxide film 6 is formed on the bottom of the groove 10e.
1 is formed, a thin oxide film 62 for protection is evenly deposited on the side wall of the groove, and an organic material that is cured by heat or chemical treatment, for example, polyimide 63 is applied to form an insulating film. Is formed.

According to this embodiment, the insulating film can be deposited more easily than the thermal oxidation method, and the insulating film has a soft viscosity, which is effective in alleviating the surface step.

In each of the above-described embodiments, the present invention has been described by taking the dielectric isolation substrate on which the diode is formed as an example, but the present invention is not limited to this. The semiconductor device can be similarly applied to a dielectric isolation substrate in which a single crystal island is formed.

[0043]

As described above, according to the present invention, the following effects can be achieved. (1) Since the influence of the electric field effect due to the lead wiring is mitigated by the thick oxide film, the breakdown voltage is improved. (2) Since the thick oxide film is embedded inside the substrate, the steps on the substrate surface are eliminated, the disconnection is less likely to occur, the reliability is improved, and the fine processing is enabled. (3) Since the angle θ formed between the sidewall of the groove in which the thick oxide film is buried and the main surface is an obtuse angle, the electric field concentration on the oxide film end of the groove bottom is relaxed and the breakdown voltage is further improved. (4) Since the high-concentration diffusion layer is formed at the end of the single crystal under the lead-out wiring, the electric field concentration on the end of the single crystal island 12 under the lead-out wiring is relaxed, and the breakdown voltage is further improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing method of FIG.

FIG. 4 is a sectional view of a third embodiment of the present invention.

FIG. 5 is a sectional view of a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between a film thickness of an oxide film and a minimum processing dimension.

FIG. 8 is a cross-sectional view of a conventional technique.

FIG. 9 is a cross-sectional view of a conventional technique.

[Explanation of symbols]

10 ... groove, 11 ... dielectric isolation substrate, 12 ... n ^- form a single crystal region, 13 ... dielectric thin film, 14 ... polycrystal Si, 15 ... n
⁺ Buried layer, 16, 26, 36, 42, 51, 61 ... Oxide film, 17 ... N-type diffusion region, 18 ... Lead wiring, 19 ...
Side wall, 34 ... Oxide film for stress relaxation, 35 ... Nitride film, 63 ... Polyimide, 81 ... P ^{+ type} region, 82 ... N ⁺
Shape area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mutsuhiro Mori 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (14)

[Claims] 1. A dielectric isolation substrate having semiconductor elements formed in a large number of first conductivity type semiconductor single crystal islands embedded in a main surface of a semiconductor supporting substrate via a dielectric thin film, wherein the inside of the single crystal island is formed. A high-concentration buried layer of the first conductivity type formed in contact with the dielectric thin film, a lead wire connected to the semiconductor element on the surface of the substrate and extended outside the single crystal island, and at least the lead wire and the first lead wire. A groove that is squeezed on the surface of the substrate where the conductive high-concentration buried layer intersects, and the side wall and the surface of the substrate form an obtuse angle, and is formed on the substrate including the inside of the groove, the main surface of which is substantially A dielectric isolation substrate comprising a flat insulating film. 2. The dielectric isolation substrate according to claim 1, wherein the depth of the groove is increased stepwise in the extension direction of the lead wiring. 3. A high-concentration diffusion layer of the first conductivity type, which relaxes electric field concentration at the edge of the single crystal island, at least in the single crystal island under the lead-out wiring. The dielectric isolation substrate according to claim 2. 4. The insulating film, wherein a thickness of a portion buried below the main surface of the semiconductor supporting substrate is thicker than a thickness of a portion exposed above the main surface. 3. The dielectric isolation substrate according to any one of 3 above. 5. The insulating film is a laminated film of a first insulating film formed in a groove and a second insulating film uniformly formed on a substrate surface including the surface of the first insulating film. The dielectric isolation substrate according to any one of claims 1 to 4, characterized in that. 6. The dielectric isolation substrate according to claim 5, wherein the first insulating film is a thermal oxide film. 7. The second insulating film is a thermal oxide film, CVD
The dielectric isolation substrate according to claim 5 or 6, which is either a film or an organic film deposited by a printing technique. 8. The dielectric isolation substrate according to claim 5, wherein a protective film is formed between the second insulating film and the side wall of the groove. 9. The dielectric isolation substrate according to claim 5, wherein the depth of the groove is about 55% of the film thickness of the first insulating film. 10. A method for manufacturing a dielectric isolation substrate, comprising: forming a semiconductor element in a large number of first conductivity type semiconductor single crystal islands embedded in a main surface of a semiconductor supporting substrate via a dielectric thin film, wherein the single crystal is formed. After the mirror-polishing of the exposed surface is completed, a groove having an obtuse angle between the side wall and the substrate surface is formed at least on the substrate surface where the lead wiring formed later and the first-conductivity-type high-concentration buried layer intersect. A step of forming an insulating film on the substrate including the inside of the groove to planarize the main surface of the substrate, and a step of connecting to the semiconductor element through an opening provided in the insulating film and extending to the outside of the single crystal island A method of manufacturing a dielectric isolation substrate, comprising the step of forming wiring. 11. A method for manufacturing a dielectric isolation substrate, comprising a semiconductor element formed in a large number of first conductivity type semiconductor single crystal islands embedded in a main surface of a semiconductor supporting substrate via a dielectric thin film, wherein the single crystal is formed. After finishing the mirror polishing of the exposed surface, at least on the substrate surface where the lead-out wiring formed later and the first-conductivity-type high-concentration buried layer intersect, the side wall and the substrate surface are deepened stepwise in the extension direction of the lead-out wiring. A step of forming a groove having an obtuse angle with, a step of forming an insulating film on the substrate including the inside of the groove to flatten the main surface of the substrate, and an opening provided in the insulating film for connecting to a semiconductor element And a step of forming a lead wiring extended to the outside of the single crystal island. 12. After the formation of the groove, the method further comprises the step of forming a first-conductivity-type high-concentration diffusion layer that alleviates the electric field concentration at the end of the single crystal island at least in the single crystal island under the lead wiring. The method for manufacturing a dielectric isolation substrate according to claim 10 or 11, which is characterized by the following. 13. The step of forming the insulating film includes the step of forming a relatively thick first insulating film in the groove, and the second insulating film on the substrate including the surface of the first insulating film. 13. The method for manufacturing a dielectric isolation substrate according to claim 10, further comprising the step of uniformly forming the substrate to flatten the surface of the substrate. 14. The step of forming a first insulating film in the groove includes a step of depositing a protective film on the groove side wall and the substrate surface excluding the groove bottom, and a LOCOS method on the substrate surface exposed at the groove bottom. 14. The method for manufacturing a dielectric isolation substrate according to claim 13, further comprising the step of forming an oxide film.