JPH05265989A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To eliminate the storage of erroneous data or the meaningless repetition of re-transmission due to the abnormality of the receiving buffer of the processor of a transmitting destination by stopping the re-transmission of transmitted data when the non-permission of the use of the receiving buffer is reported. CONSTITUTION:The decoder part 37 of the processor 2 of the transmitting destination refers to a receiving buffer permission register 34, and judges the presence or absence of the permission of the receiving buffer 31. The decoder part 37 judges that the receiving buffer 31 is not permitted because of the occurrence of the abnormality of the receiving buffer 31, it outputs a prescribed control signal to a reception control part 32. The reception control part 32 generates an NG1 packet (no packet) in an OK/NG return buffer 38, and transmits the NG1 packet to a transmitting source processor 1. This NG1 packet is inputted to the receiving buffer 23 of the processor 1. The decoder part 24 outputs a transmission stop signal to a transmission control part 22, and the transmission control part 22 stops the subsequent transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors are connected to a bus and when data transmission to a destination processor fails, the data is retransmitted to the same destination. ..

[0002]

2. Description of the Related Art FIG. 5 shows, for example, Japanese Patent Laid-Open No. 62-249541.
FIG. 10 is a block diagram showing a conventional multiprocessor system disclosed in Japanese Patent Publication No. In the figure, 1 is a processor as a transmission source, 2 is a processor as a transmission destination, and 3 is a bus to which these processors 1 and 2 are connected.

In the processor 1, 11 is a transmitter for transmitting the transmission data to the bus 3, 12 is a transmission queue for the transmission data transmitted by the transmission unit 11, and 13 is a transmission queue. The control unit controls the transmission of transmission data by the transmission unit 11. 14 is provided with a flag corresponding to the transmission data, and if the transmission data is unsuccessfully transmitted and waiting for retransmission, the flag corresponding to the transmission data indicates that the transmission data is in the standby state for retransmission, for example, It is a transmission stop management table in which a signal of logic "1" is written. Reference numeral 15 is a counter provided for the processor of the transmission destination and counting the number of transmission failures of the transmission data to the transmission destination processor by the transmission unit 11. Reference numeral 16 indicates the transmission data when the transmission failure is detected. It is a timer that generates the timing until retransmission.

The receiving function of the processor 1 as the transmission source is not shown, and the processor 2 as the reception destination has exactly the same configuration as the processor 1 as the transmission source. There is.

Next, the operation will be described. When the control unit 13 detects a transmission failure to the processor 2 after transmitting the transmission data to the transmission destination processor 2, the transmission source processor 1 transmits the transmission data addressed to the processor 2 to the transmission waiting data queue 12. Register again at the top. And
A logic "1" is written and stored in the flag corresponding to the transmission data of the transmission stop management table 14, and then the count content of the counter 15 corresponding to the destination processor 2 is updated. On the other hand, the timer 16 is reset in response to the detection of the transmission failure of the transmission data, and at the same time, starts the time counting, and when the predetermined time is reached, the data is retransmitted to the transmission unit 11 via the control unit 13. Generate a send command. The transmission unit 11 that has received this retransmission instruction
The same transmission data to be retransmitted, which is registered at the head of the transmission waiting data queue 12, is derived and an attempt is made to retransmit it to the processor 2.

Here, if the transmission data is received by the processor 2 of the transmission destination, the subsequent processing is ended. At this time, the counter 15 corresponding to the transmission destination processor 2 is cleared, and the flag corresponding to the transmission data in the transmission stop management table 14 is also cleared. Note that if the transmission fails again, the above-described processing procedure is repeatedly executed, and when the count content of the counter 15 reaches a predetermined value, the transmission of the transmission data to the processor 2 is performed thereafter. Then, the processor 2 is determined to have failed and is disconnected from the system.

[0007] By using the timer 16 for determining the timing of retransmission as described above, the time interval for retransmission is set to a finite time greater than zero, so that the processor 2 of the transmission destination is temporarily affected by the reception buffer busy. It is no longer possible to erroneously determine a serious transmission failure as a processor failure.

[0008]

Since the conventional multiprocessor system is configured as described above, the retransmission control is performed by the timer 16 which determines the retransmission timing and the counter 15 which counts the number of retransmissions. Therefore, even if data is transmitted to the receive buffer area when an error occurs in the buffer of the destination processor 2 and it is in an unusable state, the transfer is normally completed and the erroneous data is received by the receiving side. Is stored, or the transmission is judged to have failed, and the retransmission is performed using the timer 16 and the counter 15, and the retransmission without success is repeated a prescribed number of times.

The present invention has been made in order to solve the above problems, and does not store erroneous data or perform meaningless retransmission due to an abnormality in the receiving buffer of the destination processor. The purpose is to obtain a multiprocessor system.

[0010]

According to a first aspect of the present invention, there is provided a multiprocessor system including a reception buffer permission register indicating whether the reception buffer is permitted to be used and a reception buffer busy indicating whether the reception buffer is receiving. Registers, decoder unit that can judge whether receive buffer use is enabled or not, error detection unit that disables the above receive buffer enable register when an error occurs in the receive buffer, receive buffer use disable, receive buffer busy, etc. A receiver control unit that controls the transmission of the return data that notifies the notification is provided in the destination processor, and the receive buffer is used according to the decoder unit that determines the return data from this destination processor and the operating conditions generated by this decoder unit. If it is not permitted, the transfer is canceled and the If the buffer busy those which gave a transmission control unit for controlling retransmission at a predetermined timing to the transmission source processor.

According to a second aspect of the present invention, in the multiprocessor system, the destination processor has a port / buffer management table that manages the correspondence between the reception buffer and the port, and the error detection unit receives the reception buffer. When an error is detected, the corresponding receive buffer of the port is changed to another normal receive buffer, and the transmission control unit of the processor of the transmission source controls the retransmission of the transmission data even when the use of the reception buffer is not permitted. It is something to do.

[0012]

According to the first aspect of the present invention, the multiprocessor system retransmits the transmission data when the processor of the transmission destination notifies that the reception buffer is not permitted to be used due to the abnormality of the reception buffer. Stop, and when it is notified that the receive buffer is in use, by retransmitting the send data at a predetermined timing, due to an error in the receive buffer of the destination processor, incorrect data storage or A multiprocessor system that does not repeat meaningless retransmissions is realized.

In the multiprocessor system according to the second aspect of the present invention, even if an abnormality occurs in the reception buffer, the port / buffer management table that manages the correspondence between the reception buffer and the port is rewritten, By changing the corresponding reception buffer of the port to another normal reception buffer, it is possible to realize a multiprocessor system in which the transmission of the transmission data can be normally completed by the retransmission processing of the processor of the transmission source.

[0014]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1, and FIG. 2 is an explanatory diagram showing a format of each message packet at the time of message transmission. In FIG. 1, reference numerals 1 and 2 denote processors, and 3 denotes a bus. In this case as well, the processor 1 will be described as a transmission source and the processor 2 as a transmission destination. Reference numeral 20 is a transmission controller in the transmission source processor 1, 30 is a reception controller in the transmission destination processor 2, and the other functions of the processors 1 and 2 are not shown.

In the transmission controller 20, reference numeral 21 is a start packet buffer for storing the start packet shown in FIG. 2A, and 22 is a transmission start to a transmission end (retry timer section 25 to be described later). It is a transmission control unit that manages a series of operations up to (including transmission activation). Reference numeral 23 is a receive buffer for storing the received message, and 24 is a NG1 packet shown in FIG. 2B, an NG2 packet shown in FIG. 2C, or an OK packet shown in FIG. It is a decoder unit that makes a judgment and generates an activation condition whether to retransmit or not. Reference numeral 25 denotes a retry timer unit that monitors the number of retransmissions and the retransmission interval when the NG2 packet is received.

Further, in the reception controller 30, 31 is a reception buffer for storing the received message data, and 32 is a buffer for storing the message in the reception buffer 31 and then decoding, checking and NG1 of the message. It is a reception control unit that manages a series of operations on the reception side until generation / execution of a packet, an NG2 packet, and an OK packet. 33 indicates that when a reception buffer for storing message data is secured in the memory, the reception buffer permission register 34 for setting the bit of the secured buffer number and the set reception buffer number bit are receiving the message. And a reception buffer busy register 35 indicating Reference numeral 36 denotes an error detection unit that disables the reception buffer enable register 34 when an error occurs in the reception buffer, and 37 uses the destination port of the received start packet and the reception register unit to enable reception buffer use. It is judged that the receiving buffer is busy, and NG1 packet, NG
This is a decoder unit that controls the generation start condition of 2 packets and OK packet. 38 is OK / N for storing the generated NG1 packet, NG2 packet, and OK packet.
G return buffer.

Next, the operation will be described. First, as shown in FIG.
The start packet shown in (a) is transmitted. At this time,
A buffer number to be transmitted is set in the destination port portion in the start packet, and a code PID1 indicating the start packet is set in the PID portion. Processor 1
The start packet transmitted from the bus 3 enters the reception buffer 31 of the processor 2. Here, the decoder unit 37 decodes the buffer number of the destination port unit in the start packet and the buffer number bit set in the reception buffer permission register 34 to determine the presence or absence of the reception buffer, and the reception control unit 32 OK / NG
The packet generation start signal of 1 / NG2 is output. For example, if it is determined that the reception buffer is not permitted due to the occurrence of an abnormality in the reception buffer, the decoder unit 37 outputs a control signal for generating an NG1 packet (no buffer) to the reception control unit 32, and the reception control unit 32. ,
Upon receiving the signal, the NG1 packet shown in FIG.
It is generated in the K / NG return buffer 38 and the NG1 packet is transmitted to the processor 1 of the transmission source. At this time N
A code PID2 indicating that the packet is an NG1 packet is set in the PID part of the G1 packet.

On the other hand, if the use of the reception buffer is permitted, the decoder unit 37 next determines whether the designated buffer number is in use from the data of the destination port unit and the reception buffer busy register 35 in the start packet. to decide. For example, if it is determined that the receive buffer is in use,
A control signal for generating the NG2 packet (buffer in use) shown in FIG. 2C is output to the reception control unit 32. The reception control unit 32 receives the signal and fails NG2.
Generate a packet in the OK / NG return buffer 38,
The NG2 packet is transmitted to the processor 1. At this time, the code PID3 indicating the NG2 packet is set in the PID portion in the NG2 packet. If it is determined that the reception buffer is unused, the decoder unit 37 will be shown in FIG.
The control signal for generating the OK packet shown in is output to the reception control unit 32. The reception control unit 32 receives the signal, generates an OK packet in the OK / NG return buffer 38, and transmits the OK packet to the processor 1. At this time, the code PID4 indicating the OK packet is set in the PID portion in the OK packet.

NG sent from the destination processor 2
One of the 1 packet, the NG2 packet, and the OK packet is received by the reception buffer 23 of the processor 1 that is the transmission source.
to go into. Here, it is determined from the data of the PID portion in the packet received by the decoder unit 24 whether to retransmit or stop the transmission, and the start control signal is sent to the transmission control unit 2
Output to 2. For example, if the code of the PID part of the received packet is PID2 indicating the NG1 packet, the decoder part 24 outputs a transmission stop signal to the transmission control part 22, and the transmission control part 22 stops the subsequent transmission. If the code is PID3 indicating the NG2 packet, the decoder unit 24 activates the retry timer unit 25, and the transmission control unit 22 performs the same retransmission as in the conventional case. Furthermore, a code PID4 indicating an OK packet
If so, the transmission control unit 22 has confirmed the reception buffer of the transmission destination, and starts transmission of the subsequent data packets.

Example 2. In the first embodiment described above, the case where the transfer of the transmission data is stopped when the use of the reception buffer is not permitted due to the occurrence of an abnormality in the reception buffer has been described. Then, by executing the same processing as when the reception buffer is being used, it is possible to transfer the transmission data to the destination processor even if the reception buffer is not permitted to be used.

FIG. 3 is a block diagram showing an embodiment of the invention described in claim 2. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 4
0 is arranged in the processor 2 of the transmission destination, manages the correspondence between each port and the reception buffer, and when the error detection unit 36 detects an error in the reception buffer, associates 0 with the reception buffer in which the error is detected. It is a port / buffer management table that associates another normal reception buffer with the existing port. Reference numeral 50 denotes a central processing unit (hereinafter referred to as CPU) that controls the entire processor 2.

Next, the operation will be described. Now, when an abnormality occurs in the reception buffer of the processor 2 of the transmission destination, the error detection unit 36 disables the error reception buffer portion of the reception buffer permission register 34, and the CPU 50
Generate an interrupt to. Here, FIG. 4 shows this C
It is a flowchart which shows the interruption process of PU50.
When an interrupt occurs, the CPU 50 firstly proceeds to step ST
The reception buffer in which the error has occurred is confirmed by 1 and the address of the reception buffer in which the error has occurred in the port / buffer management table 40 is reset to another normal reception buffer address in step ST2. Even if a start packet is transmitted from the processor 1 during this process, the reception buffer permission register 34 is not permitted until the CPU 50 of the processor 2 permits the reception buffer, so an NG1 packet is sent to the processor 1. Then, the transmission control unit 22 of the processor 1 continues to control the retransmission of the transmission data.

After that, the port / buffer management table 4
When the change of 0 is completed, the CPU 50 of the processor 2 changes the error occurrence reception buffer portion of the reception buffer permission register 34 to permission in step ST3. After that, the processor 1 of the transmission source retransmits the same data to the processor of the same transmission destination, and thereafter, the processor 2 performs the same retransmission processing as that of the first embodiment.

[0024]

As described above, according to the first aspect of the present invention, when the processor of the transmission destination notifies that the reception buffer has been disabled due to the abnormality of the reception buffer, An error occurred in the receive buffer of the destination processor because it was configured to stop retransmitting the transmit data and retransmit the transmit data at a predetermined timing when the receive buffer is notified that it is in use. Thus, it is possible to obtain a multiprocessor system in which incorrect data is not stored or meaningless retransmission of transmitted data is not repeated.

According to the second aspect of the invention, a port / buffer management table for managing the correspondence between the reception buffer and the port is provided, and when an abnormality occurs in the reception buffer, the corresponding reception of the corresponding port is received. Since the buffer is configured to be changed to another normal receive buffer, even if the use of the receive buffer is not permitted, the transmission of the send data can be completed normally by the retransmission processing of the sender processor. The processor system is effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a format of each message packet when a message is transmitted in the above embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a flowchart showing CPU interrupt processing in the above embodiment.

FIG. 5 is a block diagram showing a conventional multiprocessor.

[Explanation of symbols]

 1, 2 processor 3 bus 15 counter 16 timer 22 transmission control unit 24 decoder unit 32 reception control unit 34 reception buffer enable register 35 reception buffer busy register 36 error detection unit 37 decoder unit 40 port / buffer management table

Claims (2)

[Claims] 1. When a plurality of processors are connected by a bus and reception of transmission data transmitted from the source processor is failed in the destination processor,
The processor of the transmission source, at a predetermined timing generated by a timer that defines the retransmission interval of the transmission data,
In the multiprocessor system that retransmits the transmission data to the destination processor until the count value of the counter that counts the number of retransmissions of the transmission data reaches a predetermined maximum number of retransmissions, A reception buffer permission register indicating to the processor permission to use the reception buffer, a reception buffer busy register indicating that the reception buffer is receiving, and a decoder unit for determining the reception buffer use permission and the reception buffer busy. An error detection unit for disabling the use of the reception buffer when an abnormality occurs in the reception buffer, and a reception control unit for controlling the transmission of return data for notifying the use of the reception buffer, reception buffer busy, etc. And a processor of the transmission source is provided with a processor of the transmission source. In the case where the receiving buffer is not permitted, the transfer is stopped without retransmitting the transmitting data according to the decoder unit that determines the transmitting data and the mobile condition generated by the decoder unit, and when the receiving buffer is busy. And a transmission control unit for controlling retransmission of the transmission data at the predetermined timing. 2. The processor of the transmission destination manages the correspondence between the reception buffer and the port, and when the error detection unit detects an abnormality in the reception buffer, it is associated with the reception buffer in which the abnormality is detected. A port / buffer management table for associating another normal reception buffer with the port that had been used, and the transmission control unit of the processor of the transmission source can retransmit the transmission data even when the use of the reception buffer is not permitted. The multiprocessor system according to claim 1, wherein the multiprocessor system is controlled.