JP2013246642A - Multiprocessor system, and interprocessor communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system and an interprocessor communication method for suppressing data loss in an interprocessor communication.SOLUTION: The multiprocessor system includes a first processor 11 for transmitting data, a second processor 12 for receiving data from the first processor 11, and a storage part 15 in which data is stored. The second processor 12 transmits a failure occurrence notification to the first processor 11 and, after performing restoration processing for the failure, transmits a restoration notification to the first processor 11. When receiving the failure occurrence notification, the first processor 11 stops data transmission and stores data to be transmitted in the storage part 15. After receiving the restoration notification, the first processor 11 transmits the data stored in the storage part 15 to the second processor 12.

Description

  The present invention relates to a multiprocessor system and an interprocessor communication method.

  In a communication device such as a router device, a multiprocessor system including a plurality of processors is used in order to perform load balancing for complicated processing. The plurality of processors execute their functions and transmit / receive data to / from each other. This inter-processor communication is not limited to a communication device, and is also used in other types of devices.

  Regarding inter-processor communication, for example, Patent Document 1 discloses a technique for acquiring error analysis information from a CPU (Central Processing Unit). Patent Document 2 discloses a technique for notifying a main processor of a sub processor failure.

JP-A-6-110858 Japanese Patent Laid-Open No. 10-271185

  In the inter-processor communication, when a failure occurs in one of the processors, the processor performs a failure content recording operation and a recovery operation such as a reset. At this time, since the processor cannot receive data transmitted from the other processor, data loss occurs. For example, in the case of a communication device, this data loss causes a failure such as a temporary interruption of a call or data communication.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a multiprocessor system and an interprocessor communication method that suppress data loss in interprocessor communication.

  The multiprocessor system described in the present specification includes a first processor that transmits data, a second processor that receives data from the first processor, and a storage unit that stores data. The second processor transmits a failure occurrence notification to the first processor, performs recovery processing of the failure, and then transmits a recovery notification to the first processor. The first processor When a failure occurrence notification is received, data transmission is stopped, data waiting to be transmitted is stored in the storage unit, and after the recovery notification is received, the data stored in the storage unit is stored in the second storage unit. Send to processor.

  In the inter-processor communication method described in the present specification, a step in which a second processor that receives data transmitted from a first processor transmits a failure notification to the first processor; When the processor receives the failure notification, stops the data transmission and stores the data waiting for transmission in the storage unit; and the second processor performs a recovery process of the failure; The second processor performs the recovery process, and then transmits a recovery notification to the first processor, and the first processor stores the recovery notification in the storage unit after receiving the recovery notification. Transmitting the processed data to the second processor.

  The multiprocessor system and the interprocessor communication method described in the present specification have an effect that data loss in interprocessor communication can be suppressed.

It is a block diagram which shows the structure of a radio | wireless communication network. It is a block diagram which shows the structure of a radio network control apparatus. It is a block diagram which shows the structure of a multiprocessor system. It is a block diagram which shows an example of call processing data. It is a block diagram which shows the function structure of a main processor and a sub processor. It is a flowchart which shows operation | movement of a sub processor. It is a flowchart which shows operation | movement of a 1st failure management part. It is a flowchart which shows operation | movement of a 2nd failure management part. It is a flowchart which shows operation | movement of a transmission process part. It is a ladder chart which shows the transmission / reception process of the information in a multiprocessor system.

  FIG. 1 is a configuration diagram showing a configuration of a wireless communication network. The radio communication network includes a plurality of radio network controllers (RNC: Radio Network Controller) 1, a plurality of radio base station apparatuses (BTS: Base Transceiver Station) 2, and a plurality of terminal devices 3. Further, the wireless network includes an operation system (OPS) 5, an IP / ATM converter (IWU) 6, and a mobile multimedia switching system (MMS) 4. The wireless communication network forms, for example, a W-CDMA (Wideband-Code Division Multiple Access) system.

  The terminal device 3 is a mobile communication device having a wireless communication function such as a mobile phone or a smartphone. The radio base station apparatus 2 is installed in the radio base station and relays communication of the terminal apparatus 3.

  The wireless network control device 1 is communicably connected to a plurality of wireless base station devices 2 via an IP / ATM converter 6 through optical fibers or the like. The IP / ATM converter 6 exchanges an Ethernet (registered trademark, hereinafter the same) frame that can be transmitted / received by the wireless network control device 1 and an ATM (ATM: Asynchronous Transfer Mode) cell that can be transmitted / received by the wireless base station device 2. Convert the format.

  The operation system 5 is a device for performing management control of the wireless network control device 1. The mobile multimedia switching system 4 is connected to a plurality of radio network control devices 1 via an IP network (IP: Internet Protocol) NW to form a data switching network.

  The wireless network control device 1 controls the plurality of wireless base station devices 2 to perform outgoing / incoming connection control, call termination control, diversity handover control, and the like. Diversity handover control includes selective combining processing of signals transmitted from the same terminal device 3 via a plurality of radio base station devices 2, replication distribution processing to the plurality of radio base station devices 2, and the like.

  FIG. 2 is a configuration diagram showing the configuration of the wireless network control device 1. The wireless network control device 1 includes a clock interface unit 1a, an inter-device interface unit 1b, a control signal termination unit 1c, a device control unit 1d, a signal processing unit 1e, and a switch unit 1f.

  The clock interface unit 1a receives a DCS (Digital Clock Supply) clock from the outside, generates an operation reference clock signal of the wireless network device 1, and distributes it to the units 1b, 1c, 1d, and 1e via the switch unit 1f. . The switch unit 1f is a layer 2 switch that switches message data transmitted and received between the units 1b to 1e.

  The inter-device interface unit 1b processes communication with other radio network control device 1, radio base station device 2, and mobile multimedia switching system 4. Communication is performed by, for example, gigabit Ethernet (GbE) technology. The control signal termination unit 1c terminates the control signal received from another radio network control device 1, the radio base station device 2, the mobile multimedia switching system 4, and the like.

  The device control unit 1d performs control signal termination processing from the operation system 5, OAM (Operation Administration and Maintenance) control, and the like. In addition to the above-described diversity handover control, the signal processing unit 1e performs control signal termination processing such as MAC (Media Access Control) layer demultiplexing processing and call processing of the radio channel.

  The wireless network control device 1 includes a multiprocessor system in order to perform high-speed and highly reliable processing. FIG. 3 is a configuration diagram showing the configuration of the multiprocessor system.

  The multiprocessor system according to the present embodiment is provided in a board unit provided with a call processing function in the signal processing unit 1e, but is not limited thereto, and is provided in other functional units 1b to 1d. May be. The multiprocessor system includes a main processor 11, a sub processor 12, an interrupt processing unit 13, a PCI (Peripheral Component Interconnect) bus 14, and interface units 101 and 102. The multiprocessor system further includes ROM (Read Only Memory) 171, 172, RAM (Random Access Memory) 161, 162, a buffer 15, and a failure information recording unit 18.

  The main processor 11 and the sub processor 12 are arithmetic processing circuits such as a CPU and a network processor. The main processor 11 is connected to the ROM 171, the RAM 161, and the storage unit 15. The sub processor 12 is connected to the ROM 172, the RAM 162, and the failure information recording unit 18. The ROMs 171 and 172 store programs to be operated by the main processor 11 and the sub processor 12, respectively. The RAMs 161 and 162 function as working memories for the main processor 11 and the sub processor 12, respectively.

  The main processor 11 receives message data including voice of a call and information of data communication from the other functional units 1b to 1d in the wireless network device 1 via the interface unit 101, and based on a predetermined protocol. Process. The main processor 11 also performs monitoring of network status by collecting statistical information of message data. In the following description, this message data is referred to as “call processing data”.

  FIG. 4 shows an example of call processing data. The call processing data includes a transmission source ID 70, a destination ID 71, a message ID 72, priority information 73, a message 74, and the like. The transmission source ID 70 and the destination ID 71 indicate a transmission source, a destination device, a software task, and the like, respectively. The message ID 72 indicates the message type, and the priority information 73 indicates the priority of the message. The message 74 is a data body.

  The main processor 11 transmits the processed call processing data to the sub processor 12 via the PCI bus 14. The sub processor 12 performs other processing not performed in the main processor 11 on the call processing data received from the main processor 11. Note that the call processing data is not limited to the PCI bus 14 and is transmitted and received by other communication means such as DMA (Direct Memory Access), I2C (Inter-Integrated Circuit), Ethernet, or SPI (Serial Peripheral Interface). Also good.

  The main processor 11 and the sub processor 12 transmit and receive various notifications via the interrupt processing unit 13. The interrupt processing unit 13 has a memory space accessible to the processors 11 and 12, and has a mask register and a status register corresponding to each notification. The main processor 11 and the sub processor 12 cancel the mask state of the mask register and set the status register to the active state, thereby causing the other processors 12 and 11 to generate an interrupt process corresponding to the corresponding status register. The mask register is again masked after the corresponding interrupt processing occurs. In this way, by transmitting and receiving notifications using interrupt processing, the main processor 11 and the sub processor 12 can immediately execute processing triggered by each notification. Note that the notification may be performed by other communication means described above.

  The processing related to the call processing data described above is performed by each function formed in the main processor 11 and the sub processor 12. FIG. 5 is a configuration diagram illustrating functional configurations of the main processor 11 and the sub processor 12.

  The main processor 11 includes a read processing unit 110, a transmission processing unit 111, a traffic monitoring unit 112, a first failure monitoring unit 113, a second failure management unit 114, and a communication processing unit 115. The sub-processor 12 includes a reception processing unit 121, a failure detection unit 122, a failure processing unit 123, a processor core 124, and a communication processing unit 125. Note that the units 110 to 115 and 121 to 125 operate based on an operating system incorporated in the program.

  The communication processing units 115 and 125 function as a communication driver and an interrupt driver, and process call processing data transmission / reception via the PCI bus 14 and notification transmission / reception via the interrupt processing unit 13, respectively. The transmission processing unit 111 of the main processor 11 transmits the call processing data received from the interface unit 101 to the sub processor 12 via the communication processing unit 115 and the PCI bus 14. The reception processing unit 121 of the sub processor 12 receives call processing data via the communication processing unit 125.

  The failure detection unit 122 detects a failure that has occurred in the sub processor 12. Examples of the failure include a watchdog timeout. The watchdog timeout occurs when the sub-processor 12 cannot issue a watchdog timer clear instruction for some reason. The failure is not limited to the watchdog timeout, and may be another error.

  When a failure is detected, the failure detection unit 122 performs autonomous reset prohibition setting for the processor core 124 in order to perform failure notification and record failure information prior to the recovery process. The failure detection unit 122 activates the failure processing unit 123 as an interrupt process.

  The failure processing unit 123 records information regarding the failure in the failure information recording unit 18. When the failure is a watchdog timeout, the information includes the content of the failure factor register of the sub processor 12 collected by the dump process. The failure information recording unit 18 is a recording unit such as a RAM or a ROM, and is accessed from the failure processing unit 123 via a memory driver. The failure information recording unit 18 may be included in at least one of the RAM 162 and the ROM 172.

  Further, the failure processing unit 123 transmits a failure notification to the main processor 11 via the communication processing unit 115. At this time, the communication processing unit 115 causes the main processor 11 to generate an interrupt process by accessing the mask register and the status register of the interrupt processing unit 13.

  The communication processing unit 125 of the main processor 11 activates the first failure management unit 113 as an interrupt process when a failure occurrence notification is made. The first failure management unit 113 updates the failure management information 161b stored in the RAM 161 to a “failed” state.

  The transmission processing unit 111 refers to the failure management information 161b. When the failure management information 161b indicates “failed”, the transmission processing unit 111 stops the transmission of call processing data and stores call processing data waiting for transmission in the storage unit 15. . For this reason, the transmission processing unit 111 does not transmit call processing data to the sub-processor 12 in which a failure has occurred.

  The accumulation unit 15 is a RAM, for example, and functions as a buffer in which call processing data is accumulated. The storage unit 15 is described as being configured separately from the RAM 161, but may be included in the RAM 161 or may be another data storage unit such as a hard disk drive.

  In addition, the first failure management unit 113 acquires information indicating the traffic volume of the call processing data from the traffic monitoring unit 112, and updates the traffic information 161a stored in the RAM 161 based on this information. For example, the traffic information 161a is updated to indicate “large” when the traffic volume of the call processing data is greater than a predetermined threshold, and to indicate “small” when the traffic volume is small. That is, the traffic information 161a indicates the traffic volume of call processing data at the time when a failure occurs.

  The transmission processing unit 111 refers to the traffic information 161 a, and stores only the call processing data in which the priority information 73 indicates high priority in the storage unit 15 when the traffic information 161 a indicates “large”. On the other hand, when the traffic information 161 a indicates “low”, the transmission processing unit 111 stores all call processing data in the storage unit 15 without depending on the priority information 73. As described above, the main processor 11 selects the call processing data to be stored in the storage unit 15 according to the traffic volume of the call processing data to be transmitted. Therefore, the storage unit 15 can be used efficiently. Note that the above selection method is an example, and other methods may be used.

  The traffic monitoring unit 112 monitors traffic of call processing data input to the interface unit 101 at time intervals. The traffic monitoring unit 112 statistically calculates the traffic volume in response to a request from the first fault management unit 113 and outputs information indicating the traffic volume to the first fault management unit 113.

  After receiving the failure occurrence notification, the first failure management unit 113 transmits a recovery instruction to the sub processor 12 via the communication processing unit 115 and the interrupt processing unit 13. In the sub processor 12, the failure processing unit 123 receives a recovery instruction via the communication processing unit 125. The failure processing unit 123 performs failure recovery processing after receiving the recovery instruction. More specifically, the failure processing unit 123 issues a reset command to the processor core 124 in accordance with the recovery instruction.

  When receiving the reset instruction, the processor core 124 activates the reset vector, reads the BOOT program 172a stored in the ROM 172, and executes it. The processor core 124 performs processing such as initialization of the processor 12 by executing the BOOT program 172a. For this reason, the processor 12 cannot receive call processing data while the BOOT program 172a is being executed. After performing the recovery process, that is, reset, the processor core 124 transmits a recovery notification to the main processor 11 via the communication processing unit 125 and the interrupt processing unit 13.

  As described above, the main processor 11 transmits a recovery instruction to the sub-processor 12 after receiving the failure occurrence notification. Further, after receiving the recovery instruction from the main processor 11, the sub processor 12 performs a recovery process. Therefore, the process timing matching between the processors 11 and 12 when a failure occurs is effectively performed.

  The communication processing unit 125 of the main processor 11 activates the second failure management unit 114 as an interrupt process when a recovery notification is made. The second failure management unit 114 updates the failure management information 161b stored in the RAM 161 to a “no failure” state. The transmission processing unit 111 refers to the failure management information 161b. When the failure management information 161b indicates “no failure”, the transmission processing unit 111 transmits the call processing data to the sub-processor 12 without accumulating in the accumulation unit 15.

  Further, the second failure management unit 114 activates the read processing unit 110. The read processing unit 110 transmits the call processing data stored in the storage unit 15 to the sub processor 12 via the communication processing unit 115 and the PCI bus 14. Transmission is performed until there is no call processing data stored in the storage unit 15. The transmitted call processing data is received by the reception processing unit 121 via the communication processing unit 125 in the sub processor 12.

  As described above, when the main processor 11 receives the failure notification, the main processor 11 stops the transmission of the call processing data, stores the data waiting for transmission in the storage unit 15, receives the recovery notification, and then stores the storage unit 15. Is transmitted to the sub-processor 12. Accordingly, the main processor 11 does not transmit call processing data to the sub-processor 12 during the occurrence of a failure or during recovery processing (reset), and the accumulated call processing data is transmitted after recovery from the failure. Loss of call processing data in is suppressed.

  Next, operations when a failure occurs in the main processor 11 and the sub processor 12 will be described with reference to FIGS. FIG. 6 shows the operation of the sub processor 12. In the following description, the ladder chart shown in FIG. 10 will be referred to as appropriate.

  When the failure detection unit 122 detects the occurrence of a failure (YES in step St1), the failure detection unit 122 performs autonomous reset prohibition setting on the processor core 124 (step St2). The reset prohibition setting is performed when an autonomous reset is involved, as in the illustrated watchdog timeout, and may not be performed otherwise.

  Next, the failure processing unit 123 starts as interrupt processing, collects information regarding the failure, and records it in the failure information recording unit 18 (step St3). Here, the failure processing unit 123 may record the failure information recording unit 18 in the failure information recording unit 18 using the file system of the processor 12 itself, but is not limited thereto.

  For example, the failure processing unit 123 may transmit the information to the main processor 11 via the communication processing unit 125 and record the information in a recording unit such as a RAM using the file system of the main processor 11. The failure processing unit 123 may perform the recording process by accessing an external file server via a network. Further, the failure processing unit 123 acquires the capacity values of the file system of the processor 12, the file system of the main processor 11, and the external file server, and compares them with the information amount of the information. What can be stored may be selected.

  Next, the failure processing unit 123 transmits a failure occurrence notification to the main processor 11 as indicated by reference numeral C3 in FIG. 10 (step St4). The failure occurrence notification may include information such as the failure type, the failure factor, and the occurrence time. Note that the failure occurrence notification may be performed prior to the processing in step St3.

  The failure processing unit 123 performs standby processing after transmitting a failure occurrence notification. When the failure processing unit 123 receives a recovery instruction from the main processor 11 (YES in Step St5), as shown by a symbol C4 in FIG. 10, the failure processing unit 123 restarts the processing.

  The failure processing unit 123 issues a reset command to the processor core 124 as indicated by reference numeral C7 in FIG. 10 (step St6). Then, the processor core 124 activates the reset vector according to the reset instruction (step St7). As a result, the BOOT program 172a is executed.

  Next, the processor core 124 transmits a recovery notification to the main processor 11 (step St6) and performs initialization processing of its own processor 12 (step St9), as indicated by reference numeral C8 in FIG. Exit. In this way, the processing of the sub processor 12 is executed.

  FIG. 7 is a flowchart showing the operation of the first failure management unit 113. When the first failure management unit 113 receives a failure occurrence notification from the sub-processor 12 (YES in step St11) as indicated by reference numeral C3 in FIG. The state is updated to “present” (step St12). Thereby, the transmission processing unit 111 stops the transmission of the call processing data indicated by the symbols C1 and C2 in FIG. 10 and accumulates the call processing data in the storage unit 15 as indicated by the symbols C4 and C5.

  Next, the first failure management unit 113 updates the traffic information 161 a to a “large” or “small” state based on the traffic volume of the call processing data acquired by requesting the traffic monitoring unit 112. The transmission processing unit 111 selects call processing data to be stored in the storage unit 15 according to the traffic information 161a.

  Next, as indicated by reference numeral C6 in FIG. 10, the first failure management unit 113 transmits a recovery instruction to the sub processor 12 (step St14), and ends the process. In this way, the process of the first failure management unit 113 is executed.

  FIG. 8 is a flowchart showing the operation of the second failure management unit 114. When the second failure management unit 114 receives a recovery notification from the sub-processor 12 (YES in step St15) as indicated by reference numeral C8 in FIG. 10, the second failure management unit 114 is activated as an interrupt process and sets the failure management information 161b to “no failure”. (Step St16). As a result, the transmission processing unit 111 stops the call processing data accumulation process indicated by reference numerals C4 and C5 in FIG. 10, and transmits the call processing data to the sub-processor 12 as indicated by reference numerals C12 and C13. Resume.

  Next, the second failure management unit 114 outputs a read instruction indicated by reference numeral C9 in FIG. 10 to the read processing unit 110 (step St17). As a result, the read processing unit 110 reads the call processing data from the storage unit 15 and transmits it to the sub-processor 12 as indicated by reference numerals C10 and C11 in FIG. 10 (step St18). The second failure management unit 114 ends the process when all the call processing data stored in the storage unit 15 is transmitted. In this way, the process of the second failure management unit 114 is executed.

  FIG. 9 is a flowchart showing the operation of the transmission processing unit 111. The transmission processing unit 111 is activated when call processing data is input through the interface unit (YES in step St21), as indicated by reference numerals C1, C4, and C12 in FIG. The transmission processing unit 111 refers to the failure management information 161b. If the failure management information 161b indicates “no failure” (YES in step St22), the call waiting for transmission is displayed as indicated by reference numerals C2 and C13 in FIG. The processing data is transmitted to the sub processor 12 (step St23), and the processing is terminated.

  On the other hand, when the failure management information 161b indicates “failed” (NO in step St22), the transmission processing unit 111 refers to the traffic information 161a (step St24). When the traffic information 161a indicates “large” (YES in step St24), the transmission processing unit 111 determines the priority information 73 of the call processing data (step St25).

  If the priority information 73 indicates high priority (YES in step St25), the transmission processing unit 111 stores call processing data waiting for transmission in the storage unit 15 as indicated by reference numeral C5 in FIG. St26), the process ends. On the other hand, if the priority information 73 does not indicate high priority (such as low priority) (NO in step St25), the transmission processing unit 111 ends the process without accumulating call processing data.

  When the traffic information 161a indicates “low” (NO in step St24), the transmission processing unit 111 stores the call processing data in the storage unit 15 regardless of the priority of the call processing data (step St26). The process is terminated. In this way, the process of the second failure management unit 114 is executed.

  As described above, the multiprocessor system according to the embodiment includes a main processor 11 that transmits call processing data, a sub-processor 12 that receives call processing data from the main processor 11, and an accumulation in which call processing data is stored. Part 15. The sub-processor 12 transmits a failure occurrence notification to the main processor 11, performs recovery processing of the failure, and then transmits a recovery notification to the main processor 11. On the other hand, when the main processor 11 receives the failure notification, the main processor 11 stops the transmission of the call processing data, stores the call processing data waiting for transmission in the storage unit 15, receives the recovery notification, and then stores the call processing data. Is transmitted to the sub-processor 12.

  Therefore, the main processor 11 can recognize that a failure has occurred in the sub-processor 12 and save the call processing data waiting for transmission in the storage unit 15 without transmitting it to the sub-processor 12. Further, the main processor 11 can recognize that the sub processor 12 has performed the failure recovery process, and can transmit the call processing data saved in the storage unit 15 to the sub processor 12. Therefore, call processing data is not transmitted to the sub-processor 12 in which a failure occurs or recovery processing (reset) is being performed, and loss of call processing data is suppressed.

The inter-processor communication method using the main processor 11 and the sub processor 12 includes the following steps (1) to (6) described above.
(1) The sub-processor 12 that receives the call processing data transmitted from the main processor 11 transmits a failure occurrence notification to the main processor 11 (step St4 in FIG. 6).
(2) When the main processor 11 receives the failure occurrence notification, the main processor 11 stops transmitting data and stores call processing data waiting for transmission in the storage unit 15 (step St26 in FIG. 9).
(3) The main processor 11 receives a failure occurrence notification and then transmits a recovery instruction to the sub processor 12 (step St14 in FIG. 7).
(4) Step of the failure recovery processing after the sub processor 12 receives the recovery instruction (step St6 in FIG. 6)
(5) The sub-processor 12 performs a recovery process and then transmits a recovery notification to the main processor 11 (step St8 in FIG. 6).
(6) Step of transmitting the data stored in the storage unit 15 to the sub-processor 12 after the main processor 11 receives the recovery notification (step St18 in FIG. 8)

  Therefore, the above-described effects can be obtained by this inter-processor communication method. In the present embodiment, call processing data is given as an example of data, but the present invention is not limited to this, and other data may be used.

  In the present embodiment, the call processing data is transmitted from the main processor 11 to the sub-processor 12, and is stored in the storage unit 15 by the main processor 11 when a failure occurs. The roles of the sub-processors 12 may be interchanged with each other.

  That is, data transmitted from the sub processor 12 to the main processor 11 may be stored in the storage unit by the sub processor 12 when a failure occurs in the main processor 11. In this case, the sub processor 12 reads data from the storage unit and transmits it to the main processor 11 after the main processor 11 performs failure recovery processing. Also in this case, the above-described effects can be obtained.

  Although the contents of the present invention have been specifically described above with reference to the preferred embodiments, it is obvious that those skilled in the art can take various modifications based on the basic technical idea and teachings of the present invention. It is.

In addition, the following additional notes are disclosed regarding the above description.
(Supplementary note 1) a first processor for transmitting data;
A second processor for receiving data from the first processor;
A storage unit for storing data;
The second processor transmits a failure occurrence notification to the first processor, performs the failure recovery process, and then transmits a recovery notification to the first processor.
When the first processor receives the failure occurrence notification, the first processor stops data transmission, accumulates data waiting to be transmitted in the storage unit, receives the recovery notification, and then accumulates the data in the storage unit. A multiprocessor system, wherein the data is transmitted to the second processor.
(Supplementary Note 2) After receiving the failure occurrence notification, the first processor sends a recovery instruction to the second processor,
The multiprocessor system according to appendix 1, wherein the second processor performs the recovery process of the failure after receiving the recovery instruction.
(Supplementary note 3) The multiprocessor system according to Supplementary note 1 or 2, wherein the first processor selects data to be accumulated in the accumulation unit according to a traffic amount of data to be transmitted.
(Supplementary note 4) a second processor that receives data transmitted from the first processor transmits a failure occurrence notification to the first processor;
When the first processor receives the failure notification, stops transmitting data and accumulates data waiting to be transmitted in an accumulation unit;
The second processor performing the failure recovery process;
The second processor, after performing the recovery process, sending a recovery notification to the first processor;
And a step of transmitting the data stored in the storage unit to the second processor after the first processor receives the recovery notification.
(Supplementary Note 5) The first processor includes a step of transmitting a recovery instruction to the second processor after receiving the failure occurrence notification,
The interprocessor communication method according to appendix 4, wherein the second processor performs the failure recovery process after receiving the recovery instruction.
(Additional remark 6) The said 1st processor selects the data accumulate | stored in the said accumulation | storage part according to the traffic amount of the data to transmit, The interprocessor communication method of Additional remark 4 or 5 characterized by the above-mentioned.

1 wireless network control device 11 main processor (first processor)
12 Sub-processor (second processor)
15 Accumulator

Claims (4)

A first processor for transmitting data;
A second processor for receiving data from the first processor;
A storage unit for storing data;
The second processor transmits a failure occurrence notification to the first processor, performs the failure recovery process, and then transmits a recovery notification to the first processor.
When the first processor receives the failure occurrence notification, the first processor stops data transmission, accumulates data waiting to be transmitted in the storage unit, receives the recovery notification, and then accumulates the data in the storage unit. A multiprocessor system, wherein the data is transmitted to the second processor. The first processor, after receiving the failure occurrence notification, transmits a recovery instruction to the second processor;
2. The multiprocessor system according to claim 1, wherein the second processor performs the failure recovery processing after receiving the recovery instruction. 3.   The multiprocessor system according to claim 1, wherein the first processor selects data to be stored in the storage unit according to a traffic amount of data to be transmitted. A second processor that receives data transmitted from the first processor, and transmits a failure occurrence notification to the first processor;
When the first processor receives the failure notification, stops transmitting data and accumulates data waiting to be transmitted in an accumulation unit;
The second processor performing the failure recovery process;
The second processor, after performing the recovery process, sending a recovery notification to the first processor;
And a step of transmitting the data stored in the storage unit to the second processor after the first processor receives the recovery notification.

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