JPH05265606A - Electronic apparatus - Google Patents

Abstract

PURPOSE:To make it possible to attain a prescribed function at a set time even if long service interruption is generated by resetting the set time erased by the service interruption. CONSTITUTION:This electronic apparatus is provided with a set time storing means (set time data memory) 5a capable of storing set time even at the time of service interruption, a power restoration detecting means (relay control circuit) 35 for detecting power restoration from service interruption status and a time set control means for controlling a time setting means 44 at the time of detecting power restoration by the means 35 and setting up the set time stored by the means 5a. At the time of restoring the generated service interruption, the means 35 detects power restoration from the service interruption status. When the power restoration is detected, the set time control means controls the means 44 to set up the set time stored in the means 5a. Thereby, when a time counting means counts up the time set up by the means 44, prescribed operation is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device that performs a predetermined operation when a set time is measured.

[0002]

2. Description of the Related Art In an electronic device, such as a terminal device controlled by a store controller, a store opening process is performed at the start of a day's work, and a store closing process is performed at the end of the work. The opening process and the closing process require a required time, and the user of the terminal device has to wait until the opening process is completed to actually start the business, and the closing process is completed to turn off the power. I have to wait until.

Therefore, in the conventional terminal device, the APS
It is known that a device (automatic power supply startup device) is provided to automatically turn on / off the main power supply of the device body.
If you set the power-on time, the APS device
When the timer provided inside the device measures the set startup time, it supplies power to the main power supply of the device body,
The stop signal from the device body stops the power supply to the main power supply of the device body.

In such a terminal device, an opening process is performed as a process when the power is turned on by supplying power to the main power source, and a stop signal is given when the closing process performed at the end of the day's work is completed. By setting to output to the APS device, the user does not have to wait until the opening process and the closing process are completed.

[0005]

By the way, in the APS device provided in the conventional terminal device, the memory for storing the startup time of the main power supply is backed up, but in case of a power failure for several minutes or more, There was no guarantee of what was stored in memory. That is, there is a fear that the contents of the memory cannot be completely stored and held due to a power failure that is longer than the backup time. Therefore, if a power failure occurs for several minutes or more, the set start-up time may be lost.

Then, the terminal device does not supply power to the main power source at the set time, and the normal store opening process is not performed at the predetermined time.

Generally, in an electronic device, the memory for storing the set time is not guaranteed in the stored contents even after a long power failure. That is, there is a problem that the electronic device cannot perform its function at the set time when a long power failure occurs.

Therefore, the present invention aims to provide an electronic device capable of resetting a set time erased by a power failure and performing a predetermined function at the set time even if a long power failure occurs. And

[0009]

SUMMARY OF THE INVENTION The present invention comprises a time measuring means for measuring the time and a time setting means for setting the time, and a predetermined operation is performed when the time measuring means measures the time set by the time setting means. In an electronic device that performs the above, set time storage means that stores and holds the set time even during a power failure, power recovery detection means that detects that power is recovered from the power failure state, and time setting is performed when power recovery is detected by this power recovery detection means. And a time setting control means for controlling the means to set the set time stored and held by the set time storage means.

[0010]

In the present invention having such a structure, when a power failure occurs and then the power is restored, the power recovery detecting means detects the power recovery from the power failure state. Upon detection of this power recovery, the time setting control means controls the time setting means to set the set time stored and held in the set time storage means.

Therefore, when the time measuring means measures the time set by the time setting means, a predetermined operation is performed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a terminal device, and 1 is a CPU (central
processing unit). A ROM (read only memo) in which program data for processing performed by the CPU 1 is stored
ry) 2, a RAM (random access me) in which areas of various memories used when the CPU 1 performs processing are formed.
3), a non-volatile memory 4 for storing the state of the CPU 1 at the time when a power failure occurs during the processing of the CPU 1, and a set time storage in which power is supplied by a battery and a set time is stored. The clock IC 5 having the set time data memory 5a as means is a system bus 6
It is connected to the CPU 1 via.

A keyboard controller 8 for controlling the keyboard 7, a display controller 10 for controlling the display device 9,
An APS (automatic power supply start-up) board 11 and a communication I / F (interface) 12 connected to the inline master machine via a line are also connected to the CPU 1 via the system bus 6.

FIG. 2 shows a block diagram of the main configuration of the power supply circuit. The power from the power source (AC100V) 21 is
The power is supplied to the main body power supply section 22 via the PS board 11. A power switch 23 is provided on the power supply line from the APS board 11 to the main body power supply 22.
However, the power switch 23 is normally kept in the ON state.

FIG. 3 shows a block diagram of a circuit configuration of a main part of the APS board 11.

The alternating current from the power source 21 is input from the I input terminal. The input alternating current is stepped down to a predetermined voltage by the transformer 31, and a direct current of +5 V is obtained via the rectifier circuit 32 and the constant voltage circuit 33. This + 5V DC current is transmitted to the APS via the first diode 34.
It is output as the control power supply for the board 11.

The output from the cathode terminal of the first diode 34 is input to a relay control circuit 35 as a power recovery detecting means. When the relay control circuit 35 detects the rising of the input voltage, The voltage of the output terminal connected to the base terminal of the relay control transistor 36 is set to the high level. The emitter terminal of the transistor 36 is connected to the ground, and the collector terminal thereof is connected to the control power source + 5V through the exciting coil 38 of the relay in which the second diode 37 is connected in parallel.

An O output terminal connected to the main body power source section 22 is connected to the I input terminal through a normally open contact 39 of the relay. Therefore, when the voltage of the output terminal connected to the base terminal of the transistor 36 of the relay control circuit 35 becomes high level, the transistor 36 is turned on, the exciting coil 38 is energized, and the normally open contact 39 is opened. By the closing operation, the alternating current from the power source 21 is output from the I terminal to the main body power source section 22 via the O output terminal.

The + 5V current of the device body, which is input to the 5V input terminal from the terminal device body, is connected to the control power source + 5V through the third diode 40. The input + 5V current is also input to the main body power supply monitoring circuit 41. The main body power supply monitoring circuit 41 outputs a low level when + 5V current is input and outputs a high level when + 5V current is not input. The output signal of the main body power supply monitoring circuit 41 is connected to one input terminal of the AND circuit 42, and the other input terminal of the AND circuit 42 is CI input from a modem (not shown) connected to a public line. The CI signal input to the terminal is input. The signal output from the output terminal of the AND circuit 42 is input to the relay control circuit 35.

Further, from the terminal device main body to the D0 input terminals to D
The set time data input to the 7 input terminal is controlled by the control signal from the data set control circuit 43 to which the strobe signal input to the STB input terminal and the set enable signal input to the SETEN input terminal are input from the terminal body. , A latch circuit 44 as time setting means
Is latched by (data retention). Further, the oscillation pulse output from the oscillation circuit 45 is input to a counter circuit 46 serving as time counting means, and this counter circuit 46 counts the time by counting the input oscillation pulse. The set time data latched in the latch circuit 43 and the measured time data counted by the counter circuit 46 are respectively input to a comparison circuit 47, and compared by the comparison circuit 47, when the set time data and the measured time data match. A low level is output to the relay control circuit 35.

Furthermore, the power supply start signal inputted from the in-line master unit to the N + input terminal and the N- input terminal is
It is input to the RPC (remote power control) starting voltage sense circuit 48. The signal output from the output terminal of the RPC activation voltage sense circuit 48 is the buffer 4
The signal is input to the relay control circuit 35 via 9 and the RPC start voltage sense circuit 48 sets the signal from the output terminal to a low level by the power supply start signal from the inline master machine.

When the relay control circuit 35 detects the fall of the output signals from the AND circuit 41, the comparison circuit 47 and the buffer 49, it outputs a high signal from the output terminal connected to the base terminal of the transistor 36. It is designed to be level.

In FIG. 4, when power is restored after a power failure occurs, that is, the relay control circuit 35 detects the rising of the control power source + 5V input from the constant voltage circuit 33 via the first diode 34. The flow of power recovery processing performed by the CPU 1 when the terminal device body is powered on will be described.

First, it is judged from the information stored in the non-volatile memory 4 whether or not there was a power failure during work. If there was a power outage during work, a reboot process that reproduces the state at the time of interruption due to a power outage is performed based on the information stored in the non-volatile memory 4, and the processing of the remaining work is started. The power recovery process is completed.

If there is no power outage during work, the set time data stored in the set time data memory 5a of the clock IC 5 is read. Next, for the APS board 11,
First, the set enable signal is output, the read set time data is output, and finally the strobe signal is output to cause the latch circuit 43 of the APS board 11 to latch the set time data. (Time setting control means) When the latching of the set time data is completed, this power recovery process is completed.

In the present embodiment having such a configuration, in the normal operation, when the power supply AC100V is supplied,
A current of AC 100V is supplied to the APS board 11, and the constant voltage circuit 33 outputs the control power supply + 5V. The rise of the control power supply + 5V is detected by the relay control circuit 35, the transistor 36 is turned on, and the normally open contact 39 of the relay is closed.

Here, as shown in FIG. 5A, the rise time data set in the latch circuit 43 by comparison by the comparison circuit 47 and the clock time data by the counter circuit 46 match or the modem. When the CI signal is input or the power supply start signal is input from the in-line master machine, the relay control circuit 35 turns on the normally open contact 39 (time A). At this time, AC 100 V is supplied to the main body power supply unit 22, the system program is started by turning on the power supply, and the business application program is executed. Business is performed by executing this business application program, and at the end of the business for one day, closing business processing is performed. At the end of the closing business process, the next start-up time data stored in the set time data memory 5a of the clock IC 5 is set in the latch circuit 43 of the APS board 11, and the relay control circuit 35 is controlled by the CPU 1 to switch the transistor. 36 is turned off, and the normally open contact 39 of the relay is opened (B
Time point). At this time, the AC 100V power supply to the main body power supply unit 22 is stopped.

In the APS board 11, the comparison circuit 47
By comparing the start time data set in the latch circuit 43 with the clock time data by the counter circuit 46, or the CI signal from the modem is input, or the power supply start signal from the inline master machine. When is input, the transistor 36 is turned on by the relay control circuit 35, the normally open contact 39 of the relay is closed, and the power supply of AC 100 V to the main body power supply unit 22 is restarted (time C). When the power is turned on, the system program is activated and the opening business process is performed.

When a power failure occurs next, for example, as shown in FIG.
As shown in (b), if a power failure occurs during the closing operation processing (at time D), the state of the CPU 1 at that time is stored in the non-volatile memory 4 during the voltage drop due to the power failure. Then, at the time of power recovery (time E), the rise of the control power supply + 5V output from the constant voltage circuit 33 is detected by the relay control circuit 35, the transistor 36 is turned on, and the normally open contact 39 of the relay is closed. Becomes Therefore,
100 VAC power is supplied to the main body power supply unit 22, and the CPU is stored in the nonvolatile memory 4 by the reboot function.
The interruption state due to the power failure is reproduced based on the data of the state 1 and the nonvolatile memory 4 is cleared. The rest of the closing business process is performed from the reproduced suspended state. Therefore, at the end of the closing business process, the next rising time data stored in the set time data memory 5a of the clock IC 5 is set in the latch circuit 43. The relay control circuit 35 is the CPU
The transistor 36 is turned off under the control of 1 and the normally open contact 39 of the relay is opened (at the time point F). At this time, the AC 100V power supply to the main body power supply unit 22 is stopped.

Further, the AC 10 to the main body power source unit 22 is
If a power failure occurs when the 0V power supply is stopped (time point G), at the time of the power recovery (time point H), the rise of the control power source + 5V output from the constant voltage circuit 33 causes the relay control circuit 35 to rise. Then, the transistor 36 is turned on, and the normally open contact 39 of the relay is closed. Therefore, AC 100V power is supplied to the main body power supply unit 22. At this time, C is stored in the nonvolatile memory 4.
Since the data of the state of PU1 is not stored, it is determined that it is not a power failure during work, the next rising time data stored in the set time data memory 5a of the clock IC 5 is set in the latch circuit 43, and the relay control is performed again. The circuit 35 is controlled so that the normally open contact 39 is closed (at the time point I), and the power supply of 100 V AC to the main body power supply unit 22 is stopped.

If the CI signal from the modem and the power activation signal from the in-line master unit are not input, the comparison circuit 47 compares the startup time data set in the latch circuit 43 with the time measured by the counter circuit 46. When the data matches, the transistor 36 is turned on by the relay control circuit 35, the power supply of AC100V to the main body power supply unit 22 is started (time J), and the opening operation processing is performed.

As described above, according to the present embodiment, the relay control circuit 35 for detecting the rise of the control power source + 5V when the power is restored even if a power failure occurs is provided with the APS board 11.
The AC power is supplied to the main body power supply unit 22 by the output from the relay control circuit 35, and the main CPU 1 processes the latch circuit 43 provided on the APS board 11 to reset the next rising time. By setting it, the next rising time can be set again in the latch circuit 43 whose setting time has been erased due to the power failure. Moreover, in this process, since a backup battery is not required, the set time can be set again when the power is restored even if a long-term power failure occurs. The function of performing processing can be surely fulfilled.

Although the terminal device integrated by the in-line master machine has been described in this embodiment, the present invention is not limited to this, and the operation time is set in advance and based on the set time. The present invention can be applied to electronic devices that operate with a timer. Further, in this embodiment, a battery-backed watch I
The set time was stored in the set time data memory 5a built in the C5, but the present invention is not limited to this, and the set time is stored in, for example, a hard disk device or the like. good.

[0034]

As described in detail above, according to the present invention,
You can reset the set time that was erased due to a power failure,
It is possible to provide an electronic device that can perform a predetermined function at a set time even if a long power failure occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of essential parts of an embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration of a power supply circuit of the embodiment.

FIG. 3 is a block diagram showing a circuit configuration of essential parts of the APS board of the embodiment.

FIG. 4 is a diagram showing a flow of a power recovery process of the embodiment.

FIG. 5 is a diagram showing timings of an AC100V power supply state, a power input state to a main body power supply unit, and an ON / OFF state of a normally-open contact according to the embodiment.

[Explanation of symbols]

1 ... CPU, 5 ... Clock circuit, 5a ... Set time data memory, 11 ... APS board, 35 ... Relay control circuit 35, 36 ... Transistor, 38 ... Excitation coil, 39
... Normally open contact, 43 ... Latch circuit, 46 ... Counter, 47
… Comparison circuit.

Claims (1)

[Claims] 1. An electronic device comprising a time measuring means for measuring a time and a time setting means for setting a time, and performing a predetermined operation when the time measuring means measures the time set by the time setting means, A set time storage means for storing and holding the set time even during a power failure, a power recovery detection means for detecting a power recovery from a power failure state, and a time setting means is controlled when the power recovery is detected by the power recovery detection means. An electronic device comprising: a time setting control means for setting the set time stored and held by the set time storage means.