JPH05265587A - Clock margin test device - Google Patents

Abstract

PURPOSE:To perform a clock margin test by realizing miniaturization and with the smaller number of components and smaller man-hours and to perform the test even in a state near to the one where a device is manufactured when it is operated with a normal clock and a user uses the device. CONSTITUTION:A margin clock generator 6 of a portable size installed at the outside of the device is connected to a one-touch device 5, and the operating characteristic of the device 5 in every waveform can be automatically tested by switching the frequency of a margin clock, a duty, potential, and the value of a phase set at random values in advance by the control of a service processor 4 sequentially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock margin test apparatus which is switched under the control of a service processor so that a user can perform a margin test of a clock for operating an information processing apparatus. is there.

[0002]

2. Description of the Related Art A semiconductor incorporated in an information processing device has its operating speed improved year by year due to the progress of process technology. As a result, information processing devices that use semiconductors
Since it can be operated with a high-speed clock, the total throughput can be improved. When performing an operation test of an information processing apparatus, a method of checking the system stability or extracting a logic design error is often used by a clock margin test in which the frequency of an operation clock is changed. As a conventional example of the clock margin tester, for example, Japanese Patent Laid-Open No. 55-33258 (see FIG. 1), or Japanese Patent Laid-Open No. 58-10793.
No. 0 publication. The former case will be described with reference to FIGS. 2 and 3 show a conventional clock marker.
It is a block diagram of a gin test device. In FIG. 2, the user operates the standard signal generator to switch the characteristics of the margin clock. In FIG. 2, reference numeral 1 is a clock unit that selects either a margin clock or a normal clock and supplies a system clock 150 to the processing unit 3. Reference numeral 2 is a clock switching circuit.
Is a processing unit that executes processing in synchronization with the system clock 150, 4 is a service processor (hereinafter, SVP), 5 is an information processing device, SG is a standard signal generator, and XNORM is a signal that generates a normal clock. The generator and CON are connectors for connecting SG. The SG can generate a signal by continuously changing the frequency by turning a screw, for example. First, the built-in signal generator XNO
The normal clock generated from the RM is supplied as the clock 150 of the processing unit 3 to operate the processing unit 3, and then the SVP 4 activates the clock switching circuit 2 to set the SG set to an arbitrary frequency. The clock is switched to the clock from No. 1, and this margin clock is supplied to the processing unit 3 to operate. In FIG. 3, instead of the external SG, an oscillator circuit XFAST that generates a clock having a frequency higher than the normal clock and an oscillator circuit XSLOW that generates a clock having a frequency lower than the nominal clock are provided in the clock unit 1. It is built in. In this case as well, the SVP 4 activates the clock switching circuit 2 to switch from the normal clock to the margin clock having a higher or lower frequency and supply this margin clock to the processing unit 3. To operate.

[0003]

However, the above-described methods of FIGS. 2 and 3 have the following problems. (A) In the device of FIG. 2, (a-1) SG can continuously change the output frequency, but is expensive.
(A-2) Since SG is large and heavy, it is troublesome to carry, and (a-3) it is difficult to perform the clock margin test by SG at the place where the user uses it. -4) A power supply for driving the SG is required, and (a-5) the SG cable connector is special, so a special connector is required between the clock unit 1 and the SG. a-6) SG is useful for measuring the marginal margin frequency, but the output frequency is SVP4.
It is not possible to control from, and it is necessary for human beings to set, (a-7) Humans who set the output frequency of SG,
Can't do other work, (a-8) If a large number of devices perform the clock margin test at the same time, the same number of people as the number of the devices is required, (a-9).
After the human confirms that the numerical value of the output frequency displayed on the SG may be misread by a human and (a-10) the execution of the process of the processing unit 3 is completed, the SG output frequency is changed. That it is necessary to re-set, (a-11) that the human needs to instruct the SVP 4 to issue a command to start execution of the processing of the processing unit 3 after the human resets the SG output frequency. There are problems such as.

(B) In the apparatus shown in FIG. 3, (b-1) XFA
Since a place for mounting the ST and XSLOW oscillation circuits is required, the device becomes large in size. (B-2) X
When viewing FAST and XSLOW, it is necessary to provide a window in the device 5 or open the door of the housing,
(B-3) When the window or door of the device is opened, the environment of the device, especially the temperature changes. (B-4) When the XFAST and XSLOW are built into the device from the beginning, a clock unit (B-5) XFAST and X due to the decrease in reliability due to an increase in the number of parts of 1
When the SLOW is attached during the clock margin test and removed after the test, there are problems such as a mistake in replacing the connector connection of the clock unit 1 and a possibility of forgetting to recover. On the other hand, in FIG. 2, there is an advantage that the clock margin test can be performed in a state close to that of the product in which the device 5 operates with the normal clock.
In FIG. 3, there is an advantage that the margin clock can be switched by the control from the SVP 4. An object of the present invention is to solve these conventional problems and to use the apparatus in a state close to that of a product operating with a normal clock, with a small number of man-hours, and without increasing the size of the apparatus. Another object of the present invention is to provide a clock margin test device capable of performing a clock margin test at a location.

[0005]

To achieve the above object, a clock margin test apparatus according to the present invention comprises a clock unit for selecting a normal clock and a margin clock and supplying them to a processing unit, and each clock. In a clock margin test apparatus including a processing unit that executes processing in synchronization with the clock unit and a service processor that controls the processing unit, the discrete values are set in advance by the control of the service processor. A margin clock generating means for sequentially changing the frequency, duty, potential, or phase value of the margin clock is installed outside the equipment and connected to the equipment only during the clock margin test. The command to switch the margin clock from the bis-processor, the command to start the processing of the processing unit, and the end of the processing. By repeatedly issuing commands to, Ma - each frequency, each Du Jin clock - tee, is characterized in that testing the operational characteristics of the device in the potentials to the respective phases.

[0006]

In the present invention, the value of the frequency of the margin clock preset to have discrete values is set to the SVP.
It is possible to switch over sequentially by the control from, and the operation unit can be installed outside the device. The generator is placed outside the equipment in order to prevent the equipment from increasing in size and the number of parts for the clock margin test, and to ensure that the margin clock generator is recovered after the clock margin test. is there. In addition, it is portable and can be easily carried, and the margin clock generator, which is used only during clock margin tests, can be connected to the unit without making any changes other than opening and closing the housing door. .. This allows the margin clock generator to be connected to the device without changing the connector connection between the internal units, except for opening and closing the door of the device. Can be eliminated. In addition, the operating characteristics of the device at each frequency of the margin clock are determined by software by means of a command for switching the margin clock from the SVP 4, a command for starting the execution of the processing of the processing unit 3, and a command for ending the execution. The test can be automatically performed by repeatedly issuing the same number of types of margin clocks. As a result, human intervention in the clock margin test can be reduced, and the number of steps can be reduced. In addition, the marginal margin frequency can be measured via a margin clock generator.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a margin clock test apparatus showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a margin clock generator 6 is independently arranged outside the device 5. Margin clock generator 6
Is connected to the clock switching circuit 2 in the device 5 and is also connected to the SVP 4. Outside the margin clock generator 6, SG11 to SG1i are connected. The margin clock generator 6 is capable of sequentially switching the margin clock frequency, which has been set in advance to have discrete values, under the control of the SVP 4, and is easily portable in a portable size. Is possible and S
The signal from G can also be supplied to the device 5. Therefore, this generator 6 is used only during the clock margin test. XNORMA 11 is a clock sending unit for sending the margin clock and HIGH level signal, 8 is a power supply circuit unit for supplying internal components of the margin clock generator 6 and generating a HIGH level signal, and XNORMA 11 Oscillation circuit for generating a clock of the same frequency as the normal clock, XSLOW11 to 1k is an oscillation circuit for generating a clock of a frequency lower than the normal clock, XFAST
Reference numerals 11 to 1j are oscillator circuits for generating a clock having a frequency higher than the normal clock, SG11 to 1i are standard signal generators, and CON11 to 1i are connectors for connecting SGs. Here, SG1i, CON1i, XFAST1
j, i, j, and k of XSLOW1k represent the numbers of each of the margin clock generators 6, and are natural numbers. The test apparatus of this embodiment is the same as that of the conventional Japanese Patent Laid-Open No. 55-55-55.
As with the device described in Japanese Patent No. 33258,
A dynamic clock control system for simulating a state in which the clock suddenly changes by switching between the round clock and the margin clock is not used, but a static clock for testing the operating characteristics of the device 5 at each margin clock is not used. Use a clock control method. Further, the apparatus of this embodiment is the same as that of the conventional Japanese Patent Laid-Open No. 58-1.
No clock control method is used, such as the device described in Japanese Patent Publication No. 07930, in which a clock switching circuit that receives a clock switching signal notifies an oscillator that can generate a high-speed clock and a low-speed clock of generation and stop of the high-speed clock , SVP4 uses a clock control method in which the SVP4 directly reports the generation and stop of the margin clock to the oscillation circuit generating the margin clock.

FIGS. 4, 5 and 6 are connection diagrams showing first, second and third embodiments of the margin clock generator for switching and outputting the frequency and the device under test, respectively. In FIG. 4, the signal cable 13 and its connector 14 connect the device 5 and the margin clock generator 6. The margin clock generator 6 is XFAST.
11 and the clock output from XSLOW11, SV
AND, OR, NOT depending on the control signal 140 from P4
Select at the gate and select either
10 is output to the clock unit 1, and at the same time, HIG
The H level signal 130 is also output to the clock unit 1.
The clock switching circuit 2 uses the signal 131 which is at the high level when the margin clock generator 6 is connected to the device 5 and is at the low level when the margin clock generator 6 is not connected to the margin clock 110 and the normal clock. Clock 1
00, and the processing unit 3 receives the system clock 5
Supply 0. Further, the power supply of the margin clock generator 6 can be secured by connecting the power supply unit 9 for supplying power to each unit of the apparatus 5 and the power supply circuit section 8 with the power supply cable 10 and its connector 11. Power circuit section 8
In order to eliminate the influence of the fluctuation of the voltage of the power supply unit 9 in the above, the power supply circuit section 8 may be provided with a voltage stabilizing circuit or a fuse. V _H is a HIGH level voltage, V _L is a LOW level voltage, and R is a voltage resistance for preventing a short circuit between V _H and V _L. The CON 11 and the signal 120 are circuits used when increasing the types of margin clocks and measuring the margin margin frequency. As a result, the margin clock oscillator 6 and the clock switching circuit 2 can be composed of simple circuits.

In FIG. 5, the margin clock generator 6 is controlled by the control signal 140 from the SVP 4 to XFAST.
11 and XSLOW 11 power supply V _X is turned ON and OF by relay
After that, the margin clocks 110 and 111 are switched and output to the clock unit 1. The clock switching circuit 2 switches between the margin clocks 110, 111, 120 and the normal clock 100 using the control signals 140 and 141 from the SVP 4, and supplies the system clock 50 to the processing unit 3. As a result, mutual interference between the power supplies of XFAST11 and XSLOW11 in the margin clock generator 6 and clock crosstalk noise can be prevented, and power consumption can be reduced. The CON 11 and the signal 120 are used to increase the types of margin clocks and to measure the margin margin frequency. In FIG. 6, the margin clock generator 6 controls the control signals 140 and 1 from the SVP 4.
41 selects the clock from CON11, MCON12 and CON13 by AND, OR and NOT gate,
It is output to the clock unit 1 as the margin clock 110. The clock switching circuit 2 switches between the margin clock 110 and the normal clock 100 using the control signals 140 and 141 from the SVP 4, and supplies the system clock 50 to the processing unit 3. In FIG. 6, S
G11, 12, and 13 are connected to the margin clock generator 6 externally. As a result, the preset frequency of the margin clock 110 can be set to an arbitrary value that can be output by the SG. Further, by installing the margin clock generator external power supply device 12 having the same ground potential as the device 5 and supplying the margin clock generator 6 with power,
It is possible to eliminate the influence of the voltage fluctuation of the power supply unit 9 in the power supply circuit section 8.

FIG. 7, FIG. 8, FIG. 9 and FIG. 10 are diagrams showing examples of the construction of a margin clock generator for switching and outputting the duty, potential, phase and frequency of the clock. The margin clock generator 6 shown in FIG. 7 has a clock 10 that passes through a delay element 15 that delays a signal by a fixed time.
When ORing 2 and 103 and the clock 101 which has not passed, the relay is turned on and off by the control signal 140 to switch the number of the delay elements 15 through which the clock passes, whereby the margin of each duty is changed. The clock 110 is generated. In FIG. 11A, the original waveform (101) generated from the XNORM 11, the delayed waveforms (102, 103) that have passed through the delay element 15, and the OR of these waveforms.
The waveform (110) taken is shown. in this way,
Since the width becomes wider by taking the OR, the duty (width) can be changed. 7 and 8
Are drawn corresponding to the margin clock generator 6 of FIG. The margin clock generator 6 of FIG. 8 uses an attenuating element 16 for attenuating a signal by a constant voltage, and controls
The margin clock 110 of each potential is generated by turning on and off the relay by 40 and switching the number of the attenuation elements 16 through which the clock passes. Marker of FIG.
The gin clock generator 6 uses a delay element 15 that delays a signal for a fixed time, and switches the relay on and off by a control signal 140 to switch the number of delay elements 15 through which the clock passes, thereby controlling the phase of each phase. Generating a jin clock 110. In FIG. 11 (b), XNORM
Original waveform (11) generated from 11, and OR gate
The waveform (110) is shown. Thus, by passing through the delay element 15, the original waveform (11)
Since there is a time difference between and, a phase is formed.

The margin clock generator 6 of FIG.
The clock from FAST11 is passed through the counter to make the cycle an integral multiple, which is the frequency of the normal clock.
The margin clock 110 having a frequency close to 0 MHz is generated. The connector 14 of the signal cable 13 in the clock unit 1 is shown in FIGS. 4, 5, and 6, and the power supply unit 9 is shown in FIGS.
By using all the connectors 11 of the power cable 10 in Fig. 1 only during the clock margin test, no changes are made except when opening and closing the housing door when connecting the units of the device 5 with each other. In addition, a margin clock generator 6 can be connected to the device 5. Further, in the case of FIG. 6, since the oscillating circuit is not built in the margin clock generator 6, it is possible to make the size portable. However, in the case of incorporating the oscillating circuit, FIG. 4, FIG. 5, FIG. Even in
It is possible to make the margin clock generator 6 portable by using a small and power-saving crystal oscillator that generates a clock of a constant frequency as an oscillation circuit. In addition, by providing a display device indicating that the margin clock has been switched and a display device indicating that power is being supplied in the margin clock generator 6,
The operating state of the margin clock generator 6 can be easily known. The display device may be a miniature lamp, for example. Also, the signal cable 13 and its connector 1 used when connecting the margin clock generator 6 and the device 5 together.
4. If the power cable 10 and its connector 11 are the same as other cables and connectors used inside the apparatus, the cost of the margin clock generator 6 can be reduced. .. Furthermore, in the margin clock generator 6,
By providing a cover, the margin clock generator 6
The reliability can be improved by facilitating storage and protecting from dust.

[0012]

As described above, according to the present invention,
The device for the clock margin test can be miniaturized to avoid mistakes in replacement and forgetting to recover the oscillator circuit when it is attached and removed, and the clock margin test can be easily performed at the user's place of use. Become. In addition to the marginal clock of preset discrete frequency, duty, or potential, S
It is practical and extremely useful because it is possible to supply the device with a signal whose characteristics are continuously changed from G.

[0013]

[Brief description of drawings]

FIG. 1 is a block diagram of a clock margin test apparatus showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional clock margin test apparatus.

FIG. 3 is a block diagram showing another example of a conventional clock margin test apparatus.

4 is a first embodiment diagram showing the connection between the margin clock generator and the test device in FIG. 1. FIG.

FIG. 5 is a second embodiment diagram showing the connection between the margin clock generator and the test device.

FIG. 6 is a third embodiment diagram showing the connection between the margin clock generator and the test device.

FIG. 7 is a diagram of a first specific example of a margin clock generator for switching and outputting a duty.

FIG. 8 is a second specific example diagram of a margin clock generator for switching and outputting a potential.

FIG. 9 is a diagram showing a third specific example of the margin clock generator which outputs the phase in a phased manner.

FIG. 10 is a diagram of a fourth specific example of the margin clock generator for switching and outputting the frequency.

FIG. 11 is a time chart when the duty and the phase of the waveforms in FIGS. 7 and 9 are changed.

[Explanation of symbols]

1 clock unit 2 clock switching circuit 3 processing unit 4 service processor (SVP) 5 test device 6 margin clock generator 7 clock sending unit 8 power supply circuit unit 9 power supply unit 10 power supply cable 11 power supply cable Connector 12 Margin clock generator External power supply device 13 Signal cable 14 Signal cable connector 15 Delay element 16 Attenuation element XNORM Normal clock generation oscillator circuit XFAST Oscillation that generates a higher frequency clock than the normal clock Circuit XSLOW Oscillation circuit that generates lower frequency clock than normal clock SG Standard signal generator CON SG connector

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Seiichi Kawashima, No. 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., Kanagawa Plant, Hitate Manufacturing Co., Ltd. (72) Seiichi Obata, No. 1 Horiyamashita, Hadano, Kanagawa Factory Kanagawa factory

Claims (1)

[Claims] 1. A clock unit for selecting a normal clock or a margin clock and supplying it to a processing unit, a processing unit for executing processing in synchronization with each clock, and the clock unit and the processing unit. In a clock margin test apparatus equipped with a controlling service processor, the frequency, duty, potential, or phase of the margin clock whose discrete value is set in advance is controlled by the control of the service processor. A command for switching the margin clock from the service processor by installing a margin clock generating means for sequentially changing the value outside the equipment and connecting to the equipment only at a clock margin test.
By repeatedly issuing a command for starting the execution of the processing of the processing unit and a command for ending the execution of the processing, each frequency of the margin clock, each duty,
A clock margin test apparatus for testing the operating characteristics of the apparatus at each potential or each phase.