JPH05260577A - Reception circuit for station line terminating device - Google Patents

Abstract

PURPOSE:To eliminate transmission line jitter and the influence of jitter due to transfer by performing the detection of a frame synchronization pattern by a transmission line clock, writing the pattern on a clock transfer means at a detection timing, and providing a frame synchronization pattern detection circuit at the front stage of the clock transfer means. CONSTITUTION:The frame synchronization pattern can be detected by using a frame synchronization pattern detecting means 40 in accordance with a reception burst when it is inputted out of plural frame synchronization pattern detecting means 40 conformed to plural digital line terminating devices, and with the transmission clock of the means. In other words, when no pattern detection pulse is detected in a window by a W/R switching means, the write reset timing of a clock transfer circuit is switched to a pulse approximated to the pattern detection pulse. In such a way, the frame synchronization pattern can be detected by using the transmission line clock, which prevents the omission of a reception signal due to a frame synchronization error from occurring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit provided in an intra-station line terminating device of a time division directional control transmission system.

In a time division directional control transmission system (also called a ping-pong transmission system), one OCU (Office
Channel Unit: Multiple DSUs in intra-station line terminator
(Digital Service Unit) is connected in multiple ways, and each digital line terminating device DSU
The data sent from the intra-office line termination unit OCU to each other are asynchronous with each other. Therefore, the phase of the transmission path clock whose timing is extracted from the received signal in the intra-office line terminating device OCU changes every time data is received from each digital line terminating device DSU. Therefore, with this transmission path clock, the frame synchronization pattern position of the next frame cannot be accurately predicted. Therefore, there is a need for a method for achieving accurate frame synchronization using the internal clock.

[0003]

2. Description of the Related Art FIG. 3 shows a conventional example of a receiving circuit of an intra-office line terminating device OCU installed on the telephone office side in a time division directional control transmission system. In the figure, 31 is a clock transfer circuit for transferring a received signal (burst signal) from the digital line terminating device DSU side in the house from the transmission path clock (clock whose timing is extracted from the received signal) to the in-station clock, which is a bit buffer. Composed by. Reference numeral 32 denotes a frame synchronization pattern detection circuit that detects a frame synchronization pattern from the received signal after changing to the in-station clock by the clock transfer circuit 31, and 33, a synchronization protection circuit that performs synchronization protection based on the frame synchronization pattern detection result of the frame synchronization pattern detection circuit 32. , 34 are window generation circuits which decode the value of the frame counter by the internal clock to predict the arrival position of the frame synchronization pattern of the next frame and create a window at the predicted position.

In the example of FIG. 3, the number of the frame synchronization pattern detection circuits 32 is one, but in reality, it corresponds to a plurality of digital line termination units DSU connected to the intra-office line termination unit OCU. A plurality of synchronization protection circuits 33 and a plurality of window creation circuits 34 are provided corresponding to the frame synchronization pattern detection circuits 32.

In this receiving circuit, the received signal from the digital line terminating unit DSU side is first transferred to the clock transfer circuit 3
In step 1, the internal clock is switched to the internal clock, and the frame synchronous pattern detection circuit 32 detects a frame synchronous pattern for the received signal after the internal clock is switched to perform frame synchronization.

[0006]

As described above, in the receiving circuit of the conventional intra-station line terminating device OCU, after changing the received signal to the in-station clock by the clock changing circuit 31, the frame synchronization pattern detecting circuit detects the changed signal. The frame synchronization pattern is detected from the received signal.

With such a configuration, the transmission line jitter is not absorbed in the received signal after the transfer to the in-station clock using the bit buffer, and the jitter at the time of the clock transfer in the clock transfer circuit 31 is also included. It will be. Therefore, the position after changing to the in-station clock (that is, the reading side of the clock changing circuit 31)
The position of the frame synchronization pattern seen in (1) is not constant for each frame because there is the above-mentioned transmission line jitter + jitter at the time of clock transfer. Further, since the frame synchronization pattern is detected by the in-station clock, there is jitter when changing the clock with respect to the frame synchronization pattern position predicted by the in-station clock. Therefore, it is impossible to accurately predict and detect the position of the frame synchronization pattern of the received signal.

In order to reduce the influence of jitter at the time of clock transfer, the clock transfer circuit 31 may be constructed by a FIFO memory. However, in the conventional circuit, the frequency of the received clock is not stable, so the clock transfer circuit 31 is not stable. Since the write reset signal WR that determines the write start timing of the received burst to the clock cannot be created, the bit buffer has been used continuously in the clock transfer circuit 31 in the related art. Therefore, the influence of the jitter at the time of clock transfer can be reduced. I couldn't lose it.

The present invention has been made in view of the above circumstances, and an object of the present invention is to achieve reception in a receiving circuit of an intra-site line terminating device without being affected by transmission line jitter or jitter during clock transfer. It is intended to enable accurate detection of a frame synchronization pattern of a signal and clock transfer without data loss.

[0010]

FIG. 1 is an explanatory view of the principle of the present invention. As a first form, the receiving circuit of the intra-station line terminating device of the present invention is the receiving circuit of the intra-station line terminating device in a time division directional control transmission system in which a plurality of digital line terminating devices are multiple-connected to the intra-station line terminating device, A plurality of frame synchronization pattern detecting means 40 provided corresponding to a plurality of digital line terminators, each of which uses a transmission line clock whose timing is extracted from the received burst to obtain a frame synchronization pattern of a received burst from the corresponding digital line terminator. And a synchronization protection means 41 for performing frame synchronization protection on the detection result of the frame synchronization pattern detection means 40.

As a second form of the receiving circuit of the intra-station line terminating device of the present invention, in the above-mentioned receiving circuit, the clock changing means 4 for changing the reception burst from the digital line terminating device from the transmission line clock to the intra-station clock.
2 is provided, and the writing start timing of the reception burst to the clock transfer means 42 is generated based on the frame synchronization pattern detection timing in the frame synchronization pattern detection means 40.

As a third form of the receiving circuit of the intra-station line terminating device of the present invention, in the receiving circuit of the above-mentioned first or second form, the arrival position of the frame synchronization pattern of the next frame based on the synchronization information. Gating so as to output a pattern detection signal when the pattern is detected by the frame synchronization pattern detection means 40 in the window generated by the window generation means 43 and the window generation means 43. And a gate means 44.

As a fourth form of the receiving circuit of the intra-station line terminating device of the present invention, in the receiving circuit of the above-mentioned second or third form, the reception burst from the clock transfer means is based on the synchronization information. It is characterized by further comprising a read start timing generating means 45 for generating a read start timing.

Further, the receiving circuit of the intra-station line terminating device of the present invention, as a fifth form, is the above-mentioned second, third or fourth.
In the receiving circuit of this embodiment, the write start timing generating means for generating the write start timing of the received burst to the clock transfer means 42 based on the synchronization information, the pattern detection signal from the frame synchronization pattern detecting means 40 and the write start timing generation. Selecting means for selecting one of the write start timing signals from the means,
When the frame synchronization pattern detection means 40 detects the frame synchronization pattern, the pattern detection signal is selected, and when the detection fails, the write start timing signal is selected by the selection means to be the write start timing of the clock transfer means 42. To do.

The receiving circuit of the intra-station line terminating device of the present invention is, as a sixth form, the above-mentioned second, third or fourth.
In the receiving circuit of this form, the frame synchronization pattern detecting means 40 has a function of detecting a pattern similar to the frame synchronization pattern, and the frame synchronization pattern detecting means 4
A selection means for selecting one of the pattern detection signal from 0 and the approximate pattern detection signal is provided, and when the frame synchronization pattern is detected by the frame synchronization pattern detection means 40, the pattern detection signal is detected, and when the detection fails, the approximate pattern is detected. It is characterized in that the detection signal is selected by the selection means and used as the write start timing of the clock transfer means 42.

[0016]

In the receiving circuit of the first embodiment, when a receiving burst is input, the frame synchronizing pattern corresponding to the receiving burst among the plurality of frame synchronizing pattern detecting means 40 provided corresponding to the plurality of digital line terminators. The pattern detection means detects the frame synchronization pattern using the transmission path clock. Therefore, since the transmission line clock is used to detect the frame synchronization pattern, it is not affected by the transmission line jitter or the jitter at the time of clock transfer.

In the receiving circuit of the second embodiment, the writing start timing of the reception burst to the clock transfer means 42 is generated by the frame synchronization pattern detection timing of the frame synchronization pattern detection means 40. As a result, the reception burst can be written in the clock transfer means 42 without being affected by the transmission line jitter.

In the receiving circuit of the third embodiment, the window generation means 43 generates a window and the gate means 44 outputs the pattern detection signal only when the frame synchronization pattern is detected in the window, whereby the frame synchronization is performed. Prevent erroneous pattern detection.

In the receiving circuit of the fourth aspect, the read start timing generating means generates the read start timing,
Read the received burst from the clock transfer means 42,
The received burst is transferred from the transmission line clock to the in-station clock.

In the receiving circuit of the fifth embodiment, when the frame synchronization pattern detecting means 40 fails to detect the frame synchronization pattern, the selecting means replaces the pattern detection signal from the frame synchronization pattern detecting means 40 with the write start timing. The write start timing signal from the generating means is selected as the write start timing of the reception burst to the clock transfer means 42. As a result, it is possible to prevent the reception burst from being lost even if a frame synchronization pattern error occurs.

In the receiving circuit of the sixth embodiment, when the frame synchronization pattern detecting means 40 fails to detect the frame synchronization pattern, the selecting means selects the approximate pattern detection signal instead of the pattern detection signal, and the clock changing means. This is the start timing of writing the reception burst to 42. As a result, it is possible to prevent the reception burst from being lost even if a frame synchronization pattern error occurs.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a receiving circuit of the intra-station line terminating device as one embodiment of the present invention. 2, ₁ 1 to 1 ₄
Is a frame synchronization pattern detecting circuit for detecting a frame synchronization pattern from the received signal (received burst), the frame synchronization pattern detecting circuit 1 ₁ to 1 _4, station line terminal a plurality of line termination device DSU connected to OCU
(4 in this example) are provided corresponding to each of. Each frame synchronization pattern detection circuit 1 ₁ to 1
₄ is configured to detect the frame synchronization pattern only for the received bursts from the line terminating device DSU corresponding to each of them based on the identification number (ID) information in the received bursts.

The frame sync pattern detector 10 _n outputs a pattern detection pulse when it detects a perfect frame sync pattern (a pattern without a 1-bit error), and also detects a pattern close to the frame sync pattern. It is configured to output an approximate pattern detection pulse at any time. This pattern detection pulse is a window signal WDn (where n = 1, 2, 3, or 4:
The same applies hereinafter)) AND gate 11 _n
To become the pattern detection pulse DETn. Further, the approximate pattern detection pulse becomes an approximate pattern detection pulse WRn ′ by passing through the AND gate 12 _n gated with the window signal WDn.

Frame sync pattern detection circuits 1 ₁ to 1 ₄
Each of the pattern detection pulses DET1 to DET4 from is input to the 1-side input terminal of the selector 15 via the OR gate 13 and the phase adjusting circuit 8, and further to the write reset input terminal of the clock transfer circuit 4 via this selector 13. Is entered.

The clock transfer circuit 4 is a circuit for transferring the received burst from the transmission path clock to the in-station clock. The clock transfer circuit 4 is composed of a FIFO memory. When the write reset signal WR is input, writing of the reception burst is started at that timing, and when the read reset signal RR is input, the reception burst accumulated is read at that timing. To start.

[0026] 20 ₁ 20 ₄ a control circuit, are provided four in each frame synchronization pattern detecting circuit ₁ 1 to 1 ₄ correspond. The control circuit 20 _n includes a synchronization protection circuit 2 _n and AN.
D gate 17 _n , frame counter 9 _n , window creation circuit 3 _n , RR creation circuit 5 _n , WR creation circuit 6 _n , O
The R gate 18 _{n and the} like are included.

Here, the synchronization protection circuit 2 _n receives the pattern detection pulse DETn from the corresponding frame synchronization pattern detection circuit 1 _n to perform synchronization protection and outputs a hunting signal HUNTn during hunting. The AND gate 17 _n takes the logical product of the pattern detection pulse DETn and the hunting signal HUNTn. Frame counter 9 _n
Is the pattern detection pulse D that has passed through the AND gate 17 _n
Using ETn as a load timing (that is, a reset timing), the frame cycle of the reception burst is counted by the internal clock.

The window creating circuit 3 _n decodes the value of the frame counter 9 _n , predicts the arrival position of the frame synchronization pattern of the next frame, and creates a window at the predicted position. This window is the OR gate 18 _n
Hunting signal HUN from synchronization protection circuit 2 _n
The logical sum of Tn and Tn is output as the window WDn. Therefore, the window WDn corresponds to the synchronization protection circuit 2 _n.
During hunting, it will be for the entire period. The window WDn is input to the AND gates 11 _n and 12 _n of the frame synchronization pattern detection circuit 1 _n corresponding thereto, and also to the corresponding WR switching circuit 7 _n .

The RR creation circuit 5 _n is a frame counter 9 _n
Value is decoded and the read reset signal RRn of the clock transfer circuit 4 is generated at an appropriate timing. Each RR
Read reset signals RR1 from the creation circuits 5 _{1 to} 5 ₄
RR4 is a clock transfer circuit 4 via the OR gate 16.
It is input to the read reset input terminal of.

The WR creating circuit 6 _n is a frame counter 9 _n
Value is decoded and the write reset signal WRn of the clock transfer circuit 4 is created at an appropriate timing. This write reset signal WRn corresponds to the corresponding WR switching circuit 7 _n.
Entered in.

The OR gate 14 is the WR forming circuit 5 _1-5
Write reset signals WR1 to WR4 from ₄ are input, or frame synchronization pattern detection circuits ₁₁ to 1
The approximate pattern detection pulses WR1 ′ to WR4 ′ from ₄ are input, and the output signal thereof is input to the 0 side input terminal of the selector 15.

The WR switching circuit 7 _{1-7 4} frame synchronization pattern detecting circuit ₁ 1 to 1 ₄ and the control circuit 20 21 _to
It is provided corresponding to 0 ₄ . The pattern detection pulse DETn from the corresponding frame synchronization pattern detection circuit 1 _n and the window WDn from the control circuit 20 _n are input to the WR switching circuit 7 _n , and it is detected whether or not the pattern detection pulse DETn is present in the window WDn. If the pattern detection pulse DETn is not detected within the window WDn, the switching signal SEL is supplied to the control input terminal of the selector 15 via the OR gate 19.

The operation of the circuit of this embodiment will be described below.
If the received burst is input, each frame synchronization pattern detecting circuit 1 ₁ to 1 ₄ operates contrary, the frame synchronization pattern detecting circuit 1 _n frame corresponding to the digital line termination device having issued the received burst The sync pattern is detected and the pattern detection pulse DETn is output.
This pattern detection pulse DETn is given as a write reset signal WR to the clock transfer circuit 4 via the OR circuit 13, the phase adjustment circuit 8 and the selector 15, and at that timing, the received burst is transferred to the clock transfer circuit via the phase adjustment circuit 8. Writing to the circuit 4 is started.

This pattern detection pulse DETn is input to the corresponding synchronization protection circuit 2 _n for synchronization protection, and during hunting, the synchronization protection circuit 2 _n outputs a hunting signal HUNTn. During this hunting, the frame counter 9 _n is reset every time the pattern detection pulse DETn is output and counts the frame period by the internal clock.

The window creation circuit 3 decodes the value of the frame counter 9 _n and creates a window WDn for the frame sync pattern predicted position of the next frame. As described above, all windows are used during hunting. This window WDn opens the AND gates 11 _n and 12 _n , and the pattern detection signal DETn and the approximate pattern detection signal WRn ′ can be output. Further, the WR switching circuit 7 _n generates a switching signal SEL and switches the selector 15 to the 0 side input when the pattern detection signal DETn is not detected in this window.

The RR creating circuit 5 _n decodes the value of the frame counter 9 _n and outputs the read reset signal RR of the clock transfer circuit 4 at an appropriate timing. Therefore, the clock transfer circuit 4 starts writing the reception burst at the timing of the pattern detection pulse DETn, and at the timing of the read reset signal RR, starts reading the reception burst written using the in-station clock.
As a result, the received burst is switched from the transmission line clock to the in-station clock.

With such a configuration, it becomes possible to carry out clock transfer without being affected by the transmission line jitter, and it is possible to detect a frame synchronization pattern which is not affected by jitter due to the clock transferring.

The WR creating circuit 6 _n decodes the value of the frame counter 9 _n and creates a write reset signal WRn for the clock transfer circuit 4 at an appropriate timing. This write reset signal WRn is not normally used,
When the pattern detection pulse DETn is not detected in the window WDn by the WR switching circuit 7 _n , the selector 15 is switched to select the write reset signal WRn side to detect the write reset timing of the clock transfer circuit 4 for pattern detection. The pulse DETn is switched to the write reset signal WRn, which causes the frame synchronization pattern detection circuit 1 _n to detect the pattern detection pulse DETn.
Even when is not output, the received burst can be written in the clock transfer circuit 4. This makes it possible to prevent the reception burst from being lost due to an error in the frame synchronization pattern.

The write reset timing of the clock transfer circuit 4 when the frame sync pattern cannot be detected is not limited to the write reset signal WRn created by the WR creation circuit 5 _n described above, but a frame sync pattern detection circuit. It is also possible to use the approximate pattern detection pulse WRn ′ generated at 1 _n .

That is, when the frame synchronization pattern is not in a perfect form due to a bit error or the like, the pattern detection pulse DETn is not generated, but the frame synchronization pattern in which the bit error has occurred becomes a pattern close to the frame synchronization pattern. , The approximate pattern detection pulse WRn ′ may be generated. Therefore, when the pattern detection pulse DETn is not detected in the window WDn by the WR switching circuit 7 _n , the write reset timing of the clock transfer circuit 4 is switched from the pattern detection pulse DETn to the approximate pattern detection pulse WRn ′. As a result, it is possible to prevent the reception signal from being lost due to a frame synchronization pattern error.

Various modifications are possible in carrying out the present invention. For example, in the above embodiment, _four control circuits 20 _{1 to} 20 ₄ including a synchronization protection circuit and the like are provided corresponding to each pattern detection pulse DET1 to DET4, but the present invention is not limited to this. The control circuit for each pattern detection pulse DET1 to DET1
It can also be commonly used for DET4. In that case, control information for each pattern detection pulse is stored in the memory, and the detected pattern detection pulse DET is detected.
Only for n, the control information is set in the control circuit to perform the synchronous control.

[0042]

As described above, according to the present invention, in the receiving circuit of the intra-station line termination device, the frame synchronization pattern is detected by the transmission line clock and written in the clock transfer means at the detection timing. It is possible to change clocks without being affected by transmission line jitter. Further, since the frame synchronization pattern detection circuit is provided in the preceding stage of the clock transfer circuit, it is possible to detect the frame synchronization pattern which is not affected by the jitter due to the clock transfer.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a receiving circuit of the intra-station line terminating device as one embodiment of the present invention.

FIG. 3 is a block diagram showing a receiving circuit of a conventional intra-station line termination device.

[Explanation of symbols]

 1 frame synchronization pattern detection circuit 2 synchronization protection circuit 3 window creation circuit 4 clock transfer circuit 5 RR creation circuit 6 WR creation circuit 7 WR switching circuit 8 phase adjustment circuit 10 frame synchronization pattern detection unit 11, 12, 17 AND gate 13, 14 , 18, 19 OR gate 15 Selector

Claims (6)

[Claims] 1. In a receiving circuit of an intra-station line terminating device in a time division directional control transmission system in which a plurality of digital line terminating devices are multiple-connected to the intra-station line terminating device, a plurality of circuits provided corresponding to the plurality of digital line terminating devices are provided. A frame synchronization pattern detecting means (40) for detecting the frame synchronization pattern of the reception burst from the corresponding digital line terminating device by using the transmission path clocks, the timings of which are extracted from the reception burst; A receiving circuit for an intra-station line terminating device, comprising: a synchronization protection means (41) for performing frame synchronization protection on the detection result of the detection means. 2. A clock transfer means (42) for transferring a received burst from the digital line terminating device from the transmission path clock to an in-station clock, and based on a frame synchronization pattern detection timing in the frame synchronization pattern detection means. The receiving circuit of the intra-station line terminating device according to claim 1, wherein the receiving circuit is configured to generate a write burst start timing to the clock transfer means. 3. A window generation means (43) for predicting the arrival position of the frame synchronization pattern of the next frame based on the synchronization information and generating a window at that position, and the window generation means (43) in the window generated by the window creation means. Gate means (44) for gating so as to output a pattern detection signal when a pattern is detected by the frame synchronization pattern detection means.
The receiving circuit of the line terminating device described in the station. 4. The reception of an intra-station line terminating device according to claim 2 or 3, further comprising a read start timing generation means (45) for generating a read start timing of a reception burst from the clock transfer means based on synchronization information. circuit. 5. A write start timing generation means for generating a write start timing of a reception burst to the clock transfer means based on synchronization information, a pattern detection signal from the frame synchronization pattern detection means and the write start timing generation means. Selection means for selecting one of the write start timing signals from the above, and when the frame sync pattern is detected by the frame sync pattern detection means, the pattern detection signal is output, and when the detection fails, the write start timing signal is output. The receiving circuit of the intra-station line terminating device according to any one of claims 2 to 4, wherein the receiving circuit is configured to be selected by the selecting means and set as a write start timing of the clock transferring means. 6. The frame synchronization pattern detecting means has a function of detecting a pattern similar to the frame synchronization pattern, and selects one of a pattern detection signal from the frame synchronization pattern detecting means and the approximate pattern detection signal. Selecting means for selecting the pattern detection signal when the frame synchronization pattern is detected by the frame synchronization pattern detecting means, and selecting the approximate pattern detection signal by the selecting means when the frame synchronization pattern is detected, and writing the clock transfer means. The receiving circuit of the intra-station line terminating device according to any one of claims 2 to 4, which is configured to have a start timing.