JPH05260380A - Title movement circuit - Google Patents

Abstract

PURPOSE:To move a position of a title for a movie software or the like and to display the title while its size is being compressed with respect to the title moving circuit used mainly for a picture reproduction device provided with a display device whose aspect ratio is 16:9. CONSTITUTION:A WE signal is obtained by a write control section (comprising blocks 21-27) in a memory controller and an RE signal is obtained by a read control section (comprising a block 24 and blocks 28-34). The WE signal gives a write enable to an FiFo memory at an interval of one title signal data within one horizontal scanning line (one line) in the portion (lines c-d) in which the title signal is in existence. The RE signal gives a read enable to the FiFo memory consecutively for a half of one horizontal period for horizontal scanning periods (lines a-b) different from the horizontal scanning period for write enable. Thus, a title signal output from the FiFo memory is compressed to 1/2 with respect to the input.

Description

Detailed Description of the Invention

[0001]

The present invention has an aspect ratio of 16: 9.
The present invention relates to a caption moving circuit mainly used in an image reproducing device having a display. And this invention especially aims at providing the subtitle moving circuit which can move the position of subtitles, such as a movie software, and can compress and display the size of the subtitle.

[0002]

2. Description of the Related Art A TV receiver (hereinafter also referred to as a wide TV) equipped with a display having an aspect ratio of 16: 9, which has recently been introduced, is provided with a video signal of a Vista size or a cinema mode (an aspect ratio of 4: 3). When only the video area of the (signal for screen) is displayed on the full screen, if subtitles exist outside the video area (for example, if subtitles are inserted in the black band portion on the screen with an aspect ratio of 4: 3), The subtitle is 16:
It goes out of the screen of 9 and is not displayed. Therefore, a caption moving circuit that moves a caption signal existing outside the video area into the video area and displays the caption on the screen is required. The basic operation and purpose of the subtitle moving circuit are as shown in Japanese Patent Application No. 3-99365 and Japanese Patent Application No. 4-28988 by the present applicant, and the basic configuration will be briefly described here.

FIG. 4 shows the basic structure of a caption moving circuit. A video signal that enters the input terminal 1 and includes a caption signal outside the video area is converted into a digital video signal by the A / D converter 2 and supplied to the memory 3. The memory controller 4 writes and controls the memory 3 at the timing when the caption signal is present, and the caption signal is written in the memory 3. The written caption signal has a different timing (that is,
It is read from the memory 3 by the memory controller 4 at a timing within the video area). The read caption signal is
A character area signal obtained by the character detection circuit 5 is mixed with a digital video signal by a mixer (composed of a multiplexer) 6. This digital video signal is D / A
It is converted into an analog video signal by the converter 7 and sent to the output terminal 8. When the signal obtained from the output terminal 8 is reproduced on the display, an image in which the caption is superimposed on the video portion and the caption is not missing can be obtained. The vertical movement position of the subtitles is determined by the read timing from the memory 3. Here, the caption signal is generally 4b in order to maintain character quality.
It is necessary to have at least it, but the character area signal may be 1 bit.

Next, the control of the memory 3 will be described.
FIG. 5 shows a state in which subtitles existing outside the video area are moved into the video area and displayed on the screen (wide TV.
Then, only the image area of the figure is displayed in full screen). Write (write) start is performed at point c (c line) of each field, and write stop is performed at point d (d) of each field.
Line). In addition, read (read) start is performed at point a (a line) of each field, and read stop is performed at point b (b line) of each field. At point a,
The read address is reset (RRST), and the write address is reset (WRST) at point c. The read is continuously enabled between the points a and b (for example, the read enable signal RE (read enable signal) is continuously activated). Further, between the points c and d, writing is continuously enabled (for example, the write enable signal WE (write enable signal) is continuously activated).

When the memory 3 is controlled by the memory controller 4 as described above, the caption signal written in the nth field is read out in the a-line to the b-line of the next (n + 1) th field, as shown in FIG. You can move subtitles like this.

Here, the memory 3 is Fast in Fast out
Dual port memory (hereinafter referred to as FiFo memory)
However, it is easier to use than the addressable memory. this is,
The FiFo memory has a WE (write enable) signal, R
While the above memory control can be performed only by controlling the E (read enable) signal, the WRST (write reset) signal, and the RRST (read reset) signal, the addressable memory has external write control and external read control. This is because it is necessary to continuously increment (increase) the address and control is complicated. FIG. 6 shows a terminal group of the FiFo memory.
The FiFo memory has clock, reset, and enable terminals for both read and write, and the same clock is supplied as the write clock (WCK) and the read clock (RCK).

FIG. 7 shows a waveform of a signal supplied from the memory controller 4 to each terminal of the FiFo memory shown in FIG. The WRST signal is generated on the start line in the period in which the caption signal of each field is present, and the WE signal is High throughout the line period in which the caption signal is present, and is Low in other cases. The RRST signal is generated in the line of each field for displaying the caption signal,
The high period of the E signal is the same as the high period of the WE signal. WE signal, RE signal, WRST signal, R
The control of the RST signal is performed by the line counter in the memory controller 4. By this control, FiF
At the output of the o memory, the caption signal written in the nth field is read at the timing of the next (n + 1) th field, and the caption is displayed on the screen.

As shown in FIG. 7, the control of the conventional FiFo memory is performed by a pulse signal of the same shape for both reading and writing, and simply by relatively delaying the timing of reading and writing within the field. The size of the moved subtitles is exactly the same as before moving. In this case, as a result of moving the subtitles into the video area, the video portion hidden by the subtitles is large, and the video signal information is greatly lost. In addition, subtitles may be displayed simultaneously inside and outside the video area on the original screen with an aspect ratio of 4: 3. In this case, when the video signal in the video area is displayed on the full screen of the wide TV with the aspect ratio of 16: 9 and the subtitle outside the video area is moved into the screen, the subtitle does not move in the horizontal direction. There is also a problem that the subtitles may overlap the subtitles in the video area, making the subtitles difficult to read.

[0009]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to compress and move subtitles and adjust the moving position so that the video signal is not damaged and the subtitles are difficult to read. What means should be taken to make a subtitle moving circuit that can move subtitles without having to do so.

[0010]

In order to solve the above problems, the present invention provides a video signal including a caption signal, controls a memory by a memory controller,
In a caption moving circuit that moves a display position of a caption signal in a vertical direction, a Fast in Fast out dual port memory (FiFo memory) is used for the memory, and one horizontal line is provided in the memory controller where the caption signal exists. In the horizontal scanning period different from the horizontal scanning period in which the writing permission is given, and the writing control unit for giving the writing permission of the caption signal to the FiFo memory at predetermined intervals within the scanning period, a predetermined fraction of one horizontal scanning period. And a read control unit for giving read permission to the FiFo memory continuously for the period of.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In general, a FiFo memory has a dual port structure having clock, reset and enable terminals independently for reading and writing, as shown in FIG. The address of the FiFo memory is automatically incremented by the clock and stopped by the enable signal. Therefore, data can be compressed by changing the enable signal relatively on the write side and the read side, and the size of the subtitles in the horizontal and vertical directions can be compressed. The subtitle moving circuit of the present invention has the same basic configuration as the conventional one shown in FIG.
A FiFo memory is used for the above, and the data compression control as described above is performed by the memory controller.

FIG. 1A shows the waveforms of the RE signal and the WE signal of the first embodiment for horizontally compressing the subtitles to 1/2, and FIG. 1 is a block diagram of the memory controller of the first embodiment. It shows in (b).

The WE signal shown in FIG. 1 (a) changes at a cycle twice as long as that of WCK (see FIG. 3 (a)), whereby the subtitle signal of one horizontal scanning period (1H) is changed in the writing stage. 1/2 is thinned out. (In the portion where the caption signal exists (c line to d line described later), the WE signal gives write permission to the FiFo memory every other data of the caption signal within one horizontal scanning period (1 line).) (A)
In the RE signal shown in, the frequency matches the horizontal scanning frequency,
The duty ratio is a pulse of 50%, and the thinned input data is continuously read from the FiFo memory in the period of (1/2) H. (In a horizontal scanning period (a line to b line described later) different from the horizontal scanning period (c line to d line) to which the writing permission is given, the RE signal is continuously ½ of one horizontal scanning period). Then, the read permission is given to the FiFo memory.)

As a result, the caption signal written in the nth field is read out in the next (n + 1) th field,
The caption signal output from the FiFo memory is 1 for the input.
The waveform is compressed to / 2. By adjusting the interval for giving write permission by the WE signal (the cycle of the WE signal) and the read permission period by the RE signal (duty ratio of the RE signal), horizontal compression can be performed at various magnifications.

FIG. 2 shows the RE signal and the WE signal of the second embodiment in which this principle is applied to 1/2 compression in the vertical direction.
Here, it is assumed that there is a caption signal in the 12H period outside the video area. The WE signal becomes High every 1H, and the caption signal is thinned out to 1/2 in the vertical direction. (In the portion where the subtitle signal exists (12H period outside the video area),
The WE signal gives the FiFo memory permission to write the subtitle signal every other horizontal scanning period. ) The RE signal is the total number of horizontal scanning periods when the WE signal becomes High (in this case, 6).
H), continuously becomes High, and the thinned caption signals are read from the FiFo memory. (In the horizontal scanning period different from the horizontal scanning period to which the writing permission is given, the RE signal indicates the reading permission to the same horizontal scanning period number (6H) as the number of horizontal scanning periods (6H) to which the writing permission is given. It is applied to the FiFo memory. In the illustrated case, it is applied continuously for 6H periods.) Thereby,
The subtitle signal written in the field is the next (n + 1) th
The subtitle signal output read from the field and output from the FiFo memory is compressed to 1/2 of the input.
By adjusting the interval for giving the write permission by the WE signal and the read permission period by the RE signal, the compression in the vertical direction can be performed at various magnifications.

Next, the block diagram of the memory controller of the first embodiment shown in FIG. 1B will be described with reference to the timing chart of FIG. Here, it is assumed that the original position of the subtitle to be moved is between the c line and the d line, and the destination is between the a line and the b line. The number of lines is the same as the number of lines from line a to line b). In addition, the frequency fs of the basic clock CK that is the read clock (RCK) and the write clock (WCK) is
910 times the horizontal scanning frequency fH, that is, fs = 910
fH

First, the light side will be described. The write line start counter 21 has a vertical synchronization signal (VD).
As input, and horizontal synchronization signal (HD) as clock,
The count value is determined by the data value given from the write line start value setting circuit 22 (in this case,
The start line is set to c line). The output of the write line start counter 21 becomes the WRST signal. The output of the write line start counter 21 is supplied to the write line width set counter 23, and the write line width set counter 23 receives the subtitle line width setting circuit 24.
The data value from determines which line to which signal to write to memory (in this case,
The writing line width is determined from c line to d line). From the write line width set counter 23, FIG.
The WE1 signal shown in (b) is output, and the WE1 signal is NA.
It is supplied to one terminal of the ND circuit 25. At the other terminal of the NAND circuit 25, the frequency of the clock CK is halved in the block 26 and WE2 obtained through the switch 27.
A signal (see FIG. 3A) is supplied.

The NAND circuit 25 has a WE1 signal and a WE2 signal.
A WE signal is generated from the signal and the WE signal is supplied to the FiFo memory. With this WE signal, when viewed in the vertical cycle, the caption signal from the c line to the d line is
It is thinned to 1/2 and written. When viewed in the horizontal cycle, as described with reference to FIG. 1A, the WE signal permits the writing permission of the WE signal every other data for the caption data of one line.
o Give to memory. The blocks 21 to 27 shown in FIG. 1B constitute a write controller.

Next, the lead side will be described. The read line start counter 28 uses a vertical sync signal (VD).
As input, and horizontal synchronization signal (HD) as clock,
The count value is determined by the data value given from the read line start value setting circuit 29 (in this case,
The start line is determined to be line a). The output of the read line start counter 28 becomes the RRST signal. The output of the read line start counter 28 is supplied to the read line width set counter 30, and the read line width set counter 30 outputs the subtitle line width setting circuit 24.
The data value from determines which line to which line the caption signal is displayed (in this case,
The read line width (that is, the vertical movement destination) is determined from the a line to the b line). The RE1 signal shown in FIG. 3B is output from the read line width set counter 30, and the RE1 signal is supplied to one terminal of the NAND circuit 31. The 1 / 2H pulse generation counter 32 is
The (horizontal synchronizing signal) is input and the clock CK is used as a clock to output the RE2 signal (see FIG. 3A) having a pulse width of 1/2 cycle of 1H. The RE2 signal is applied to the delay circuit 3
3, and is supplied to the other terminal of the NAND circuit 31 via the switch 34.

The NAND circuit 31 has the RE1 signal and the RE2 signal.
The RE signal is generated from the signal and the RE signal is supplied to the memory. With this RE signal, when viewed in the vertical cycle,
The caption signal, which has been thinned and written in half, is read from the memory and displayed between the a line and the b line. When viewed in the horizontal cycle, as described with reference to FIG. 1A, the data is continuously read from the memory for each line for a period of (1/2) H. The destination of the subtitles is
It can be adjusted by the value of the start line set by the read line start value setting circuit 29. In the horizontal direction, the delay circuit 33
Can be adjusted by changing the phase of the RE2 signal. The block 24 and the blocks 28 to 34 shown in FIG. 1B constitute a read control unit.

The switches 27 and 34 are switches for displaying subtitles reduced to 1/2 size or subtitles of the original size, and are switched according to a horizontal size control signal. ..

As described above, in the first embodiment, since the subtitle can be reduced to 1/2 in the horizontal direction and displayed, even if the subtitle is moved within the video area, the video signal is not damaged as compared with the conventional case. Further, in the first embodiment, the moving position can be arbitrarily set in the horizontal direction and the vertical direction, so that the caption can be moved to a position that is easy to read.

The memory controller of the second embodiment which can be vertically compressed to 1/2 can be constructed so as to generate the RE signal and the WE signal by the timing shown in FIG. 2 based on the first embodiment. .. In the second embodiment, the horizontal movement position cannot be adjusted, but the vertical movement position can be adjusted arbitrarily.

A memory controller capable of horizontal compression and horizontal / vertical movement of subtitles as shown in the first embodiment, and vertical compression of subtitles as shown in the second embodiment. And a memory controller capable of moving vertically, the compressed size of subtitles can be adjusted independently in the horizontal and vertical directions, and the moving position can be set independently in the horizontal and vertical directions. It may be a caption moving circuit.

For example, in the WE signal shown in FIG. 2, the write permission is continuously given for every one horizontal scanning period, but the continuous write permission is given to the WE signal shown in FIG. As described above, every other data is written.
(Write permission given to the FiFo memory every other horizontal scanning period (write permission by the WE signal shown in FIG. 2) is given in FIG.
The write permission is generated every other data, like the write permission by the WE signal shown in (a). Further, the RE signal shown in FIG. 2 continuously gives read permission for the number of horizontal scanning periods (6H) for which write permission has been given by the WE signal. Figure 1
The RE signal shown in FIG. (Read permission (read permission by the RE signal shown in FIG. 2) given to the FiFo memory for the same number of horizontal scanning periods (6H) as the number of horizontal scanning periods for which the writing permission is given is given for each horizontal scanning period. In this case, read permission is generated consecutively during a half of one horizontal scanning period (read permission by the RE signal shown in FIG. 1A).
2. The subtitle moving circuit can compress the subtitle size to 1/2 in the vertical direction and can arbitrarily set the moving position independently in the horizontal direction and the vertical direction.

A wide TV having an aspect ratio of 16: 9 using the subtitle moving circuit of the present invention in place of the conventional subtitle moving circuit will of course have an aspect ratio of 4: 3 as in the conventional case.
The video signal for the video can be expanded and displayed as a screen with an aspect ratio of 16: 9.

[0027]

As described above, since the caption moving circuit according to the present invention can compress the display size of the caption, even if the caption is moved within the video area, the video signal is hardly damaged. Furthermore, since the moving position of this subtitle moving circuit can be adjusted, the subtitle can be moved to a position that is easy to read. To describe the effect for each claim, the caption moving circuit of claim 1 can adjust the compressed size of the caption in the horizontal direction, and can set the moving position of the caption independently in the horizontal direction and the vertical direction. The subtitle moving circuit according to the second aspect can adjust the compressed size of the subtitle in the vertical direction and can arbitrarily set the moving position of the subtitle in the vertical direction. In the subtitle moving circuit according to the third aspect, the compressed size of the subtitle can be adjusted independently in the horizontal direction and the vertical direction, and the moving position of the subtitle can be arbitrarily set independently in the horizontal direction and the vertical direction.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment in which a subtitle is horizontally compressed by 1/2.

FIG. 2 is a diagram for explaining a second embodiment in which subtitles are vertically compressed by ½.

FIG. 3 is a timing diagram of the first embodiment.

FIG. 4 is a diagram showing a basic configuration of a caption moving circuit.

FIG. 5 is a diagram illustrating an operation of moving a subtitle on a screen having an aspect ratio of 4: 3.

FIG. 6 is a diagram showing input / output terminals of a FiFo memory.

FIG. 7 is a diagram showing a conventional input / output timing of a FiFo memory in a vertical cycle.

[Explanation of symbols]

 1 Input Terminal 2 A / D Converter 3 Memory 4 Memory Controller 5 Character Detection Circuit 6 Mixer 7 D / A Converter 8 Output Terminal 21 Write Line Start Counter 22 Write Line Start Value Setting Circuit 23 Write Line Width Set Counter 24 Subtitle Line Width setting circuit 25,31 NAND circuit 26 1/2 divider 27,34 Switch 28 Read line start counter 29 Read line start value setting circuit 30 Read line width set counter 32 1 / 2H pulse generation counter 33 Delay circuit

Claims (3)

[Claims] 1. A caption moving circuit for supplying a video signal including a caption signal and controlling the memory by a memory controller to move a display position of the caption signal in a vertical direction, wherein the memory is Fast in Fast out Dual. Port memory (F
In the portion where the caption signal exists, a write control unit that gives the FiFo memory write permission for the caption signal at predetermined intervals within one horizontal scanning period, and In a horizontal scanning period different from the given horizontal scanning period, there is provided a read control unit for giving a read permission to the FiFo memory continuously for a predetermined period of one horizontal scanning period. circuit. 2. A subtitle moving circuit that receives a video signal including a subtitle signal and controls the memory by a memory controller to move the display position of the subtitle signal in the vertical direction, wherein the memory is Fast in Fast out Dual. Port memory (F
(iFO memory) is used, and in a portion where a caption signal is present, a write control unit that gives the FiFo memory write permission of the caption signal at predetermined horizontal scanning periods, and a horizontal scanning period different from the horizontal scanning period that has given the write permission. A subtitle moving circuit, comprising: a read control unit that gives read permission to the FiFo memory for the same number of horizontal scanning periods as the number of horizontal scanning periods to which the writing permission has been given in the scanning period. 3. The caption moving circuit according to claim 2, wherein the write control unit gives the write permission given to the FiFo memory at every predetermined horizontal scanning period, in the horizontal scanning period to which the write permission is given. A write control unit that allows writing to occur at predetermined intervals, and the read control unit applies the read permission to the FiFo memory over the same number of horizontal scanning periods as the number of horizontal scanning periods to which the writing permission is given. A caption moving circuit, characterized in that a read control unit is configured to permit a read permission to occur continuously for each predetermined period of one horizontal scanning period for every one horizontal scanning period.