JPH05260233A - Facsimile broadcast receiver - Google Patents

Abstract

PURPOSE:To replace a dual port memory having been used between a data fetch section and a signal processing section with a memory used in general with popularity by adding a simple multiplexer circuit to the receiver. CONSTITUTION:A data fetch section comprising a microprocessor 6 recovers a frame synchronizing signal based on a demodulation clock 3 and demodulation data 2 demodulated by a demodulation circuit 1 to implement descramble processing and de-interleave processing and the processed data are stored in a data memory section 60 in time division via a multiplexer circuit 59 controlled by the microprocessor 6. The stored data are extracted in time division via the multiplexer circuit 59 and error correction processing is implemented and reception processing is implemented by a signal processing section 9. Thus, the multiplexer circuit 59 controlled by the microprocessor 6 shares the data memory with the data fetch section 6 and the signal processing section 9 in time division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television / facsimile multiplex broadcasting (hereinafter referred to as a "multi-channel"), in which a facsimile channel with a second subcarrier is provided in an audio frequency band of a television broadcast radio wave and a facsimile signal is multiplexed with an audio signal for transmission. The present invention relates to a facsimile broadcast receiving device for receiving (facsimile broadcast).

[0002]

2. Description of the Related Art In recent years, the above-mentioned facsimile broadcasting system has been put into practical use. FIG. 6 is a diagram showing a spectrum of an audio frequency band in this facsimile broadcasting system. In addition to the main audio channel and the sub audio channel, a facsimile channel using the second subcarrier is provided.

FIG. 7 is a diagram showing the structure of one frame which is one transmission unit of a facsimile signal. The data transmission rate is 16 Kbps, and the data part of one packet consists of 272 bits (34 bytes) of digital data, and a 16-bit (2 bytes) mode control (MC) code is added at the beginning of this data part. Is added, and one packet is composed of 288 bits (36 bytes). The MC code is composed of information bits b1 to b5 and check code bits b6 to b16.

Further, one frame is composed of 32 packets, and a 16-bit (2 bytes) frame synchronization signal (FC) is added to the beginning of the frame. That is, one frame is composed of 9232 bits (1154 bytes). The 16-bit frame sync signal always has the same code pattern, and scramble for bit sync reproduction is not added.

The 1-frame data is subjected to an interleaving process in which the data in the frame is transmitted vertically bit by bit, following a 16-bit (2-byte) frame synchronization signal (FC).

That is, in order to protect data against burst errors, the first bit of each packet is sequentially transmitted from packet 1 to packet 32 as shown by arrow A in FIG. 7, and the second bit of each packet is further transmitted. Bits are sequentially transmitted, and then 288 of each packet are finally transmitted in the same manner.
The th bit is sequentially transmitted from packet 1 to packet 32.

In the facsimile broadcast receiving apparatus for receiving the facsimile broadcast of such a transmission form, first, the timing of the frame synchronization signal indicating the beginning of the data of one frame is surely detected, and the synchronization with the transmission side is established. The frame synchronization signal is reproduced, the descrambling process and the deinterleaving process are performed, and the data is captured in frame units.

FIG. 8 is a configuration diagram of one packet of a facsimile signal. The data part of one packet is composed of 272 bits (34 bytes) of digital data, and a 16-bit (2 bytes) mode control (MC) code is added to the head of this data part, and 288 bits (3 bytes).
One packet is composed of 6 bytes. Of the above-mentioned 1-packet structure, the error correction target is the data section 2
It is 72 bits.

The error correction system employs a (272,190) shortened difference set cyclic code and has an error correction capability of 8 bits or more in one packet. As this error correction circuit, a circuit that performs error correction processing in units of a minimum of 1 packet and a maximum of 16 packets has already been developed.

The time required for error correction is about 173 μS per packet when the clock supplied to the error correction processing circuit is 8 MHz. Therefore, the error correction processing circuit, when processing a plurality of packets at one time, is 173 μS.
Therefore, the address data control bus is exclusively used for processing in units of an integral multiple of.

FIG. 9 is a diagram showing the configuration of a part of the data capturing section and the signal processing section in the conventional receiving apparatus.
The facsimile signal is guided to the demodulation circuit 1 and demodulated, and the demodulation data 2 and the demodulation clock 3 are derived. The demodulated data 2 and the demodulated clock 3 are supplied to the frame synchronization signal pattern detection circuit 4 and the frequency dividing circuit 5, respectively, and the detection signal 10 in which the code pattern of the frame synchronization signal is detected and the frequency divided clock 11 in which the demodulated clock 3 is divided. Derive.

Reference numeral 6 is the detection signal 10 and the divided clock 1
A microprocessor which reproduces a frame synchronization signal based on 1 and takes in data in 1-byte units by a signal obtained by serial-parallel conversion of the demodulated data 2 through a serial-parallel conversion circuit 12, and performs descrambling processing and deinterleaving processing. 7 is a dual-port memory having two independent input / output ports for storing the fetched data.

Reference numeral 8 is an error correction circuit for taking out the data stored in the dual port memory 7 and performing error correction processing of the facsimile signal. Reference numeral 9 is the error correction circuit 8
It is a microprocessor that receives data that has been subjected to error correction processing.

Next, the operation of the above circuit will be briefly described. Based on the demodulated data 2 demodulated by the demodulation circuit 1 and the demodulation clock 3, the frame synchronization signal pattern detection circuit 4 and the frequency division circuit 5 derive a detection signal 10 and a frequency division clock 11. Based on this detection signal 10 and the divided clock 11,
The microprocessor 6 of the data capturing unit performs reproduction in frame synchronization, converts the demodulated data 2 into serial-parallel data by the serial-parallel conversion circuit 12, captures data byte by byte, performs descrambling processing, and performs descrambling processing. The data is deinterleaved and the data is transferred to the dual port memory unit 7 for each frame.
To store.

On the other hand, the data stored in the dual port memory 7 is taken out frame by frame by the microprocessor 9, the error correction circuit 8 performs error correction processing, and the signal processing of the data after error correction is performed.

[0016]

In the above conventional apparatus, while the facsimile signal is being received, the microprocessor 6 of the data capturing section and the microprocessor 9 of the signal processing section simultaneously read and write data in the memory at independent timings. Therefore, there is a problem that a dual port memory having two independent input / output ports is required and the circuit configuration becomes expensive. The present invention has been made in view of the above points, and it is possible to replace the dual port memory used between the data acquisition unit and the signal processing unit with a commonly used memory. An object is to provide a facsimile broadcast receiving device.

[0017]

In order to achieve the above object, the present invention provides a facsimile channel with a second subcarrier in the audio frequency band of television broadcast radio waves,
In a facsimile broadcast receiver that modulates the second subcarrier by a digitized facsimile signal and multiplexes it into a voice signal, and transmits it, a frame synchronization signal is reproduced based on a demodulation clock and demodulated data demodulated by a demodulation circuit. The descrambling process and deinterleaving process first.
Of the data taken in by the microprocessor, the data memory part for storing the taken data, and the facsimile signal data stored in the data memory part, and the error correction processing circuit performs the error correction to correct the corrected data. A signal processing unit for performing reception processing by a second microprocessor; a multiplexer circuit for switching address / data / control buses so that the data acquisition unit and the signal processing unit can share the data memory unit in a time division manner; A bus switching control means for controlling the multiplexer circuit by the microprocessor of the data fetching section is provided.

[0018]

According to the above construction, based on the demodulated clock and the demodulated data demodulated by the demodulation circuit, the data synchronizing section constituted by the first microprocessor reproduces the frame synchronization signal to perform the descramble processing and the deinterleave processing. The data subjected to these processes are stored in the data memory unit in a time division manner via the multiplexer circuit controlled by the first microprocessor.

The data stored in the data memory unit is time-divisionally extracted through the multiplexer circuit controlled by the first microprocessor, subjected to error correction processing, and supplied to the signal processing unit. Is received. Therefore, the multiplexer circuit controlled by the first microprocessor can share the data memory by the data fetching unit and the signal processing unit in a time division manner.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in the drawings will be described in detail below. FIG. 1 is a block diagram of a facsimile broadcast receiving apparatus according to an embodiment of the present invention. In the figure, 20 is an antenna for receiving television broadcast radio waves, 21 is a receiving unit including a tuner and an audio signal demodulation circuit, and 22 is demodulation for demodulating a facsimile signal from an audio signal including a facsimile signal from the receiving unit 21. It is a department.

Since the facsimile broadcast signal is 4-phase differential phase modulated (4-phase DPSK) and multiplexed with the voice signal, the demodulation unit 22 performs 4-phase differential phase demodulation to sample the bit data string. The demodulation clock and demodulation data of are output.

Reference numeral 23 is a data fetching section, which reproduces frame synchronization by demodulated data and a demodulated clock,
Descramble processing, deinterleave processing, and bus switching are performed. A signal processing unit 24 performs signal processing such as error correction processing and discrimination processing between control data including a program number and page number and image data. An image receiving unit 25 prints pixel data of a required program.

Next, a main part of the data fetching section 23 and a part of the signal processing section 24, which are characteristic configurations of the present invention, will be described in detail with reference to the block diagram shown in FIG. In FIG. 1, the data capturing unit 23 that captures data from the demodulating unit 22 has the following configuration as shown in the block diagram of FIG. In FIG. 2, reference numeral 4 is a frame synchronization pattern detection circuit for detecting the code pattern of the frame synchronization signal based on the demodulation data 2 from the demodulation circuit 1, and 5 is a component for dividing the demodulation clock 3 from the demodulation circuit 1. It is a circuit.

Reference numeral 6 is a micro-controller which reproduces the frame synchronizing signal based on the detection signal 10 from the frame synchronizing signal pattern detecting circuit 4 and the divided clock 11 from the dividing circuit 5 and performs descrambling and deinterleaving processing. Reference numeral 12 denotes a processor, which converts demodulated data 2 which is serial data from the demodulation circuit 1 into parallel data based on the divided clock 11 from the frequency divider circuit 5,
This is a serial-parallel conversion circuit that converts 1-byte data.

Reference numeral 60 denotes a data memory unit for storing data which has been descrambled and deinterleaved.
A multiplexer circuit 59 for switching the address data control bus is provided so that the data memory unit 60 can be shared by the microprocessor 6 and the microprocessor 9 in a time division manner. The multiplexer circuit 59 is controlled by the bus switching control means provided in the microprocessor 6.

Next, the configuration of the signal processing unit 24 in FIG. 1 will be described with reference to the block diagram of FIG. The signal processing unit 24 takes out the data stored in the data memory unit 60 packet by packet and performs error correction, and a micro-processor that receives data that has been subjected to error correction by the error correction circuit 8. It is composed of a processor 9.

In the above structure, the frame synchronization signal pattern detection circuit 4 stores the code pattern of the frame synchronization signal in advance, and stores this code pattern and the bit pattern of the data sequentially input in synchronization with the demodulation clock 3. The detection signal 10 is output when the comparison results in coincidence.

The frequency dividing circuit 5 lengthens the period of an interrupt signal, which will be described later, to allow the microprocessor 6 a margin of processing. The frequency dividing ratio is the number of bits of the frame synchronization signal. And the frame bit number is 9
Any common divisor of 232 may be used, and in this embodiment, the frequency is divided into 8 by matching the bit number of the parallel data by the serial-parallel conversion circuit 12.

The number of bits of the serial / parallel conversion circuit 12 is determined in consideration of the number of data buses of the microprocessor 6 and the operating speed of the microprocessor 6, but in this embodiment, it is set to 8 bits. In addition, it is possible to secure 500 μS corresponding to 8 bits at a transmission rate of 16 Kbps as processing time.

The microprocessor 6 shifts to interrupt processing by the detection signal 10 from the frame synchronization signal pattern detection circuit 4 and the divided clock 11 from the frequency dividing circuit 5 and responds to each interrupt signal with the frame synchronization signal. Playback, descrambling process, and deinterleaving process, and bus switching.

The reproduction of the frame synchronization signal is started at the time when the code pattern of the frame synchronization signal first arrives, that is, the counting of the frequency-divided clock is started using the first detection signal 10 as the reference signal, and the frame synchronization is performed by this count value. The signal cycle is detected, and when the same code pattern arrives a predetermined number of times, for example, three times in succession from the reference signal in the cycle of the frame sync signal, it is determined that a normal frame sync signal is detected and synchronized with it. When the reproduction of the frame synchronization signal is started, and when the same code pattern does not arrive in the cycle, the time point when the code pattern of another frame synchronization signal arrives, assuming that the normal frame synchronization is not detected, that is, Similar processing is performed using another detection signal as a new reference signal to detect and reproduce a regular frame synchronization signal.

FIG. 3 is a timing diagram of bus switching in the data memory unit 60. 3A is a detection signal 10 output from the frame synchronization signal pattern detection circuit 1, B is a frequency division clock 11 output from the frequency division circuit 5 in a 1-byte cycle, and C is a descrambler that takes in 1-byte data. A signal indicating the period required for deinterleave processing, H
The above process is performed during the IGH period. D is a signal indicating a period required until the error correction circuit 8 performs error correction processing for one packet and the microprocessor 9 performs signal processing, and the above processing is performed during the HIGH period.

Here, the descrambling and deinterleaving processing must be carried out by taking in 1-byte data within the 1-byte cycle period of (1), but the descrambling and deinterleaving processing is actually taken in by taking 1-byte data. The period required for is shorter than the 1-byte cycle period of (i) and is a HIGH period of (c). Therefore, the error correction circuit 8 performs the error correction processing of one packet during the period D of the 1-byte cycle period of the above b. Further, since the period required for the microprocessor 9 to perform the signal processing is the HIGH period (E) of I, this is processed within the period of D. Therefore, error correction and signal processing of one packet can be performed during the period D.

Therefore, the multiplexer circuit 59 switches the bus to the side of the microprocessor 6 during the period of 1 byte cycle of (a) and the side of the microprocessor 6 during the high period (C), and to the side of the microprocessor 9 during the period D. The microprocessor 6 and the microprocessor 9 can share the data memory unit 60 in a time division manner. The bus switching process of the multiplexer circuit 59 for enabling the data memory unit 60 to be shared in a time division manner is performed by the microprocessor 6.

FIG. 4 is a flow chart of processing by the microprocessor 6. The frequency-divided clock 11 is input and the frame-synchronized reproduction is performed, so that the processing shifts to the processing in FIG. In FIG. 4, in step R1, 1-byte data is fetched from the serial / parallel conversion circuit 12, a descrambling process is performed on the fetched data, and the process proceeds to step R2. In step R2, the address / data control bus of the data memory unit 60 is switched to the microprocessor 6 side by the multiplexer circuit 59, and the process proceeds to step R3.

At step R3, the data descrambled at step R1 is deinterleaved, the processed data is stored in the data memory unit 60, and the routine goes to step R4. In step R4, the address / data control bus of the data memory unit 60 is switched to the microprocessor 9 side by the multiplexer circuit 59, and the process is terminated.

FIG. 5 is a flow chart of processing by the microprocessor 9. Since the processing of the microprocessor 9 is performed for each packet, the microprocessor 6
After receiving one packet, the processing is performed once. By inputting the divided clock 11,
Process shifts to. In FIG. 5, in step S1, a divided clock counter that counts the divided clock 11 is provided, 1 is added to the divided clock counter, and the process proceeds to step S2.

In step S2, it is determined whether or not the value of the divided clock counter has reached the counter value for one packet. When it is determined that the counter value has not reached one packet, the processing is terminated without doing anything. When it is determined in step S2 that the value of the divided clock counter is the counter value for one packet, the process proceeds to step S3. Step S
In 3, the frequency division clock counter is cleared, and the process proceeds to step S4.

In step S4, it is determined whether the address / data control bus of the data memory section 60 is switched to the microprocessor 9 side. When it is determined that it is switched, the process proceeds to step S5. In step S5, one packet of data in the data memory unit 60 is fetched, the error correction circuit 8 performs error correction processing, and the process proceeds to step S6. In step S6,
In step S5, the error correction circuit 8 receives the data that has been subjected to the error correction processing, and ends the processing.

[0040]

Since the present invention has the above-mentioned configuration, by adding a simple multiplexer circuit, the dual port memory used between the data capturing section and the signal processing section can be converted into a widely used memory. It becomes possible to replace them, and an inexpensive circuit configuration can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of a main part of the present invention.

FIG. 3 is a timing chart showing the timing of bus switching in the data memory unit of the present invention.

FIG. 4 is a flowchart of descrambling, interleaving, and bus switching processing according to the present invention.

FIG. 5 is a flowchart of error correction and data reception processing according to the present invention.

FIG. 6 is a diagram showing a spectrum of a voice frequency band in a facsimile broadcasting system.

FIG. 7 is a diagram for explaining the structure of one frame of a facsimile signal.

FIG. 8 is a diagram for explaining the structure of one packet of a facsimile signal.

FIG. 9 is a block diagram showing the main parts of a data acquisition unit and a signal processing unit in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Demodulation circuit 6 Data acquisition unit 9 Data memory unit 59 Multiplexer circuit 60 Signal processing unit 63 Bus switching control means

Claims (1)

[Claims] 1. A facsimile channel with a second subcarrier is provided in an audio frequency band of television broadcast radio waves,
In a facsimile broadcast receiving apparatus that modulates the second subcarrier by a digitized facsimile signal and multiplexes it into a voice signal, and transmits it, a frame synchronization signal is reproduced based on a demodulation clock and demodulated data demodulated by a demodulation circuit. Then, the first microprocessor performs the descrambling process and the deinterleaving process, the data memory unit that stores the captured data, and the facsimile signal data that is stored in the data memory unit, and performs the error correction process. A signal processing unit that performs error correction in a circuit and performs reception processing of corrected data in a second microprocessor; and an address that enables the data acquisition unit and the signal processing unit to share the data memory unit in a time division manner. A multiplexer circuit for switching the data control bus, and A bus switching control means for controlling the multiplexer circuit by the first microprocessor of the data fetching section is provided, and the signal fetching section and the signal processing section including the error correction processing access the data memory section in a time division manner. Facsimile broadcast receiving apparatus characterized in that.