JPH05258580A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a penetrating current from a writing circuit to write verifying controller circuit by controlling to supply a second voltage to a word line after the writing circuit becomes inactive by the write verifying controller circuit. CONSTITUTION:At the time of writing, since a verifying signal is set on an L level and PGM signal is set on an H level, an nMOS transistor Tr 9 is turned on and a voltage required writing is supplied to the word line. Even if the verifying signal is changed to an H level in this state, nMOS Tr 17 keeps the OFF state since the write verifying control signal SC maintains the L level. When the PGM signal is changed to the L level and nMOS Tr 9 is turned off later, the write veryfying control signal SC becomes to the H level, nMOS Tr 17 is turned on and the voltage necessary for write verification is supplied to the word line. Thus, the nMOS Tr 9 and nMOS Tr 17 are prevented from turning on simultaneously by means of the write verifying controller 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash memory and an EPROM (Erasable and Programmable Read Only).
Memory) and the like.

[0002]

2. Description of the Related Art FIG. 5 is a cross-sectional view schematically showing a memory cell transistor mounted on a flash memory. 1 is a P-type silicon substrate, 2 is a drain made of an N ⁺ diffusion layer, 3 Is a source formed of an N ⁺ diffusion layer, 4 is a floating gate, and 5 is a control gate (word line).

In such a memory cell transistor, for programming, the source 3 is set to 0 [V], about 12 [V] is applied to the control gate 5 and about 6 [V] is applied to the drain 2, and the vicinity of the drain 2 is applied. Floating electrons generated by avalanche breakdown in
It is performed by injecting into the gate 4.

On the other hand, for erasing, the drain 2 is floating, the control gate 5 is 0 [V],
This is performed by applying about 12 [V] to the source 3 and extracting the electrons injected into the floating gate 4 to the source 3 by the tunnel phenomenon.

In reading, the source 3 is set to 0 [V], the control gate 5 is set to about 6 [V], and the drain 2 is set.
Is applied as a voltage change to detect whether or not a drain current flows, and this is amplified.

Heretofore, in the conventional flash memory, as shown in a partial circuit diagram of FIG. 6, in addition to a write circuit (write circuit) 6, a write verification circuit (write verify circuit) 7 is provided. After writing, write verification can be performed (write verify).

In the writing circuit 6, 8 is about 12
VPP line supplying high voltage VPP of [V], 9 is nMO
The S transistors and 10 are PGM signal input terminals to which a PGM (program) signal is input.

In the write verification circuit 7, 11,
12 is a VPP line, 13 to 15 are resistors, 16 and 17 are nM
OS transistor, 18 is pMOS transistor, 19
Is a write verification control signal input terminal to which a write verification control signal SC based on a verify signal supplied from the outside is input, and in the write verification circuit 7, about 6 [V] is obtained at the node 20. The circuit constant is set in.

FIG. 7 is a waveform diagram for explaining the write operation and the write verify operation in the conventional flash memory having the write circuit 6 and the write verify circuit 7 mounted therein.

In this example, first, the PGM signal is set to the H level, the nMOS transistor 9 is turned on (conducting), and the word line is passed through the row decoder for about 12 times.
[V] is supplied, and then the voltage of the bit line is about 6
When set to [V], data is written to the memory cell transistor.

After that, the verify signal is set to H level, the PGM signal is set to L level, the nMOS transistor 9 is turned off (non-conducting), the write circuit 6 is deactivated, and the write verification control is performed. Signal SC is set to H level.

As a result, the nMOS transistor 17 becomes O
N, the word line is supplied with about 6 [V] through the row decoder, and the voltage of the bit line is about 1
At [V], the data of the memory cell transistor is read and the write verification is performed.

[0013]

In such a conventional flash memory, as shown by a broken line 21 in FIG. 7, when the PGM signal is at the H level, that is, before the nMOS transistor 9 is turned off, When the write verification control signal SC is set to the H level, the nMOS transistor 17 is turned on, a through current flows from the VPP line 8 to the ground through the nMOS transistors 9 and 17 and the pMOS transistor 18, and the ground voltage changes, There is a risk of malfunction.

In view of the above point, the present invention is such that, when performing write verification, a through current does not flow from the write circuit to the write verification circuit, and malfunctions due to fluctuations in the ground voltage can be prevented. An object is to provide a semiconductor memory device.

[0015]

A nonvolatile semiconductor memory device according to the present invention includes a write circuit for supplying a first voltage required for a write operation to a word line during a write operation, and a write circuit for a word line during a write verify operation. On the other hand, a write verification circuit that supplies a second voltage necessary for a read operation, and a write verification circuit that supplies a second voltage to a word line after the write circuit is deactivated when performing the write verification. A write verification control circuit for controlling the circuit is provided and configured.

[0016]

In the present invention, the write verification circuit is controlled by the write verification control circuit so as to supply the second voltage to the word line after the write circuit is inactivated when performing the write verification. Therefore, the voltage source of the second voltage of the write verification circuit is not connected to the output end of the write circuit when the write circuit is activated. Therefore, it is possible to prevent a through current from flowing from the write circuit to the write verification circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4 as an example in which the present invention is applied to a flash memory. In FIG. 1, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 1 is a circuit diagram showing an essential part of an embodiment of the present invention. In this embodiment, a write verification control circuit 22 is provided, and other parts are shown in FIG.
It has the same structure as the memory.

Here, the write verification control circuit 22 comprises an inverter 23 and a NOR circuit 24, and the inverter 23 has its input terminal connected to a verify signal input terminal 25 to which a verify signal is input. The output terminal is connected to one input terminal of the NOR circuit 24.

The NOR circuit 24 has a PGM signal input terminal 26 to which the PGM signal is input at the other input terminal.
Is connected to the nMO of the write verification circuit 7.
It is connected to the gate of the S transistor 17. That is,
The write verification control circuit 22 obtains the write verification control signal SC at the output terminal of the NOR circuit 24.

In this embodiment, at the time of writing, as shown in FIG. 2, when the verify signal is at the L level, the PGM is used.
The signal is set to the H level and the nMOS transistor 9 becomes O level.
N, and about 12 [V] required for writing is supplied to the word line through the row decoder. In this case, the write verification control signal SC becomes L level, so that the nMOS transistor 17 is turned off.

In this state, as shown in FIG. 3, even if the verify signal is set to the H level, the write verification control signal S
Since C maintains the L level, the nMOS transistor 1
7 maintains the OFF state.

Thereafter, as shown in FIG. 4, when the PGM signal is set to L level and the nMOS transistor 9 is turned off, the write verification control signal SC becomes H level and n
The MOS transistor 17 is turned on, and about 6 [V] required for write verification is applied to the word line via the row decoder.
Is supplied.

As described above, in the present embodiment, the write verification control circuit 22 controls the write verification control signal SC to become H level after the PGM signal becomes L level, and the nMOS of the write circuit 6 is controlled. The transistor 9 and the nMOS transistor 17 of the write verification circuit 7 are prevented from turning on at the same time.

Therefore, according to the present embodiment, when the write verification is performed, a through current is prevented from flowing from the VPP power supply line 8 to the ground via the nMOS transistors 9 and 17 and the pMOS transistor 18, and the ground voltage varies. It is possible to prevent malfunction.

[0026]

As described above, according to the present invention, when performing the write verification, the write verification circuit supplies the second voltage to the word line after the write circuit becomes inactive. With the configuration controlled by the write verification control circuit, when the write circuit is activated, the voltage source of the second voltage of the write verification circuit is not connected to the output end of the write circuit. It is possible to prevent a through current from flowing from the write circuit to the write verification circuit and prevent malfunction due to fluctuations in the ground voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a write operation and a write verify operation in one embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining a write operation and a write verification operation according to an embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining a write operation and a write verify operation in one embodiment of the present invention.

FIG. 5 is a sectional view schematically showing a memory cell transistor mounted in a flash memory.

FIG. 6 is a circuit diagram showing a write circuit and a write verification circuit mounted on a conventional flash memory.

FIG. 7 is a waveform diagram for explaining a write operation and a write verification operation in a conventional flash memory.

[Explanation of symbols]

 6 Writing Circuit 7 Writing Verification Circuit 22 Writing Verification Control Circuit SC Writing Verification Control Signal

Claims (3)

[Claims] 1. A write circuit for supplying a first voltage required for a write operation to a word line during writing, and a second voltage required for a read operation for the word line during a write verification. And a write verification control circuit for controlling the write verification circuit so as to supply the second voltage to the word line after the write circuit is inactivated when performing the write verification. A non-volatile semiconductor memory device, comprising: 2. The write circuit is electrically connected by a program signal between a voltage source of the first voltage and the word line,
A first switch element whose non-conduction is controlled is provided, and the write verification circuit is configured to conduct or non-conduct between the voltage source of the second voltage and the word line by the write verification control circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is configured by providing a second switch element to be controlled. 3. The write verification control circuit controls the write verification circuit so that the second switch element is rendered conductive only when the program signal is at an inactive level and the verify signal is at an active level. The non-volatile semiconductor memory device according to claim 2.