JP3277542B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash memory and an EPROM (Erasable and Programmable Read Only).
Memory) and the like.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view schematically showing a memory cell transistor mounted on a flash memory, wherein 1 is a P-type silicon substrate, 2 is a drain made of an N ⁺ diffusion layer, Is a source formed of an N ⁺ diffusion layer, 4 is a floating gate, and 5 is a control gate (word line).

In such a memory cell transistor, writing is performed by setting the source 3 to 0 [V], applying approximately 12 [V] to the control gate 5, applying approximately 6 [V] to the drain 2, Floating electrons generated by avalanche breakdown
This is performed by injecting into the gate 4.

On the other hand, for erasing, the drain 2 is floating, the control gate 5 is set to 0 [V],
This is performed by applying about 12 [V] to the source 3 and extracting electrons injected into the floating gate 4 to the source 3 by a tunnel phenomenon.

For reading, the source 3 is set to 0 [V], the control gate 5 is set to about 6 [V], and the drain 2 is set to 0 [V].
About 1 [V] is applied to detect whether a drain current flows or not as a voltage change, and amplify this.

Here, conventionally, a flash memory is provided with a write verify circuit (write verify circuit) 7 in addition to a write circuit (write circuit) 6 as shown in a partial circuit diagram of FIG. After writing, it is configured so that write verification (write verify) can be performed.

In the write circuit 6, 8 is about 12
VPP line for supplying high voltage VPP of [V], 9 is nMO
The S transistor 10 is a PGM signal input terminal to which a PGM (program) signal is input.

In the write verifying circuit 7,
12 is a VPP line, 13 to 15 are resistors, and 16 and 17 are nM
OS transistor, 18 is a pMOS transistor, 19
Is a write verification control signal input terminal to which a write verification control signal SC based on a verify signal supplied from outside is input. In this write verification circuit 7, approximately 6 [V] is obtained at the node 20. Is set to the circuit constant.

FIG. 7 is a waveform diagram for explaining a write operation and a write verify operation in a conventional flash memory having the write circuit 6 and the write verify circuit 7 mounted thereon.

In this example, first, the PGM signal is set to the H level, the nMOS transistor 9 is turned on (conducting), and about 12 lines are supplied to the word line via the row decoder.
[V] is supplied, and then the bit line voltage is
[V] to write data to the memory cell transistor.

Thereafter, the verify signal is set to the H level, the PGM signal is set to the L level, the nMOS transistor 9 is turned off (non-conducting), the write circuit 6 is deactivated, and the write verification control is performed. Signal SC is set to H level.

As a result, the nMOS transistor 17
N, about 6 [V] is supplied to the word line via the row decoder, and the voltage of the bit line is about 1 [V].
[V], data of the memory cell transistor is read, and write verification is performed.

[0013]

In such a conventional flash memory, when the PGM signal is at the H level, that is, before the nMOS transistor 9 is turned off, as shown by a broken line 21 in FIG. When the write verification control signal SC is set to the H level, the nMOS transistor 17 is turned on, a through current flows from the VPP line 8 to the ground via the nMOS transistors 9, 17 and the pMOS transistor 18, and the ground voltage fluctuates. A malfunction may occur.

In view of the foregoing, the present invention provides a non-volatile memory that prevents a through current from flowing from a write circuit to a write verification circuit when performing write verification, thereby preventing a malfunction due to a fluctuation in ground voltage. It is an object to provide a semiconductor memory device.

[0015]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a first voltage source connected between a first voltage source and a word line;
The conduction and non-conduction are controlled by the program signal
The first switching element is provided, upon writing, for the word line
A write circuit for supplying a first voltage, and a voltage of a second voltage
Between the source and the word line by a write verify control signal.
Passing the second switching element non-conductive is controlled provided, during write verification, a write verify circuit for supplying a second voltage for the word line, as a write verify control signal, program
Program signal and verify signal, and the program signal
Only when the active level and verify signal are active level,
A signal for turning on the second switch element is generated, and
At the time of write verification, a write verification control circuit that controls the write verification circuit so as to supply the second voltage to the word line after the first switch element is turned off is provided. That is.

[0016]

In the present invention, the write verifying circuit is controlled by the write verifying control circuit to supply the second voltage to the word line after the write circuit is deactivated when performing the write verifying operation. Therefore, when the write circuit is activated, the voltage source of the second voltage of the write verify circuit is not connected to the output terminal of the write circuit. Therefore, it is possible to prevent a through current from flowing from the write circuit to the write verification circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4, taking a case where the present invention is applied to a flash memory as an example. In FIG. 1, portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a circuit diagram showing a main part of one embodiment of the present invention. In this embodiment, a write verification control circuit 22 is provided, and the other parts are the same as those of the conventional flash memory shown in FIG.
It has the same configuration as the memory.

The write verification control circuit 22 includes an inverter 23 and a NOR circuit 24. The inverter 23 has its input terminal connected to a verify signal input terminal 25 to which a verify signal is input. The output terminal is connected to one input terminal of the NOR circuit 24.

The NOR circuit 24 has a PGM signal input terminal 26 to which a PGM signal is input.
And its output terminal is connected to the nMO of the write verifying circuit 7.
Connected to the gate of S transistor 17. That is,
The write verification control circuit 22 obtains a write verification control signal SC at the output terminal of the NOR circuit 24.

In this embodiment, at the time of writing, as shown in FIG.
The signal is set to the H level, and the nMOS transistor 9
N, and about 12 [V] necessary for writing is supplied to the word line via the row decoder. In this case, the write verification control signal SC becomes L level, so that the nMOS transistor 17 is turned off.

In this state, as shown in FIG. 3, even if the verify signal is set to the H level, the write verification control signal S
Since C maintains the L level, nMOS transistor 1
7 maintains the OFF state.

Thereafter, as shown in FIG. 4, when the PGM signal is set to L level and the nMOS transistor 9 is turned off, the write verification control signal SC is set to H level and n
The MOS transistor 17 is turned on, and about 6 [V] required for write verification with respect to a word line via a row decoder.
Are supplied.

As described above, in the present embodiment, the write verification control circuit 22 controls the write verification control signal SC to go to the H level after the PGM signal goes to the L level. The transistor 9 and the nMOS transistor 17 of the write verifying circuit 7 are not turned on at the same time.

Therefore, according to the present embodiment, when writing verification is performed, a through current is prevented from flowing from the VPP power supply line 8 to the ground via the nMOS transistors 9 and 17 and the pMOS transistor 18, and the ground voltage is changed. Malfunction can be prevented.

[0026]

As described above, according to the present invention, when performing write verification, the write verification circuit supplies the second voltage to the word line after the write circuit is deactivated. With the configuration controlled by the write verification control circuit, when the write circuit is activated, the voltage source of the second voltage of the write verification circuit is not connected to the output terminal of the write circuit. It is possible to prevent a through current from flowing from the write circuit to the write verification circuit, and to prevent a malfunction due to a change in the ground voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a write operation and a write verify operation in one embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining a write operation and a write verify operation in one embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining a write operation and a write verify operation in one embodiment of the present invention.

FIG. 5 is a cross-sectional view schematically showing a memory cell transistor mounted on the flash memory.

FIG. 6 is a circuit diagram showing a write circuit and a write verification circuit mounted on a conventional flash memory.

FIG. 7 is a waveform diagram for explaining a write operation and a write verify operation in a conventional flash memory.

[Explanation of symbols]

 6 Write circuit 7 Write verify circuit 22 Write verify control circuit SC Write verify control signal

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-218098 (JP, A) JP-A-63-268200 (JP, A) JP-A-4-268295 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G11C 16/06

Claims (1)

(57) [Claims] A first voltage is applied between a voltage source of a first voltage and a word line.
A first signal whose conduction and non-conduction are controlled by the program signal
The switching element is provided, the write verification between the write time, a write circuit for supplying the <br/> first voltage for the word line, the word line voltage source of the second voltage
A second switch whose conduction and non-conduction is controlled by the control signal.
The pitch element is provided, during write verify, for the word line
A write verify circuit for supplying the second voltage, as it said write verify control signal, said program signal and
Process the verify signal and the program signal is inactive
Level, only when the verify signal is at the active level,
Generating a signal for turning on the second switch element
Then, at the time of writing verification, the first switch element is turned off.
And a write verification control circuit that controls the write verification circuit so as to supply the second voltage to the word line after the write operation.