JPH05251507A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH05251507A JPH05251507A JP4698092A JP4698092A JPH05251507A JP H05251507 A JPH05251507 A JP H05251507A JP 4698092 A JP4698092 A JP 4698092A JP 4698092 A JP4698092 A JP 4698092A JP H05251507 A JPH05251507 A JP H05251507A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- solder
- wiring board
- electronic component
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明フリップチップ方式によっ
て電子部品が実装される配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which electronic parts are mounted by a flip chip method.
【０００２】[0002]
【従来の技術】近年、半導体素子の微細化に伴い、接続
端子数は多端子化の傾向にある。そのため、半導体チッ
プの実装工程においては従来のワイヤボンディングによ
る端子接続方式では対処しきれなくなっており、新たに
フリップチップボンディング方式が脚光を浴びるように
なった。2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements, the number of connection terminals tends to increase. Therefore, in the mounting process of the semiconductor chip, the conventional terminal connection method by wire bonding cannot be dealt with, and the flip chip bonding method has come into the spotlight.
【０００３】フリップチップボンディング方式とは、図
３に示すように、電極部に半田による突起電極（半田バ
ンプ６）が形成された半導体チップ５と配線基板１と
を、この突起電極を介して電気的に接続するものであ
る。In the flip chip bonding method, as shown in FIG. 3, a semiconductor chip 5 having a protruding electrode (solder bump 6) formed by solder on an electrode portion and a wiring board 1 are electrically connected via the protruding electrode. Are to be connected.
【０００４】このとき、基板１側の半田接続部表面を親
半田金属で構成し、半田接続部周囲を半田に濡れない構
成にする必要がある。図４はその１例であり、半田ダム
構造と称されるものである。これは、表面が親半田性を
有する金属配線上に半田接続部（接続用パッド）７を残
してソルダーレジスト等の被着膜を形成することにより
半田ダム８を形成するものである。At this time, it is necessary to form the surface of the solder connection portion on the substrate 1 side with a parent solder metal so that the periphery of the solder connection portion is not wet with solder. FIG. 4 shows an example thereof, which is called a solder dam structure. In this method, a solder dam 8 is formed by forming an adhered film such as a solder resist while leaving a solder connection portion (connection pad) 7 on a metal wiring having a solder-philic surface.
【０００５】ソルダーレジストは半田濡れ性が悪いた
め、半田バンプ６は接続用パッド７から他の領域にはみ
でることはない。Since the solder resist has poor solder wettability, the solder bumps 6 do not extend from the connection pads 7 to other regions.
【０００６】[0006]
【発明が解決しようとする課題】上述のソルダーレジス
トは一般に印刷方式またはホトプロセスによって図５
（ａ）の如く形成される。しかしながら、印刷方式でソ
ルダーレジストを塗布する場合、微細な半田ダムを形成
することは困難であり、配線の微細化に対応しきれな
い。一方、感光性を有するソルダーレジストを用いたホ
トプロセスでは、レジストを薄くすれば微細な半田ダム
を形成することは困難である。The above-mentioned solder resist is generally formed by a printing method or a photo process.
It is formed as shown in FIG. However, when the solder resist is applied by the printing method, it is difficult to form a fine solder dam, and it is not possible to cope with the miniaturization of wiring. On the other hand, in the photo process using a photosensitive solder resist, it is difficult to form a fine solder dam if the resist is thin.
【０００７】一方、感光性を有するソルダーレジストを
用いたフォトプロセスの場合には、レジストを薄くする
ことによって微細な半田ダムを形成することが可能であ
るが、レジストが薄いと金属配線のエッジ部にピンホー
ルが発生するなどの不具合が生じ（図５（ｃ）参照）、
配線部の信頼性が低下してしまうという問題があった。On the other hand, in the case of a photo process using a photosensitive solder resist, it is possible to form a fine solder dam by thinning the resist. However, if the resist is thin, the edge portion of the metal wiring will be formed. There is a problem such as pinholes on the surface (see Fig. 5 (c)),
There is a problem that the reliability of the wiring portion is reduced.
【０００８】そこで本発明は、微細な半田ダムの形成が
可能で、しかも高い配線部の信頼性を得ることができる
配線基板を提供することを目的とする。[0008] Therefore, an object of the present invention is to provide a wiring board capable of forming a fine solder dam and obtaining high reliability of a wiring portion.
【０００９】[0009]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明はフリップチップ方式を用いて電子部品が
実装される配線基板において、少なくとも実装される電
子部品の接続用パッドに対応した開孔部を有して半田ダ
ム構造を成す第１の被着膜と、前記開孔部近傍以外の領
域の基板上の配線を保護する第２の被着膜とを具備して
なることを特徴とする配線基板である。In order to achieve the above object, the present invention corresponds to at least a connection pad of an electronic component to be mounted on a wiring board on which an electronic component is mounted by using a flip chip method. A first deposition film having an opening and forming a solder dam structure; and a second deposition film protecting the wiring on the substrate in a region other than the vicinity of the opening. It is a characteristic wiring board.
【００１０】[0010]
【作用】第１の被着膜に、実装される電子部品の接続用
パッドに対応した開孔部を設け、この第１の被着膜上に
設ける第２の被着膜で配線を保護する。The first adhered film is provided with an opening corresponding to the connection pad of the electronic component to be mounted, and the second adhered film provided on the first adhered film protects the wiring. ..
【００１１】[0011]
【実施例】以下、図１と図２とを用いて本発明の実施例
を説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
【００１２】図１において符号１は電子部品を実装する
ための配線基板であって、この配線基板１の上には金属
配線２が施されている。この金属配線２のうちの電子部
品の接続される部分には感光性ソルダーレジスト３が形
成される。この感光性ソルダーレジスト３は薄く形成さ
れており、微細加工が施されて開孔部１０が形成され半
田ダムとなる。この開孔部１０の近傍以外の領域には感
光性ソルダーレジスト３よりも厚いソルダーレジスト４
が形成され、このソルダーレジスト４によって配線を保
護する。In FIG. 1, reference numeral 1 is a wiring board on which electronic parts are mounted, and metal wiring 2 is provided on the wiring board 1. A photosensitive solder resist 3 is formed on a portion of the metal wiring 2 to which the electronic component is connected. This photosensitive solder resist 3 is thinly formed, and is subjected to microfabrication to form the opening portion 10 to form a solder dam. A solder resist 4 thicker than the photosensitive solder resist 3 is provided in a region other than the vicinity of the opening 10.
Is formed, and the wiring is protected by the solder resist 4.
【００１３】次に、本発明の配線基板の作成方法を説明
する。Next, a method of manufacturing the wiring board of the present invention will be described.
【００１４】図２（ａ）は基板１上へＡｕ／Ｎｉ／Ｃｕ
等の金属配線２を形成したものである。まず、この金属
配線２のボンディングパッド部に半田ダムとして感光性
ソルダーレジスト３を塗布し、露光、現像工程を行って
図１（ｂ）を得る。FIG. 2A shows that Au / Ni / Cu is formed on the substrate 1.
The metal wiring 2 is formed. First, a photosensitive solder resist 3 is applied as a solder dam to the bonding pad portion of the metal wiring 2 and exposure and development steps are performed to obtain FIG.
【００１５】この感光性ソルダーレジスト３の端部は実
装される部品の端部と一致していることが好ましい。The end of the photosensitive solder resist 3 is preferably aligned with the end of the component to be mounted.
【００１６】この後、ボンディング領域以外の基板１上
にソルダーレジスト４を印刷によって形成して図４
（ｃ）の配線基板を得る。After that, a solder resist 4 is formed on the substrate 1 other than the bonding region by printing to form the solder resist 4 shown in FIG.
The wiring board of (c) is obtained.
【００１７】この配線基板に実装される部品としては半
導体チップが一般的であるが、その他の電子部品一般の
実装にも使用し得ることはいうまでもない。A semiconductor chip is generally used as a component mounted on this wiring board, but it goes without saying that it can also be used for mounting other electronic components in general.
【００１８】[0018]
【発明の効果】以上説明したように、本発明によれば半
田ダム用と配線保護用とで被着膜を分けて使っているた
め、微細な接続パッド部を有し、しかも、信頼性に優れ
たフリップチップ用配線基板を形成することが可能とな
る。As described above, according to the present invention, since the deposited film is used separately for the solder dam and for the wiring protection, it has a fine connection pad portion and has a high reliability. It is possible to form an excellent flip-chip wiring board.
【図１】本発明に係る配線基板の一実施例を示す図であ
る。FIG. 1 is a diagram showing an embodiment of a wiring board according to the present invention.
【図２】本発明に係る配線基板の作成方法を説明する図
である。FIG. 2 is a diagram illustrating a method for producing a wiring board according to the present invention.
【図３】半導体チップのフリップチップボンディングを
説明する図である。FIG. 3 is a diagram illustrating flip chip bonding of a semiconductor chip.
【図４】フリップチップボンディングのボンディング部
の詳細を示す図である。FIG. 4 is a diagram showing details of a bonding portion of flip chip bonding.
【図５】従来例の配線基板を示す図である。FIG. 5 is a diagram showing a conventional wiring board.
１ 基板 ２ 金属配線 ３ 感光性ソルダーレジスト ４ ソルダーレジスト １０ 開孔部 1 substrate 2 metal wiring 3 photosensitive solder resist 4 solder resist 10 opening
Claims (3)
実装される配線基板において、少なくとも実装される電
子部品の接続用パッドに対応した開孔部を有して半田ダ
ム構造を成す第１の被着膜と、 前記開孔部近傍以外の領域の基板上の配線を保護する第
２被着膜と、 を具備してなることを特徴とする配線基板。1. A wiring board on which an electronic component is mounted by using a flip chip method, having a hole portion corresponding to at least a connection pad of the mounted electronic component and forming a solder dam structure. A wiring board comprising: a deposition film; and a second deposition film that protects wiring on the substrate in regions other than the vicinity of the opening.
れ、電子部品端部と前記第２の被着膜端部とが一致して
なることを特徴とする請求項１に記載の配線基板。2. The electronic component is mounted on the first adhered film, and an end of the electronic component and an end of the second adhered film are aligned with each other. Wiring board.
り、前記第２被着膜は比較的厚い膜からなることを特徴
とする配線基板。3. The wiring board according to claim 1, wherein the first deposition film is a relatively thin film, and the second deposition film is a relatively thick film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4698092A JP2726592B2 (en) | 1992-03-04 | 1992-03-04 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4698092A JP2726592B2 (en) | 1992-03-04 | 1992-03-04 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251507A true JPH05251507A (en) | 1993-09-28 |
| JP2726592B2 JP2726592B2 (en) | 1998-03-11 |
Family
ID=12762382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4698092A Expired - Fee Related JP2726592B2 (en) | 1992-03-04 | 1992-03-04 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2726592B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253315A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus |
-
1992
- 1992-03-04 JP JP4698092A patent/JP2726592B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253315A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2726592B2 (en) | 1998-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |