JPH05251462A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To realize optimization of emitter structure by introducing an emitter having the polycrystal/tunnel film/single crystal structure into a bipolar transistor. CONSTITUTION:A collector region 30 is an n-region of about 1X10<14>-1X10<18>cm<-3> formed by the epitaxial technique. A base region is a p-type region having impurity concentration of 10<15>-10<20>cm<-3>. An emitter region 50 is an n<+>-type region of about 10<17>-10<21>cm<-3> in the single crystal Si. A tunnel film 60 is a silicon oxide film which is a part of the emitter having the thickness of 15Angstrom or less. An n<+>-type polycrystalline layer 70 is composed of Si1-xCx, Si or the like having impurity concentration of 10<18>-10<21>cm<-3>. Thereby, a bipolar transistor having excellent high speed characteristic can be manufactured without diffculty.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar transistor structure and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 8 is a sectional view of a conventional bipolar transistor.

In the figure, 10 is phosphorus (P), arsenic (A
substrate doped with impurities such as s) and antimony (Sb) to be an n-type, or doped with impurities such as boron (B), aluminum (Al), gallium (Ga) and p
It is a shaped silicon substrate.

Reference numeral 20 is an n ⁺ region as an embedded region having an impurity concentration of 10 ¹⁶ to 10 ²⁰ cm ^-3 .

Reference numeral 30 denotes an n region as a collector region of about 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ formed by an epitaxial technique or the like.

Reference numeral 40 is a p-type region as a base region having an impurity concentration of 10 ¹⁵ to 10 ²⁰ cm ^-3 .

Reference numeral 45 is a p ⁺ region for reducing the base resistance with an impurity concentration of 10 ¹⁷ to 10 ²¹ cm ^-3 .

50 is an emitter in single crystal Si 1
It is an n ⁺ region of about 0 ¹⁷ to 10 ²¹ cm ⁻³ .

Reference numeral 80 is an n ⁺ region for connecting the collector electrode and the buried layer 20 to reduce the collector resistance.

Reference numerals 100, 110 and 120 denote insulating films for separating electrodes, elements and the like.

Reference numeral 200 denotes wirings and electrodes made of metal, silicide, polycide, or the like.

[0012]

However, in the conventional homo-bipolar transistor, when the size is reduced, the emitter-base depth is made shallow and the concentration is high, and therefore the following problems occur. There is. (1) The breakdown voltage between the emitter and the base becomes low. (2) The current amplification factor is significantly reduced.

Further, a bipolar transistor (hereinafter referred to as BP)
In order to improve its high-speed performance, it is necessary to make the width of the base region thin and increase the concentration.

However, since the current amplification factor (hereinafter abbreviated as h _FE ) decreases as the base concentration increases, it is necessary to maintain a practical value of h _FE and increase the base concentration.

As an example thereof, there is a hetero-bipolar transistor (HBT) using different materials.

As the emitter material of HBT, μC-S
i or a-SiC is used, and Si is used as the base material.
Ge or the like is used.

However, these BPTs use different materials, and therefore the process is complicated and difficult. Further, there is a problem that many of them are unstable with respect to heat treatment.

(Object of the invention) The object of the present invention is to optimize the structure of the emitter, (1) the breakdown voltage between the emitter and the base is high, (2) the current amplification factor is prevented from being lowered, and the maximum performance of the transistor is obtained. The object is to provide a semiconductor device capable of producing by a relatively easy process.

Another object of the present invention is to reduce the resistance of the thin film in a BPT having a thin film through which a tunnel current flows between an emitter region and an emitter electrode and improve the high speed performance of the BPT. To do.

[0020]

The present invention provides, as a means for solving the above-mentioned problems, at least a first region and a second region of the first conductivity type, and a first region and a second region. A third region of a second conductivity type, which is located between and is opposite to the first conductivity type, and adjacent to the first region,
A fourth region having a width wider than the forbidden band of the first region and having a thickness such that majority carriers tunnel to the first region, and a fifth region of the first conductivity type adjacent to the fourth region. ,
Thickness W _E from the interface of the first region with the third region
Is at least smaller than the diffusion length L _P of the minority carriers injected into the first region, and the first region and the fourth region
The effective recombination velocity S _{eff at} the interface of the region is
There is provided a semiconductor device wherein the same or smaller than the diffusion coefficient D _P of the minority carriers in the region between the ratio D _P / L _P of the diffusion length L _P.

The thickness W _E of the first region is not more than 1/3 of the diffusion length L _P of the minority carriers, and the fourth region is a silicon oxide film.
Its thickness is 15 Å or less, and the fifth minority carrier for the minority carriers injected into the first region is characterized by
It is an object of the present invention to solve the above-mentioned problems by a semiconductor device characterized in that the barrier height of the region is 0.1 eV or more.

Further, the present invention further comprises a collector region of the first conductivity type, a base region of the second conductivity type and an emitter region of the first conductivity type, which is provided on the emitter region and allows a tunnel current to flow. A semiconductor device comprising a thin film to be obtained and an electrode laminated on the thin film, wherein at least two kinds of impurities are introduced into the emitter region. And wherein the at least two kinds of impurities are, for example, As ⁺ and P ⁺ ,
Further, a thin film having a collector region of the first conductivity type, a base region of the second conductivity type, and an emitter region of the first conductivity type, the thin film being provided on the emitter region and allowing a tunnel current to flow.
In the method of manufacturing a semiconductor device having an electrode laminated on the thin film, the thin film capable of passing the tunnel current is formed by reacting a surface of the emitter region, and is included in the emitter region. The present invention provides a method for manufacturing a semiconductor device, characterized in that an impurity level for facilitating a tunnel current is formed in the thin film by the impurities contained therein.

Further, in the method of manufacturing a semiconductor device, a thin film capable of passing the tunnel current is formed by oxidizing the surface of the emitter region.

[0024]

According to the present invention, optimum structuring can be performed by using an emitter having a polycrystalline / tunnel film / single crystal structure in a bipolar transistor.

The operation of improving the device characteristics by the means of the present invention will be described below.

FIG. 1 shows a potential diagram of the npn bipolar transistor of the present invention.

In the means for solving the problems of the present invention described above, the first region to the fifth region are bipolar transistors, and the first region is the emitter.
The second region corresponds to the collector, the third region to the base, the fourth region to the tunnel film on the emitter, and the fifth region to the microcrystalline silicon electrode on the tunnel film.

In FIG. 1, the emitter region is composed of an n ⁺ region 1, a tunnel film 4 and an n ⁺ region 5, the base region is represented by a p region 3 and the collector region is represented by an n region 2.

Reference numerals 6 and 7 denote depletion layer regions. Although FIG. 1 shows an npn-type bipolar transistor,
The present invention also applies to an np type bipolar transistor.
The same applies.

Current amplification factor h of bipolar transistor
_FE is represented by the ratio of the collector current I _C to the base current I _B.

The collector current depends on the impurity concentration and distribution of the base.

In the case of the uniform impurity distribution as shown in FIG. 1, it is represented only by the diffusion of minority carriers in the base. In that case, it is shown by the following equation.

[0033]

[Equation 1] However, J _C : collector current density (A / cm ² ), q:
Charge (C), _ni : Intrinsic semiconductor carrier density (c
m ^-3 ), D _n : electron diffusion coefficient (cm ² / sec), N
_B: base impurity density (cm ^-3), W _B: base width (c
m), L _n : electron diffusion length (cm), k: Boltzmann coefficient (eV / ° K), T: absolute temperature (° K), V _BE : base-emitter applied voltage (V).

The collector current is the thickness W _{B of the} base region.
Then, it is apparent from the equation (1) that it is determined by D _n and L _n determined by the majority carrier concentration N _B and the concentration N _B in the base.

On the other hand, the base current is mainly determined by the behavior of minority carriers injected from the base to the emitter.

In the electrogram as shown in FIG. 1, when holes diffuse from the base to the emitter, the solution of the diffusion equation is represented by the following equation.

[0037]

[Equation 2]

[0038]

[Equation 3] J _B : base current density (A / cm ² ), W _E : emitter depth (cm), L _P : hole diffusion length (cm), D _P : hole diffusion coefficient (cm ² / sec), N _E : Emitter impurity density (cm ^-3 ), ΔE _g : band gap narrowing width (eV) of the emitter, ΔE _B : potential difference in the emitter (e
V), S _eff : Effective recombination velocity (cm / sec), S
_O : Recombination rate at the tunnel film / Si interface (cm / se
c), T _i : tunnel coefficient of tunnel film, L _poly : minority carrier diffusion length (cm) in wide gap region, D
_poly : minority carrier diffusion coefficient (cm ² / sec) in the wide gap region.

As is apparent from the equations (2) and (3), which of the conditions n _B , W _E and S _eff of the n ⁺ emitter region determines which one is dominant.

The S _eff is determined by complicated conditions.

In the conventional transistor, the tunnel film and the wide gap material are immediately terminated with a metal, which corresponds to the case where S _eff is made infinite.

When S _{eff is set} to infinity in the equation (2), the following equation is obtained.

[0043]

[Equation 4] Taking the ratio to compare with the conventional transistor,

[0044]

[Equation 5] Becomes R allows easy comparison with conventional devices.

From equation (2)

[0046]

[Equation 6] As the base saturation current density J _BO (S _eff ) (A / cm
² ) and S _eff are shown in FIG. Fig. 3 shows the vertical axis J
_BO (A / cm ² ), horizontal axis S _eff (cm / sec), and emitter impurity density N _E (cm ⁻³ ) as a parameter. The emitter depth W _E is fixed at 0.1 μm.

When S _eff is 10 ⁶ cm / sec or more, it becomes the same as that of the metal electrode and becomes the same as the expression (4). When S _eff decreases, J _BO is less, the higher is N _E is lower J _BO
Can be achieved. When N _E is 1 × 10 ²⁰ cm ^−3, it is possible to achieve a reduction of J _BO of 1 to 10 digits, and 1 × 10 ¹⁹ cm ⁻³ to a few digits. Since the collector current depends on the base condition,
The conventional transistor and the transistor of the present invention have the same value. Therefore, the reduction of the base current directly leads to the improvement of the current amplification factor.

From FIG. 3, if S _eff is approximately tens of thousands of cm / sec or less, the improvement of J _BO can reach one digit or more. Qualitatively, D _P / L _{P ≈S eff} or D _P /
If L _P > S _eff and S _eff is sufficiently small, J _BO
Will occur. However, W _E << L _P is a necessary condition, and it is necessary that the minority carriers injected from the base reach the tunnel film. W at D _P / L _P ≈ S _{eff
When P} / L _P << 1, R decreases by about W _E / L _P.

FIG. 4 shows the emitter depth W _E (μm) and R with N _E = 10 ¹⁹ cm ⁻³ constant. S _eff is used as a parameter. The smaller W _E is, the smaller R is. W
_E is W _E ≤ 1/3 L _P (however, D _P / L _P ≈S
_eff ) makes the effect clearer.

Next, the effective recombination velocity S _eff shown in the equation (3) will be considered. In determining S _eff , T _i determined by S _O and the tunnel film thickness is first important. S _O depends on the nature of the interface. In a normal semiconductor process, it is in the order of several hundreds to tens of thousands of cm / sec, though it depends on the conditions. The second term of the tunnel film becomes thick T _i becomes smaller (3) right-hand side is smaller than the first term S _O, S _O only S
_eff comes to be decided.

FIG. 5 shows S _eff as a function of tunnel oxide film thickness. S _O is 1000,1000
2 types of 0 cm / sec, ΔE _B is 0, 0.02, 0.
05, 0.1, and 0.2 eV are shown. When the oxide film becomes 10 Å or less, the tunnel coefficient T _i becomes large, and the oxide film diffuses toward the wide gap material side. Therefore, S _eff becomes large. The only way to suppress this is to increase ΔE _B. ΔE _B ≧
If it is 0.1 eV, even if the oxide film thickness approaches 0, there is a considerable effect, and if it is 0.2 eV or more, diffusion of holes into the almost perfect wide-gap material does not occur and a sufficient barrier is obtained. Have an effect.

This potential barrier is generated by the fifth step shown in FIG.
Not only the wide bandgap in the region but also the same bandgap width as shown in FIG. 15, the potential barrier may be formed by changing the Fermi level. As the method, a substantial Fermi level shift can be realized by using a difference in impurity concentration or by using a quantum effect by atomizing the fifth region.

When the tunnel film becomes thick, the emitter resistance becomes very large, which adversely affects the high speed response of the transistor.

Factors that affect the emitter resistance include resistance in the polysilicon electrode and contact resistance between the polysilicon electrode and the AL electrode in addition to the resistance through the thin film. The resistance component is the largest.

It is known that the emitter resistance deteriorates the high speed characteristics of BPT. The cutoff frequency (f _T ) that is a standard for high-speed operation of the BPT is the series resistance (R) of the emitter.
_E ) lowers.

It has been found that this relationship is represented by the following equation. (Influence on cut-off frequency (f _T ) of emitter resistance (R _E ) in C-558 bipolar transistor of IEICE Spring National Congress 1991) f _T = f _T0 / (1 + 2πf _T0 · R _E · C _BC ) ... (10) f _T0 : Cutoff frequency when there is no emitter resistance C _BC : Base-collector junction capacitance When there is no emitter resistance, f _T maximum value is 20 GHz
If there is a BPT that can be output, R _E is 50Ω and C _BC is 50
If it is fF, the maximum value of f _T is 15G from the equation (10).
It will drop to Hz.

The series resistance caused by the tunnel oxide film can be calculated. The barrier height of electrons in Si in the conduction band of the Si oxide film is about 3 eV, but according to the literature, the barrier height becomes lower as it becomes an oxide film of ultra-thin film, and when it becomes close to -10Å, It seems to go down to about 1 eV. In SiO ₂ of 10~15Å thickness in Experiment 1
The resistance value is about 0 ⁻⁵ to 10 ⁻⁴ Ω · cm ² .

In FIG. 6, the barrier height x _e is 0.5, 1, 2.
In the case of eV, the series resistance value with respect to the oxide film thickness was calculated and shown. In comparison with the experimental value, x _e ~ 0.5 ~ 1
It is considered to be about eV. The oxide film should be thinner than about 15Å. The resistance decreases by about one digit only by thinning it by a few Å.

As described above, the transistor of the present invention has a smaller base current than the conventional transistor. This has the same effect as that of the hetero bipolar transistor, and is a structure suitable for a high-speed BPT that requires a base region with a high concentration and a shallow junction depth.

As another method of lowering the emitter resistance, at least two kinds of impurities are introduced into the emitter region,
There is a method in which a thin film formed by reacting this is used as a thin film through which the tunnel current can flow.

In the thin film formed by this method, since the impurity level is formed in the film, a tunnel current easily flows, so that the resistance can be lowered.

As described above, the transistor of the present invention has a smaller base current and a larger current amplification factor than the conventional transistor. The conditions are summarized as follows: (1) W _E / L _P ≤1 / 3 (2) S _eff ≤D _P / L _P (3) Tunnel oxide film thickness 15 Å or less (4) ΔE _B ≧ 0.1 eV is optimized It becomes a condition to reach.

[0063]

(Embodiment 1) FIG. 2 is a sectional view of a bipolar transistor as an embodiment of the present invention.

In the figure, 10 is phosphorus (P), arsenic (A
substrate doped with impurities such as s) and antimony (Sb) to be an n-type, or doped with impurities such as boron (B), aluminum (Al), gallium (Ga) and p
It is a shaped silicon substrate.

Reference numeral 20 is an n ⁺ region as an embedded region having an impurity concentration of 10 ¹⁶ to 10 ²⁰ cm ^-3 .

Reference numeral 30 designates an n region as a collector region of about 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ formed by an epitaxial technique or the like.

Reference numeral 40 is a p-type region as a base region having an impurity concentration of 10 ¹⁵ to 10 ²⁰ cm ^-3 .

Reference numeral 45 is a p ⁺ region for reducing the base resistance with an impurity concentration of 10 ¹⁷ to 10 ²¹ cm ^-3 .

50 is an emitter in single crystal Si 1
It is an n ⁺ region of about 0 ¹⁷ to 10 ²¹ cm ⁻³ .

Reference numeral 60 denotes a silicon oxide film as a tunnel film which is a part of the emitter and has a thickness of 15 Å or less.

70 is made of Si _1-X C _X , Si, etc.,
The impurity concentration is 10 ¹⁸ to 10 ²¹ cm ^-3 n ⁺
It is a polycrystalline layer.

Reference numeral 80 is an n ⁺ region for connecting the collector electrode and the buried layer 20 to reduce the collector resistance.

Reference numerals 100, 110 and 120 are insulating films for separating electrodes, elements and the like.

Reference numeral 200 denotes wirings and electrodes formed of metal, silicide, polycide or the like.

Next, a manufacturing process of the semiconductor device shown in FIG. 2 will be described. (1) By implanting As, Sb, P or the like into the p-type or n-type substrate 10 by ion implantation or impurity diffusion, the n ⁺ buried region 20 (impurity concentration 1 × 10 ¹⁶ to 1 × 10 ²⁰ c
m ⁻³ ) was prepared. (2) An n region (impurity concentration 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ ) 30 was produced by an epitaxial technique or the like. (3) n ⁺ region 80 for reducing collector resistance
(1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ ) was produced by ion diffusion and thermal diffusion. (4) The element isolation region 100 is manufactured by the selective oxidation method. (5) Using a resist mask, B is selectively ion-implanted and then heat-treated to form a p-type base region 40 and a p ⁺ region 45 for lowering the base resistance. (6) After depositing a silicon oxide film 120 by chemical vapor deposition (CVD) and then opening an emitter contact A
An n ⁺ region 50 to be an emitter region in the single crystal is formed by heat-treating s, P, Sb, etc. after ion implantation. (7) A thin tunnel insulating film 60 is formed.

In this embodiment, after the normal cleaning, the diluted HF treatment is performed to remove the natural oxide film, and then the oxidation at a low temperature of 500 to 650 ° C. is performed by the rapid thermal annealing method. (8) After depositing microcrystalline polysilicon by a low pressure CVD method, after ion-implanting Ph, As, etc., heat treatment is performed at a temperature not breaking the thin tunnel oxide film 60, a temperature of 900 ° C. or less, and then patterning is performed. Form area 70. (9) A silicon oxide film, a silicon nitride film or the like 110 is deposited by the CVD method, and after heat treatment, an opening is formed in a contact region for joining electrodes. (10) Al-Si (1%) to be the electrode 200 is sputtered, and then Al-Si is patterned.

The tunnel insulating film 60 in the present invention may be made of a material other than the silicon oxide film, such as a silicon nitride film, aluminum oxide and silicon carbide.

As the material 70 on the tunnel film 60, not only microcrystalline silicon but also a polycrystalline material (Si _1-X C _X ) mixed with carbon or Si _1-X mixed with oxygen is used.
A material of O _X and the like may be. Not limited to only Si type,
It may be a compound material of II-VI or III-V type.

In the means for solving the problems of the present invention described above, the first to fifth regions are the emitter 5 in the case of the bipolar transistor of this embodiment.
0, the second region is the collector 30, the third region is the base 40,
The fourth region corresponds to the tunnel film 60 on the emitter, and the fifth region corresponds to the polysilicon electrode 70 on the tunnel film.

In the present embodiment, the fourth region is wider than the forbidden band width of the first region and the fifth region has minority carriers injected into the first region in the fourth region by the manufacturing process described above. It has an energy barrier height that blocks after passing through the tunnel, and a thickness W _E from the interface of the first region with the third region is at least smaller than the minority carrier diffusion length L _P injected into the first region, Moreover, the effective recombination velocity S _{eff at} the interface between the first region and the fourth region is equal to or smaller than the ratio D _P / L _P of the diffusion coefficient D _P of the minority carriers in the first region and the diffusion length L _P.

The thickness W _E of the first region is 1/3 or less of the diffusion length L _P of the minority carriers, and the fourth region is a silicon oxide film having a thickness of 15Å or less.

Further, the barrier height of the fifth region against the minority carriers injected into the first region can be changed by controlling the grain size of polysilicon and the impurity concentration. Further, in the case of the Si _1-x C _x polycrystal and the Si _1-x O _x polycrystal, it can be controlled to 0.1 eV or more by changing the composition.

FIG. 7 shows current-voltage characteristics of the transistor of the present invention and the conventional transistor. The transistor of the present invention and the conventional transistor are shown in FIG.
0, 30, etc. are exactly the same, and the electrode portion is changed to a poly-Si / tunnel film and an Al-Si electrode for comparison. As shown in the figure, the collector currents match, but the base current is about 1/100 in the transistor of the present invention, which is an obvious improvement. (Embodiment 2) Next, an example of forming a tunnel film having a low emitter resistance by introducing two or more kinds of impurities into the emitter region and reacting them with each other will be described.

FIG. 9 is a schematic sectional view showing a preferred embodiment of the present invention. 9A is a sectional view of the BPT, and FIG. 9B is an enlarged view of the vicinity of the emitter region of the BPT.

In FIG. 9, 901 is a P-type substrate, and 902.
Is an N-type buried region formed to reduce collector resistance, and 903 is an N ⁻ region which is a collector region, which is formed by an epitaxial technique or the like.

Reference numeral 904 is an element isolation region formed of an oxide film, and 9
Reference numeral 05 is an oxide film, and 906 is an N-type region for reducing collector resistance.

Reference numeral 907 denotes a P ⁺ region for reducing the base resistance, and 908 denotes a P region which is a base region.

Reference numeral 909 is an N ⁺ emitter region, 910 is an interface oxide film capable of passing a tunnel current, and 911 is an N-type polysilicon region which is an electrode of the emitter region.

Reference numeral 912 is an insulating film, and 913 is a metal electrode such as AL.

Next, the manufacturing method of this embodiment will be described with reference to the manufacturing process sectional views of FIGS.

First, an N-type region 902 is formed at a desired location on the P-type semiconductor substrate 901, and then an N-type epitaxial region 903 is formed.

Subsequently, silicon in a desired place is etched, and only this portion is selectively oxidized to form an element isolation region 904. Then, an N-type impurity is introduced into a desired place and heat treatment is performed to form an N-type region connecting the N-type region 902 and a metal electrode described later (FIG. 10).
(A)).

Thereafter, the film thickness of 150 to 50 is formed by thermal oxidation.
An oxide film 905 having a thickness of about 0Å is formed. Subsequently, a P-type impurity is introduced into a desired place and heat treatment is performed to form an external base region 907.

Next, a P-type impurity is introduced into a desired place, and then an N-type impurity is introduced into a desired place, and heat treatment is performed to form a base region 908 and an emitter region 909. In this example, two types of impurities, arsenic As and phosphorus P, were implanted as N-type impurities (FIG. 10).
(B)).

As a method of introducing impurities to form these base region and emitter region, there are ion implantation and diffusion from an impurity source deposited on the substrate surface. A BPT having excellent high-speed characteristics is desired to have a shallow junction in both the base region and the emitter region. Therefore, an ion implantation method is desired in which the impurity profile can be easily controlled.

For forming the base region, B ⁺ is generally used.
(Boron) ions or BF ₂ ⁺ ions are used, but BF ₂ ⁺ ions are preferable for forming a shallow junction.

Further, as a heat treatment method, a heat treatment by a rapid thermal annealing method (RTA) or the like which can activate carriers while suppressing diffusion of impurities is more preferable than heat treatment by an electric furnace which is generally used. Be done.

Next, the oxide film at a desired place on the emitter region is etched and removed.

Then, the substrate is inserted into a polysilicon film forming apparatus and the natural oxide film existing in the portion where the oxide film has been removed is completely removed in an HF atmosphere of about 1%.

Then, oxidation at 500 to 660 ° C. is applied to the portion from which the oxide film has been removed by a rapid thermal annealing method by about 10Å.
An oxide film capable of passing the tunnel current of is formed.

Thereafter, the temperature is lowered to 620 ° C., and polysilicon is deposited in a thickness of 2000 to 4500 Å.

N-type impurities were ion-implanted into the polysilicon, heat treatment was performed, and then patterning was performed to form a polysilicon electrode (FIG. 10C).

The ion implantation conditions and heat treatment conditions for the N-type impurities were set such that the oxide film capable of passing the tunnel current was not destroyed during these processes.

The amount of impurities introduced into polysilicon is, for example, 2.5 × 10 ¹⁵ to 1 × 10 ¹⁶ [ions / cm ² ].
And

The heat treatment temperature is, for example, 900 ° C. and 10 m.
in, 850 ° C., 30 min.

Next, a PSG film or BP is formed by using the CVD method.
After forming the insulating film 912 such as the SG film, the insulating film at a desired position was etched to form a contact hole.

Subsequently, a metal such as AL is deposited by the sputtering method and then etched to form electrodes 913 of the emitter region 909, the base region 908 and the collector region 903.

FIG. 11 shows N implanted with ions in the emitter region.
The relationship between the dose of arsenic and phosphorus, which are shape impurities, and the contact resistivity is shown. Ion implantation was performed for each impurity through a 200 Å oxide film. The contact resistivity was measured by the Kelvin method.

For all the impurities, the contact resistance decreased as the dose increased. Moreover, the contact resistivity of the phosphorus-implanted sample was lower than that of the arsenic-implanted sample.

From this, it is considered that the impurities contained in the emitter region form an impurity level which is taken into the oxide film during the formation of the oxide film to facilitate the flow of the tunnel current.

When the dose amount of any impurity is the same, the peak concentration of the emitter region is almost the same,
It is considered that the level of the formed level is different depending on the impurity because the resistivity is changed depending on the impurity.

As described above, in order to improve the high speed characteristics of BPT, it is preferable that the contact resistivity is low. From this point of view, it seems appropriate to use phosphorus.

However, phosphorus is more likely to be thermally diffused than arsenic and causes a phenomenon such as emitter push. Therefore, it is difficult to form a shallow junction structure essential for high-speed BPT.

Further, in a semiconductor characterized by having a thin film through which a tunnel current can flow and an electrode laminated on the thin film, h _FE becomes larger as the emitter junction becomes shallower, and the base concentration can be increased. When phosphorus, which is easy to diffuse, is used as an impurity, compared with the case of As ⁺ ,
Since it is not possible to increase the base concentration while ensuring h _FE , it is not very suitable as a high-speed operation BPT.

In FIG. 12, 1 × 10 ¹⁵ arsenic is used as an impurity.
(Ions / cm ² ), 40 KeV ion implantation, and phosphorus at 1 × 10 ¹⁴ to 1 × 10 ¹⁵ ions / cm ² , 2
The dose amount and the contact resistivity when implanted at an acceleration energy of 2 KeV are shown.

The acceleration energy at the time of phosphorus ion implantation is set as low as 22 KeV so that the diffusion of phosphorus does not affect the emitter profile, and the dose amount is 1 × with respect to 1 × 10 ¹⁵ ions / cm ^{2 of} arsenic. 10 ¹⁵ ion
It was set to s / cm ² or less.

As shown in FIG. 12, the contact resistivity was lowered by adding phosphorus to arsenic.

[0118] The maximum value of the cutoff frequency according to the result dose of P ^+, as shown in Figure 13 is increased (f _T
MaX ) increased.

However, if the dose amount of P ⁺ increases, P
The diffusion of ⁺ reduced h _FE .

As described above, by introducing As ⁺ into the emitter region and further introducing P ⁺ , the resistance of the oxide film obtained by thermally oxidizing the surface of the substrate can be lowered.

Up to this point, after ion implantation of As ⁺ ,
The case where P ⁺ is ion-implanted has been described.
This is not limited to P ⁺ , but similar effects can be obtained with ions such as antimony (Sb ⁺ ) and germanium (Ge ⁺ ).

Further, although the oxide film has been described as the thin film capable of passing the tunnel current, the insulating film is not limited to the oxide film and may be another insulating film such as a nitride film. (Embodiment 3) In the embodiment 2, the case where the BPT is manufactured by using the lithography technique which has been conventionally used is described. The case where they are used consistently is shown.

The manufacturing method is shown in FIG. 14 and FIG.
This will be described with reference to FIG.

In the second embodiment, ion implantation of the emitter region 909 is performed after ion implantation of the base region 908.

In this embodiment, a contact hole for a polysilicon electrode is formed after ion implantation of the base region 908. After that, ions are implanted into this contact hole to form an emitter region 909 in a self-aligned manner with respect to the contact hole.

In this case, the oxide film 905 is set to a film thickness such that ions do not reach the substrate by ion implantation. For example, under the ion implantation condition of As ⁺ 40 KeV, the oxide film thickness is set to 500 Å or more.

Subsequently, the base region 908 and the emitter region 9
The heat treatment of 09 is performed. After that, the same process as in Example 2 is performed.

By thus forming the emitter region in a self-aligned manner with the contact hole of the polysilicon electrode, the size of the emitter region can be reduced to about the same size as the contact hole.

Since a smaller emitter size is better for higher BPT speed, higher speed can be realized by the emitter forming method of this embodiment.

[0130]

As described above, according to the present invention, a bipolar transistor having a high-concentration, shallow-junction base region, a low emitter resistance, and an excellent high-speed characteristic is formed based on the conventional silicon-BPT manufacturing process. With the above-described process, it is possible to obtain the effect of being able to manufacture without difficulty in the process.

Furthermore, according to the present invention:
Compared to conventional transistors, it reduces the base current and increases the current amplification factor.-The current amplification factor can be kept high even when miniaturized, and the junction breakdown voltage can be increased.-Ideal for high-speed devices. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a potential diagram of an npn-type bipolar transistor of the present invention.

FIG. 2 is a sectional view of a bipolar transistor as an embodiment of the present invention.

FIG. 3 Effective recombination velocity (S _eff ) and base current density J
It is a figure which shows the relationship of.

FIG. 4 is a diagram illustrating a basic operation of a SIS bipolar transistor.

FIG. 5 is a diagram showing a relationship between an oxide film thickness and an effective recombination rate S _eff .

FIG. 6 is a diagram showing a relationship between an oxide film thickness and a resistance value.

FIG. 7 is a diagram showing current-voltage characteristics of a transistor of the present invention and a conventional transistor.

FIG. 8 is a diagram showing a cross-sectional view of a conventional bipolar transistor.

FIG. 9 is a sectional view of the semiconductor device shown in Example 1 of the present invention.

FIG. 10 is a sectional view of a manufacturing process of the semiconductor device shown in the first embodiment.

FIG. 11 is a graph showing the relationship between the ion implantation dose of N-type impurities and the contact resistivity.

FIG. 12 shows As ⁺ ions at 1 × 10 ¹⁵ ions / cm ^2.
6 is a graph showing the relationship between the dose amount of P ⁺ ions and low contact efficiency when P ⁺ ions are further implanted.

FIG. 13 shows As ⁺ ions at 1 × 10 ¹⁵ ions / cm ^2.
The graph showing the relationship between the dose amount of P ⁺ ions and the maximum value of the BPT current amplification factor and cutoff frequency when P ⁺ ions are further injected.

FIG. 14 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 15 is a potential diagram showing an example in which a potential barrier is created by changing the Fermi level.

[Explanation of symbols]

1 emitter (n ⁺ region) 2 collector (n region) 3 base (p region) 4 tunnel film 5 n ⁺ region 6, 7 depletion layer 10 n-type substrate 20 n ⁺ region 30 collector region 40 base region 50 emitter region 60 tunnel Film 70 n ⁺ Polycrystalline layer 80 n ⁺ Region 200 Metal electrode 901 Silicon substrate 902 Embedded region 903 Collector region 904 Element isolation region 905 Oxide film 906 N type region for reducing collector resistance 907 P type region for reducing base resistance 908 Base region 909 Emitter region 910 Oxide film capable of passing tunnel current 911 N-type polysilicon 912 Insulating film 913 Metal electrode

Claims (9)

[Claims] 1. At least a first region and a second region of a first conductivity type, and a second conductivity located between the first region and the second region and having a conductivity type opposite to the first conductivity type. A third region having a shape, and a fourth region formed adjacent to the first region, having a width wider than the forbidden band of the first region, and having a thickness such that majority carriers tunnel to the first region, A fifth region of the first conductivity type adjacent to the fourth region, the thickness W _E from the interface of the first region with the third region
Is smaller than at least the diffusion length L _P of the minority carriers injected into the first region, and the effective recombination velocity S _{eff at} the interface between the first region and the fourth region is less than the minority in the first region. A semiconductor device characterized in that the ratio of carrier diffusion coefficient D _P to diffusion length L _P is D _P / L _P or less. 2. The semiconductor device according to claim 1, wherein the thickness W _E of the first region is 1/3 or less of a diffusion length L _P of the minority carriers. 3. The semiconductor device according to claim 1, wherein the fourth region is a silicon oxide film and has a thickness of 15 Å or less. 4. The fifth region has an energy barrier height that blocks minority carriers injected from the third region into the first region after passing through a tunnel in the fourth region. Item 2. The semiconductor device according to item 1. 5. The semiconductor device according to claim 1, wherein a barrier height of the fifth region with respect to minority carriers injected into the first region is set to 0.1 eV or more. 6. A first conductivity type collector region, a second conductivity type base region, and a first conductivity type emitter region,
In a semiconductor device having a thin film provided on the emitter region and capable of flowing a tunnel current, and an electrode laminated on the thin film, at least two kinds of impurities are introduced into the emitter region. A semiconductor device characterized by the above. 7. The at least two types of impurities are As.
The semiconductor device according to claim 6, wherein the semiconductor device is ⁺ and P ⁺ . 8. A first conductivity type collector region, a second conductivity type base region, and a first conductivity type emitter region,
In a method for manufacturing a semiconductor device, which is provided on the emitter region and has a thin film capable of passing a tunnel current and an electrode laminated on the thin film, the thin film capable of passing the tunnel current is A method for manufacturing a semiconductor device, which is formed by reacting a surface, and an impurity level that facilitates a tunnel current to flow is formed in the thin film by the impurities contained in the emitter region. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the surface of the emitter region is oxidized to form a thin film through which the tunnel current can flow.