JPH0525120Y2 - - Google Patents

Description

[Detailed description of the invention] A. Industrial application field The present invention relates to equalization circuits, and in particular,
CMOS (complementary metal oxide)
static type RAM with semiconductor) configuration
(ramdom access memory).

B. Summary of the invention This invention is an equalization circuit that equalizes the potential of a pair of bit lines in a RAM, and is used in the RAM as an equalization MOS transistor that shorts the pair of bit lines when an equalization pulse signal is applied. By applying an N-channel MOS type transistor having a lower threshold voltage than other N-channel MOS type transistors, the current drive capability of the equalizing transistor is increased and the equalizing period is shortened.

C. Prior Art A static RAM having a CMOS structure is constructed by arranging memory cells 10, each of which is a flip-flop circuit of a MOS transistor, in a matrix, as shown in FIG.

Each memory cell 10 arranged in parallel in the row direction is connected to a common word line 11, and each memory cell 10 arranged in parallel in the column direction is connected to a common pair of complementary bit lines 12 and 13. has been done. When accessing a predetermined memory cell 10, the word line 11 to which the memory cell 10 is connected is selected by an unillustrated X decoder, and the Y
A pair of bit lines 12 and 13 to which the memory cell 10 is connected is selected by the decoder,
In this way, only predetermined memory cells are activated and data can be written or read.

A pair of bit lines 12 and 13 are connected to an N-channel MOS transistor Q1 whose gate terminal and drain terminal are respectively connected to the power supply line L1.
and the source terminal of Q2. Also,
A pair of bit lines 12 and 13 are connected to the source and drain terminals of a P-channel MOS type transistor Q3, respectively, whose gate terminal is supplied with an equalizing pulse signal _φEQ .

The pair of bit lines 12 and 13 is arranged so that when the write data is logic "H", bit line 12 has a low potential of about 1 to 2 [V] and bit line 13 has a high potential of about 4 to 5 [V]. Conversely, when the write data is logic "L", the bit line 12 is 4 to 5.
At a high potential of about [V], the bit line 13 is 1 to 2 [V]
The voltage is set to a relatively low potential to operate the flip-flop circuit of the memory cell 10. Furthermore, when the read data from the memory cell 10 is at logic "H", the bit line 12
The potential of the bit line 13 becomes about 2 to 3 [V], the potential of the bit line 13 becomes about 4 to 5 [V], and when the logic is "L", the potential of the bit line 12 becomes about 4 to 5 [V],
The potential of the bit line 13 becomes about 2 to 3 [V].

If the transistor Q3 is not provided in a RAM that takes such a potential, the access time will be longer and the logic "L" data will be read in any read cycle, and the logic "H" data will be read in the next cycle. In the case of reading, the bit line 12 becomes 2 to 3 due to the previous reading.
[V], and the bit line 13 is at 4 to 5 [V], so when the memory cell 10 is selected for the next read, the stored contents may be accidentally inverted and destroyed due to these potentials. There is a risk that the next read data will be different from the original stored content.

Therefore, when accessing the memory cell 10, the transistor Q3 is turned on by the pulse signal _φEQ to equalize the potentials of the pair of bit lines 12 and 13, thereby preventing a malfunction due to the data state caused by the previous access. I'm trying to prevent it.

D. Problems to be solved by the invention By the way, the access time also includes the time for equalization described above. Therefore, in order to shorten access time and speed up processing, it is desirable to shorten the time for equalization.

However, if a P-channel MOS transistor is applied to the equalizing transistor Q3 as shown in FIG.
Because MOS transistors have slow carrier mobility, it takes a long time for equalization.

This idea was created taking the above points into consideration.
The present invention aims to provide an equalization circuit that can equalize a pair of bit lines in a short time and shorten RAM access time.

E. Means for solving the problem In order to solve the problem, in the present invention, a pair of bit lines 1 of the RAM having a CMOS configuration are used.
The source terminal and the drain terminal are respectively connected to 2 and 13, and an equalizing pulse signal ( φ _EQ or φ _EQ ) is supplied to the gate terminal, and the pair of bit lines 12 and 13 are short-circuited to equalize the equalizing MOS. In the equalizing circuit including the MOS transistor Q3, the equalizing MOS transistor Q3 is formed of an N-channel MOS transistor having a lower threshold voltage than other N-channel MOS transistors used in the RAM.

F Effect By using the equalizing transistor Q3 as an N-channel MOS transistor, carrier mobility is increased and current drive capability is increased. In addition, since the threshold voltage V _TH is lower than that of other N-channel MOS transistors, the drain current can be reduced accordingly.
Increases I _D and increases current drive capability.

As a result of the increased current driving capability of transistor Q3, the equalization period during which the pair of bit lines 12 and 13 are equalized is significantly shortened compared to conventional circuits.

G. Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1, in which parts corresponding to those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, a pair of bit lines 12 and 13
The transistor Q3 provided to equalize the memory cell 10, peripheral circuits such as a circuit provided for an active load of the bit lines 12 and 13, a circuit provided for precharging the bit lines 12 and 13, and a memory An N-channel MOS transistor is used, which has a lower threshold voltage V _TH than other N-channel MOS transistors used in a read amplification circuit or the like that amplifies read data from the cell 10.

For example, a depletion type transistor is applied to transistor Q3, and other N-channel
Applying enhanced type transistors to MOS type transistors.

In this case, since the carrier mobility is higher than that of a P-channel MOS transistor, the current driving ability of the transistor Q3 is increased accordingly, and the equalization period is shortened.

Here, the reason why a transistor having a lower threshold voltage V _TH than other N-channel MOS transistors is used as the transistor Q3 is based on the results of the study shown below.

Generally, in the case of a CMOS configuration, enhanced type transistors having the same threshold voltage V _TH (approximately 1 [V]) are used for a plurality of N-channel MOS transistors to simplify the manufacturing process. When such an N-channel MOS transistor is applied to the equalizing transistor Q3, the voltage difference between the gate-source voltage V _GS of the transistor Q3 and the threshold voltage V _TH cannot be made large, so the following equation is obtained. The drain current I _{D ID} =K(V _GS −V _TH ) ² (1) is small (K is a comparison constant). Therefore, the current drive capability is small, and the N-channel
Even if a MOS type transistor is applied to the equalizing transistor Q3, the equalizing period cannot actually be shortened much.

Therefore, as described above, a transistor with a much smaller threshold voltage V _TH is used as the equalizing transistor Q3, and the drain current is increased to increase the current drive capability and shorten the equalization period.

Incidentally, as transistor Q3, another N channel
If a MOS transistor with a different threshold voltage V _TH is used, a RAM will be manufactured by mixing N-channel MOS transistors with multiple threshold voltages, but such a configuration This can be easily realized by masking the transistor Q3 portion in an ion implantation process performed to adjust the threshold voltage of other N-channel MOS transistors, and the process can be made particularly uncomplicated.

As described above, according to this embodiment, the equalization period can be further shortened compared to the conventional circuit. This means that in the present invention and the conventional circuit, the pair of bit lines 1 after the equalization pulse signals φ _EQ and φ _EQ are applied until the equalization is performed.
This can be confirmed from FIGS. 2 and 3, which show the theoretical calculation results of the potential changes in Nos. 2 and 13. In this operation, the equalizing transistor Q
Channel width W of 3 is 7 [μm], channel length L
1.2 [μm], and the thickness of the gate silicon oxide film is
200 [Å], the capacitance of the pair of bit lines 12 and 13 is
It was calculated as 1.6 [pF]. From this calculation result, when using a conventional P-channel MOS transistor, it takes approximately 11 [ns] from the fall of the pulse signal φ _EQ until both the high and low bit line potentials V _BH and V _BL are equalized. In contrast, in the case of the present invention, it takes about 6 [ns] from the rise of the pulse signal φ _EQ until both bit line potentials V _BH and V _BL are equalized, and the above-mentioned effect is achieved. I was able to confirm that it was obtained.

Furthermore, when a depletion type N-channel MOS transistor is applied to the equalizing transistor Q3, the threshold voltage V _TH becomes -1.
Since it is about -2 [V], the low potential bit line potential can be easily raised to the power supply voltage _VDD , and data can be discriminated without confirmation. Furthermore, the bit line potential on the low potential side never drops below about 1 [V] during operation, and at that potential, the gate of transistor Q3 is in an off state.
V _GS =-1 [V] is applied, and no channel leakage occurs.

H. Effect of the invention As described above, according to the invention, the equalizing transistor is an N-channel MOS transistor with a lower threshold voltage than other N-channel MOS transistors.
Since it is configured with MOS type transistors,
An equalization circuit capable of further shortening the equalization period of a pair of bit lines and thereby shortening the access time can be easily obtained without complicating the manufacturing process.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram showing one embodiment of the equalization circuit according to the present invention, Fig. 2 is a schematic diagram showing how both high and low bit line potentials are equalized by the circuit of Fig. 1, and Fig. 3 is a schematic diagram showing how both high and low bit line potentials are equalized by the circuit of Fig. 1. A schematic diagram showing how the potentials of both bit lines are equalized by the conventional circuit, and FIG. 4 is a connection diagram showing the conventional circuit. 10...Memory cell, 11...Word line, 1
2, 13... Bit line, Q3... Equalizing transistor.

Claims (1)

[Claims for Utility Model Registration] A source terminal and a drain terminal are respectively connected to a pair of bit lines of a RAM having a CMOS configuration,
In an equalization circuit comprising an equalization MOS type transistor that shorts the pair of bit lines and equalizes the pair of bit lines by supplying an equalization pulse signal to a gate terminal, the equalization MOS type transistor is
Other N channels used in the above RAM
An equalization circuit characterized in that it is formed of an N-channel MOS type transistor having a lower threshold voltage than a MOS type transistor.