JPH05250815A - Data demodulator circuit - Google Patents

Abstract

PURPOSE:To prevent demodulation error occuring due to the timing shift of encoding data at the timing of demodulating the encoding data. CONSTITUTION:When the encoding data is resynchronized by a standardizer 3, a phase relation with the output clock 20 of a PLO 1 is varied. Then the demodulation error of NRZ data 13 being the then output of a demodulator 4 is detected by a control circuit 5 and an error rate is calculated and the delay time of a delay circuit 2 is controlled so that the error rate becomes a minimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulation circuit, and more particularly to a coded data demodulation circuit used in a magnetic storage device.

[0002]

2. Description of the Related Art Conventionally, a coded data demodulation circuit used in a magnetic storage device receives a coded data and generates a clock synchronized with the phased oscillator (hereinafter referred to as PL
Abbreviated as O)) and a standardizer for inputting encoded data and the output clock of the PLO to resynchronize the encoded data with the output clock of the PLO, and demodulation for demodulating the original data from the resynchronized encoded data. It was a configuration that included a vessel.

In this conventional data demodulation circuit, a noise component contained in encoded data and a timing shift due to intersymbol interference are absorbed by the PLO and the standardizer, and demodulation is performed with completely synchronized data.

[0004]

In the above conventional data demodulation circuit, since the timing of the encoded data which is the input of the standardizer and the PLO output clock is fixed, the resynchronization is performed depending on the input quality of the encoded data. There is a drawback that an error is likely to occur at the time of. That is, due to the influence of the timing component due to the noise component contained in the encoded data and the intersymbol interference, the encoded data and the P
The phase relationship with the LO output clock is shifted, and there is a high probability that an error will occur.

[0005]

A data demodulating circuit of the present invention includes a PLO for generating a clock synchronized with encoded data, and a standardizer for resynchronizing encoded data with a PLO output clock. A demodulator that demodulates the resynchronized encoded data to the original data, a delay circuit that delays the encoded data and the PLO output clock, and a delay time of the delay circuit while monitoring the error rate of the output data of the demodulator. And a control circuit for controlling.

Further, the control circuit controls the delay time of the delay circuit so that the error rate of the output data of the demodulator becomes the minimum, and stores the storage time when the error rate becomes the minimum. Further, the control circuit further estimates the point where the error rate becomes the minimum from the error rate of each demodulator output data when the delay time of the delay circuit is set to each of the minimum side and the maximum side. The delay time of the delay circuit may be determined.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the present embodiment, as shown in FIG. 1, the output clock 20 of the PLO 1 for generating a clock synchronized with the encoded data 10 and the encoded data 10 are delayed by a delay circuit 2 for a desired time, and the delayed encoded data is delayed. 11 and the delayed clock 21 are input to the standardizer 3.

The standardizer 3 resynchronizes the delayed encoded data 11 with the delayed clock 21, and inputs the synchronized encoded data 12 and the synchronized clock 22 to the demodulator 4.

The demodulator 4 demodulates the synchronized code data 12 and the synchronized clock 22 into original data in accordance with a prescribed conversion rule, and inputs the NRZ data 13 and the bit clock 23 to the control circuit 5.

The control circuit 5 detects an error during data demodulation from the NRZ data 13 and the bit clock 23,
The delay control signal 50 for controlling the delay time of the delay circuit 2 is transmitted while calculating the error rate at that time.

FIG. 2 is a block diagram showing details of the delay circuit 2 of FIG. As shown in FIG. 2, the delay circuit 2 includes a delay line 6 that delays the encoded data 10 for a predetermined time, a delay line 7 that delays the output clock 20, and a selector 8 that selects a delay time by the delay control signal 50. It is composed by.

Next, the coded data 10 includes a timing shift due to noise components and inter-code interference, and
Since 1 generates a clock synchronized with these average phases, each bit of the encoded data 10 and the output clock 20 have a different phase relationship. That is, when the phase relationship between the two shifts by a predetermined time or more (usually for one clock), an error occurs in resynchronization in the standardizer 3 and therefore the NRZ data 13 demodulated by the demodulator 4 is generated.
Is also incorrect.

Normally, the phase relationship between the delayed encoded data 11 and the delayed clock 21 at the input point of the standardizer 3 is such that the edge of the encoded data 11 delayed about halfway between the adjacent edges of the delayed clock 21. Existing. Further, the encoded data 10 includes the timing shift factor as described above, but the positive side and the negative side do not necessarily have the same shift amount, and are often deviated to either side, and thus delayed. The lowest point of the error rate in which the phase relationship between the encoded data 11 and the delayed clock 21 is most desirable is not the case where the delayed edge of the encoded data 11 exists almost in the middle of the adjacent edge of the delayed clock 21. This is a point shifted by the difference between the shift amount on the positive side and the shift amount on the negative side of the encoded data 10.

In this embodiment, the NRZ data 1 output from the demodulator 4 is changed while varying the delay time of the delay circuit 2.
The error rate of 3 is monitored, and the delay time at which the error rate becomes the minimum is set.

In FIG. 2, the phase of the clock 21 delayed with respect to the encoded data 11 delayed by setting the delay time of the delay line 6 to about 1/2 of the total delay time of the delay line 7, It is possible to shift the delay time of the delay line 7 to the positive side and the negative side by about 1/2.

Here, as a method of setting the point at which the error rate becomes the minimum, a method of calculating each error rate by varying the delay time of the delay line 7 from the minimum to the maximum and setting the minimum point from the result is calculated. There is. Since the error rate tends to be high near the minimum or maximum delay time of the delay line 7 and low near the middle of the delay time, the delay line 7 has several points near the minimum and maximum delay times. Alternatively, the delay time may be set by calculating the error rate for each and estimating the lowest point of the error rate from the result.

Further, a storage means is provided inside the control circuit,
The delay time of the delay circuit 2 at the lowest error rate point may be stored. This method is particularly effective in a magnetic storage device and is effective in reducing the error rate. In the magnetic storage device, the electromagnetic conversion characteristics change depending on the address,
The noise component of the encoded data 10 and the timing shift due to intersymbol interference change. Therefore, by setting the lowest error rate point for each address and storing the result in the storage means, the best result can be obtained at any address.

[0019]

As described above, according to the present invention, the error rate is monitored while the resynchronization timing of encoded data is changed, and the error rate minimum point is set.
It is possible to automatically deal with the imbalance of the timing shift of the encoded data, and there is an effect that the error rate is reduced, that is, the reliability of the data is improved.

Further, by providing the storage means, it is possible to absorb the difference due to the address of the magnetic storage device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a delay circuit 2 in FIG.

[Explanation of symbols]

 1 PLO (Phase Synchronized Oscillator) 2 Delay Circuit 3 Standardizer 4 Demodulator 5 Control Circuit 6, 7 Delay Line 8 Selector 10 Coded Data 11 Delayed Coded Data 12 Synchronized Coded Data 13 NRZ Data 20 Output Clock 21 Delayed clock 22 Synchronized clock 23 Bit clock

Claims (3)

[Claims] 1. A phase-locked oscillator for generating a clock synchronized with encoded data, a standardizer for resynchronizing the encoded data with the clock, and resynchronized encoded data as original data. A demodulator that demodulates to
A delay circuit that delays the encoded data and the output clock of the phase-locked oscillator; and a control circuit that controls the delay time of the delay circuit while monitoring the error rate of the output data of the demodulator. Characteristic data demodulation circuit. 2. The control circuit controls the delay time of the delay circuit so that the error rate of the output data of the demodulator is minimized, and stores the delay time when the error rate is minimized. 2. The data demodulation circuit according to claim 1, further comprising storage means for storing the data. 3. The control circuit, based on an error rate of each demodulator output data when the delay time of the delay circuit is set to each of a plurality of points on the minimum side and the re-large side,
3. The data demodulation circuit according to claim 1, wherein the delay time of the delay circuit is determined by estimating the point at which the error rate becomes the minimum.