JPH05250608A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To decrease residual equalization errors to lower an error rate by subjecting only the specific pattern signal in the reproduced signals to be actually used as error information of equalization to averaging in place of removing the noise of the reproduced signals. CONSTITUTION:The information signal, such as video signal, recorded on a tape 1 traveling by being wound around a rotary drum is reproduced by a reproducing head 2 mounted on a rotary drum and is amplified by a preamplifier 3. The reproduced signal outputted from the preamplifier 3 is converted into a digital signal by an A/D converter 4. The signal is then branched to the two signals, a part of which is inputted through a transmission line 5 to an automatic equalizer 13. This signal is introduced through the automatic equalizer 13 and a pattern detecting circuit 14 to a signal output terminal 16. The other part of the reproduced signal outputted from the AD converter 4 is inputted via a delay element 6 to a gate circuit 7. A pattern detection circuit 14 sends the control pulses to the gate circuit 7 and a frequency divider 15 at the time of the detection of the specific pattern in the reproduced signals after the equalization from the automatic equalizer 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus, and more particularly to a magnetic recording / reproducing apparatus having a short convergence time required for waveform equalization and a low error rate.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus of a VTR, particularly a digital recording system such as a digital VTR, an equalizer is generally provided in a reproducing system in order to eliminate intersymbol interference of a reproduced signal waveform. In particular, digital VTRs for broadcasting stations that require high image quality and high reliability are automatically equalized as an equalizer in order to ensure adaptability to changes over time in recording and reproduction and compatibility of magnetic recording media such as tapes. It is desirable to use an automatic equalizer that adjusts the equalization characteristics. Well-known conventional tap coefficient correction algorithms for automatic equalizers include the ZF (Zero-Focing) method and the MSE (Mean Square) method.
Error) method, etc., and is used for automatic equalizers using transversal filters.

In any of the automatic equalizers using these algorithms, the information of the error (equalization error) between the output waveform of the equalizer and the target waveform is used as control information, and the tap coefficient value is successively and repeatedly corrected. To go. This equalization error represents the amount of intersymbol interference included in the output waveform of the equalizer. Specifically, {y _n} of the bit period (T seconds) for each sample value sequence of the output waveform of the equalizer, {a _n} the sample value sequences of interest waveform sample values sequence errors {e _n }, The equalization error is expressed as e _n = y _n −a _n . The tap coefficient value C _k after the k-th correction is the tap coefficient value C after the k−1-th correction.
It is a value updated by a correction value ε made from this error e _n for _k−1 , and is expressed as C _k = C _k−1 + ε.

Incidentally, the reproduced signal waveform in the magnetic recording / reproducing apparatus contains noise in the recording / reproducing system. An automatic equalizer using a linear transversal filter cannot eliminate such noise, but tends to increase it. Therefore, since the output waveform of the equalizer includes noise, the equalization error information used as the control information for updating the tap coefficient also includes noise. By the noise included in this equalization error information,
The probability of accidentally modifying the tap coefficient increases. For this reason, there is a problem that the time required for the residual equalization error to be suppressed to the allowable value or less, that is, the convergence time becomes long. Furthermore, since the residual equalization error amount is disturbed by the influence of noise, the number of errors that occur in the code after identification of the reproduced signal increases.

In order to remove the influence of noise from the equalization error information for correcting the tap coefficient, a method of removing the noise itself of the reproduced signal can be considered, but it is difficult to completely remove the noise, Moreover, a new device is required for that purpose, and the circuit scale of the reproducing system becomes large.

[0006]

As described above, in the conventional magnetic recording / reproducing apparatus, the probability that the tap coefficient is erroneously corrected due to the noise included in the equalization error information in the automatic equalizer increases. As the convergence time increases,
There is a problem that the error rate increases due to the disturbance of the residual interference amount.

Therefore, the present invention provides a magnetic recording / reproducing apparatus which suppresses erroneous correction of the tap coefficient due to noise, has a short convergence time of equalization, has a small residual equalization error, and consequently can achieve a low error rate. The purpose is to

[0008]

In order to solve the above problems, the present invention provides a reproducing head for reproducing a signal recorded on a magnetic recording medium to obtain a reproducing signal, and a reproducing signal obtained by the reproducing head. The averaging means for averaging the noise of the specific pattern signal and the automatic equalizer for equalizing the waveform of the reproduction signal using the specific pattern signal whose noise is averaged by the averaging means as error information. This is a basic feature.

In addition to the basic features described above, the present invention further includes an equalization error detecting means for detecting an equalization error in the output of the automatic equalizer, and a detection signal obtained by the equalization error detecting means. A first control means for controlling the equalization characteristic of the automatic equalizer based on the above, and a first control means for controlling the averaging degree of the averaging means based on the detection signal obtained by the equalization error detecting means. And two control means.

According to one aspect of the present invention, there is provided a variable equalizer as an automatic equalizer, which equalizes a reproduced signal waveform and performs an equalizing operation only when a specific pattern signal in the reproduced signal waveform is detected. Used. In this case, out of the noise included in the reproduced signal, the cause of the adverse effect on the equalization operation such as erroneous correction of the tap coefficient is the same as the fact that the noise included in the specific pattern signal used as the equalization error information has a large effect. Paying attention to the fact that the averaging can be simply performed with the specific pattern signal of, the intermittently arriving specific pattern is retroactively stored a predetermined number of times, and the specific pattern signal arrives. Are used as the input signal waveform of the equalizer by suppressing the turbulence of the amplitude due to the noise of the specific pattern by averaging the specified pattern signal and the target pattern of the specific pattern signal used as the error information of the equalization. Reduce the noise component transmitted to the error. At this time, it is desirable to control the degree of averaging by changing the number of times of averaging in accordance with the value of the equalization error obtained by the equalization error detection means.

[0011]

As described above, by using the specific pattern signal in which the noise is averaged to suppress the variation in the amplitude as the error information input of the automatic equalizer, the variation in the amplitude of the error information due to the noise can be reduced. It is possible to suppress the adverse effect on the activating operation. Therefore, erroneous correction of the tap coefficient due to noise is suppressed without using a new device for noise removal from the reproduced signal, and the convergence time of equalization and the residual equalization error are reduced, resulting in a low error rate. Can be achieved.

In this case, since the noise level in the actual system varies depending on various conditions during recording and reproduction, it is desirable to increase the averaging degree when the noise level is high. For example, if you adjust the degree of averaging by the number of averaging, you can increase the degree of averaging by increasing the number of averaging, but if you simply increase the number of averaging, the time required for processing It will increase. On the contrary, if the number of averaging is too small, the influence of noise on the equalizing operation cannot be suppressed.

Here, since the equalization error in the automatic equalization using the specific pattern signal is the difference between the specific pattern signal and the target pattern signal, noise itself is included, and when the noise level is large, The value of the equalization error is also large, and the value of the equalization error is small when the noise level is low. Focusing on this point, in the present invention, when the equalization error value is large, the noise level is also considered to be large, and the number of times of averaging of the specific pattern is increased, and when the equalization error value is small, the noise level is high. The number of times of averaging is considered to be small and the number of times of averaging is reduced by changing the number of times of averaging according to the value of the equalization error, thereby controlling the appropriate number of times of averaging according to the noise level. As a result, it is possible to avoid an increase in processing time due to unnecessary averaging, and it is also possible to avoid a situation in which the influence of noise on the equalization operation cannot be suppressed because the number of averaging is insufficient.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a portion related to the present invention of a magnetic recording / reproducing apparatus according to a first embodiment of the present invention. In this embodiment, the present invention is a digital VTR.
And a reproducing head 2, a preamplifier 3, an A / D converter 4,
The gate circuit 7, the averaging circuit 8, the gate circuit 12, the automatic equalizer 13, the pattern detection circuit 14, and the frequency divider 15 are included.

In FIG. 1, an information signal such as a video signal recorded on a magnetic recording medium (tape) 1 wound around a rotating drum and traveling is reproduced by a reproducing head 2 mounted on the rotating drum, and is preamplified by a preamplifier 3. Is amplified. The reproduced signal output from the preamplifier 3 is input to the A / D converter 4 and converted into a digital signal.

The reproduced signal output as a digital signal from the A / D converter 4 is branched into two, and a part of the reproduced signal is input to the automatic equalizer 13 through the transmission path 5, and the automatic equalizer 13 and the pattern detection circuit. It is led to the signal output terminal 16 via 14. Another part of the reproduced signal output as a digital signal from the A / D converter 4 is input to the gate circuit 7 via the delay element 6.

The pattern detection circuit 14 sends a control pulse to the gate circuit 7 and the frequency divider 15 when it detects a specific pattern signal in the reproduced signal after equalization from the automatic equalizer 13.
By receiving the control pulse, the gate circuit 7 opens only during the period when the specific pattern signal is input, and guides the specific pattern signal to the averaging circuit 8. Here, if the delay amount of the delay element 6 is set to be equal to the time until the specific pattern signal in the reproduced signal is detected by the pattern detection circuit 14 via the transmission path 5 and the automatic equalizer 13, The specific pattern signal can pass through the gate circuit 7 only when the specific pattern is detected by the pattern detection circuit 14.

The averaging circuit 8 is composed of an amplifier 9, an adder 10 and a memory 11. Gate circuit 7
The specific pattern signal that has passed through is input to the amplifier 9 and its value is set to 1 / n (n is a positive integer). The reproduced signal other than the specific pattern does not pass through the gate circuit 7, but passes only through the transmission path 5. The value of the specific pattern signal whose amplitude has become 1 / n in the amplifier 9 is added to the signal value held in the memory 11 in the adder 10, and this added signal value is stored in the memory 1
Held at 1. The memory 11 is the previously input n-1.
The signal value of the number of times is always held, and the average value of the specific pattern signal of the number of n times is output by adding the signal value of the nth time to the signal value of the number of n-1 times. A specific pattern signal in which the noise component is averaged is obtained by the averaging for n times.

The specific pattern signal whose noise component is averaged by the averaging circuit 8 is input to the automatic equalizer 13 via the gate circuit 12. The gate circuit 12 is controlled by a control pulse generated when the specific pattern signal from the pattern detection circuit 14 is detected. However, the gate circuit 1
2 is closed from the time when the magnetic recording / reproducing apparatus starts reproduction until the first n times of the specific pattern signal is detected,
The gate circuit 12 is not turned on until the frequency divider 15 counts the pulse signals from the pattern detection circuit 14 only for the first n times so that the averaging circuit 8 opens when the averaging is completed n times as described above. Send an open control pulse. At the same time, the frequency divider 15 also sends a control pulse to the automatic equalizer 13 so that the automatic equalizer 13 can pass from the averaging circuit 8 to the gate circuit 12.
The automatic equalization operation is started with respect to the average value of n times of the specific pattern signal input via the.

The frequency divider 15 counts the pulse signal from the pattern detection circuit 14 only for the first n times from the start of reproduction, and thereafter, the pulse signal from the pattern detection circuit 14 is directly used as the gate circuit 12. It is sent to the automatic equalizer 13.

In the case of this embodiment, a signal of a specific pattern existing in the reproduction signal with a certain probability or more, for example, a synchronization signal for frame synchronization during reproduction is previously determined as the specific pattern signal, and the same pattern as this is determined. Is held by the automatic equalizer 13 as a target waveform, and automatic equalization is performed by using the difference from the specific pattern signal as error information of equalization. In this case, of the noise included in the reproduced signal, it is the same as that of the noise included in the specific pattern signal used as the equalization error information, which affects the equalization operation such as erroneous correction of the tap coefficient. Paying attention to the fact that the averaging can be simply performed with the specific pattern signal of, the intermittently arriving specific pattern signal is stored retroactively for a predetermined number of times, and the specific pattern signal arrives. Each time you do it, it averages out a fixed number of times. The noise transmitted to the error between the specific pattern signal used as the equalization error information and the target waveform is used by using the signal whose amplitude disturbance due to the noise of the specific pattern signal is suppressed by this averaging as the input signal waveform of the equalizer. The ingredients are reduced.

As described above, instead of removing the noise of the reproduced signal, by averaging only the specific pattern signal in the reproduced signal actually used as the error information of the equalization, the variation in the amplitude due to the noise is removed, By suppressing erroneous correction of tap coefficient due to noise, shortening convergence time of equalization, and reducing residual equalization error, a low error rate can be achieved as a result.

Next, another embodiment of the present invention will be described. 2 is a block diagram of a magnetic recording / reproducing apparatus according to a second embodiment of the present invention, and the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, the equalization error detection circuit 21 is arranged on the output side of the automatic equalizer 13, and the pattern detection circuit 22 is arranged on the output side of the equalization error detection circuit 21. Further, a gain control circuit 23 for controlling the gain of the tap coefficient of the automatic equalizer 13, a frequency divider 24 for supplying a control pulse to the gate circuit 12 and the gain control circuit 23, an amplifier 9 and a frequency divider 24. There is provided a microcomputer (μCPU) 25 for controlling the.

Next, the operation of this embodiment will be described. An information signal such as a video signal recorded on the magnetic recording medium 1 is reproduced by the reproducing head 2 and passed through the preamplifier 3 to A /
It is converted into a digital signal by the D converter 4. A / D
The reproduction signal output as a digital signal from the converter 4 is branched into two, and a part of the reproduction signal passes through the transmission path 5 to the automatic equalizer 1.
3 is input to the automatic equalizer 13 and the equalization error detection circuit 21.
And it is led to the signal output terminal 16 through the pattern detection circuit 22. Another part of the reproduced signal output as a digital signal from the A / D converter 4 is input to the gate circuit 7 via the delay element 6.

The pattern detection circuit 14 sends a control pulse to the gate circuit 7 and the frequency divider 15 when it detects a specific pattern signal in the reproduced signal after equalization from the automatic equalizer 13.
By receiving the control pulse, the gate circuit 7 opens only during the period when the specific pattern signal is input, and guides the specific pattern signal to the averaging circuit 8.

Here, the pattern amount of the delay amount of the delay element 6 is reproduced by the specific pattern signal in the reproduced signal through the transmission path 5, the automatic equalizer 13 and the equalization error detecting circuit 21.
If it is set to be equal to the time until it is detected, the specific pattern signal can pass through the gate circuit 7 only when the pattern detection circuit 22 detects the specific pattern signal.

The averaging circuit 8 is composed of an amplifier 9, an adder 10 and a memory 11 as in the embodiment of FIG.
By averaging the specific pattern signals for n times, the specific pattern signal in which the noise component is averaged is output. The specific pattern signal whose noise component is averaged by the averaging circuit 8 is input to the automatic equalizer 13 via the gate circuit 12. The gate circuit 12 is controlled by a control pulse generated when the specific pattern from the pattern detection circuit 14 is detected.

However, the gate circuit 12 is closed from the start of reproduction by the magnetic recording / reproducing apparatus until the first n times of the specific pattern signal is detected, and the averaging circuit 8 operates as described above. A control pulse for opening the gate circuit 12 is sent only when the frequency divider 24 counts the pulse signal from the pattern detection circuit 22 only for the first n times so that the frequency is opened when the averaging is completed.

At the same time, the frequency divider 24 has a gain control circuit 23.
Control pulse to the gate circuit 1 of the automatic equalizer 13.
The automatic equalization operation is started with respect to the average value of the signal values of the specific pattern signal input through 2 for n times. Frequency divider 2
4 counts the control pulse from the pattern detection circuit 22 only at the first n times from the start of reproduction, and thereafter, the control pulse from the pattern detection circuit 22 is sent to the gate circuit 12 and the gain control circuit 23 as it is. To do.

On the other hand, the equalization error is detected from the output of the automatic equalizer 13 by the equalization error detection circuit 21 and the target waveform, and the value of the equalization error is detected by the gain control circuit 21 and the μCPU 25. Sent. μCPU25
Using the value of this equalization error, the number of times n of averaging in the averaging circuit 8 is controlled. For example, the μCPU 25 has some candidate values for the number of averaging times n according to the error amount output from the equalization error detection circuit 21 in advance. When the equalization error amount is large, n is also large, and the equalization error amount is large. When n is small, a small value of n is selected and the selected value of n is sent to the amplifier 9 and the frequency divider 24.

The amplifier 9 reduces the amplitude of the specific pattern signal to be input to 1 / n according to the value of n thus supplied from the μCPU 25. The specific pattern for n times is added by the adder 10 until the gate circuit 12 is opened by the frequency divider 24.
Is added in. As described above, in this embodiment, the averaging count n of the specific pattern signal is controlled by the equalization error amount detected by the equalization error detection circuit 23.

Next, another embodiment will be described. In a digital magnetic recording / reproducing apparatus such as a digital VTR or a digital transmission system, it is necessary to adaptively equalize waveform distortion of a signal due to intersymbol interference caused by recording / reproducing characteristics or transmission characteristics. Therefore, for example, in a digital VTR, a waveform equalizer is provided in the reproducing system in order to eliminate intersymbol interference of the reproduced signal waveform. As a waveform equalizer, a digital VTR for a broadcasting station, which is particularly required to have high image quality and high reliability,
Equalization characteristics are automatically adjusted to ensure adaptability to changes in recording / reproduction characteristics over time and compatibility of magnetic recording media.
The use of so-called automatic equalizers is desired. ZF (Zero Forcing) method and MSE (M
The ean square error) method is known, and all of them are used in an automatic equalizer using a transversal filter.

In each of such automatic equalizers, the error between the output signal waveform of the equalizer and the target waveform (this is called equalization error) is used as control information, and the tap gain of the transversal filter is sequentially corrected. Do it. This equalization error corresponds to the intersymbol interference amount of the reproduced signal waveform. In particular,
The output signal waveform of the equalizer, the target waveform, and the sample value series of the equalization error for each bit period T are {Yn} and {an}, respectively.
And {en}, the equalization error is en = yn-an
Is expressed as The tap gain Ck after the k-th correction of the transversal filter is the (k-1) -th tap gain C.
It is a value updated by a correction value ε made from the equalization error en with respect to k-1, and is represented as Ck = Ck-1 + ε.

In an actual system, the reproduced signal waveform is a signal waveform composed of random bit patterns, and the target waveform is often unknown. Therefore, a method of estimating the target waveform from the reproduced signal waveform or using a reproduced waveform of a known pattern such as a sync signal pattern repeatedly included in the reproduced signal as the target waveform is adopted. In the latter method of using the reproduction waveform of the known pattern as the target waveform, the known pattern in the reproduction signal is detected, and the estimated value is obtained by comparing the reproduction signal waveform corresponding to the detected pattern with the target waveform prepared in advance as a reference. Since an accurate equalization error that does not include is obtained, the tap gain converges with a small number of corrections as compared with the former method of estimating the error without using a reference.

By the way, the frequency characteristic of the reproduced signal of the VTR constantly fluctuates due to changes such as spacing loss between the head and the tape. Along with this, the bit error rate of the reproduced signal is constantly changing. In order to eliminate the influence of this fluctuation, the automatic equalizer needs to operate at high speed. However, the known pattern such as the sync signal pattern appears in the reproduced signal only a limited number of times, and the method of obtaining the equalization error information only when all the bits of the known pattern are detected without error causes dropout. When a large number of code errors occur due to fluctuations in frequency characteristics or frequency characteristics, the number of times to obtain equalization error information becomes smaller and smaller. Furthermore, even if the known pattern can be detected, equalization error information cannot be obtained until the known pattern in the next reproduction signal is detected.
There is a problem that it is not possible to follow the fluctuation of the reproduction signal that occurs during that time.

In the following, by solving the above problems and increasing the number of times of acquisition of equalization error information per predetermined time, the convergence time of the equalization characteristic is shortened and the distortion of the reproduced signal that fluctuates at short time intervals is reduced. Third to fifth embodiments relating to a magnetic recording / reproducing apparatus provided with a waveform equalizing circuit that can obtain good adaptive performance will be described.

FIG. 3 is a block diagram showing a third embodiment of the present invention, showing only the structure on the reproducing side. In FIG. 3, the signal recorded on the magnetic recording medium (magnetic tape) 101 is reproduced by the reproducing head 102 and amplified by the preamplifier 103. The reproduction signal output from the preamplifier 103 is input to the variable equalizer 104. The variable equalizer 104 is composed of a transversal filter whose tap gain is controlled by the tap gain control circuit 105, and equalizes the waveform of an input reproduction signal.

The reproduction signal output from the variable equalizer 104 is guided to a terminal 109 connected to a decoder (not shown) and is also input to the pattern detection circuit 106. The pattern detection circuit 106 is a circuit that detects a known pattern from the bit patterns included in the waveform of the input reproduction signal. More specifically, the pattern detection circuit 106 stores the bit pattern of the input reproduced signal waveform in the memory device 107.
If a match is determined by comparing the known pattern stored in advance in bit units with each other, and both patterns match for a predetermined number of bits or more, that is, both patterns match except for a bit error of a predetermined number of bits. Then, the bit pattern is detected as a known pattern.

Then, when the pattern detection circuit 106 detects a known pattern, a known pattern detection signal indicating the fact,
Bit pattern in input reproduction signal waveform and memory device 10
The bit position signal indicating the bit position where the known pattern stored in 7 matches, and the pattern position signal indicating the position of the bit pattern in the reproduced signal waveform are output. The known pattern detection signal, the bit position signal, and the pattern position signal output from the pattern detection circuit 106 are supplied to the tap gain control circuit 105 and the equalization error detection circuit 108.

The equalization error detection circuit 108 includes the variable equalizer 1
The equalization error of the output signal of 04 is detected and an error detection signal is output. This error detection signal is output to the tap gain control circuit 1
It is input to 05. The tap gain control circuit 105 controls the tap gain of the transversal filter in the variable equalizer 104 on the basis of the error detection signal and the reproduction signal output from the preamplifier 103, thereby determining the equalization characteristic of the variable equalizer 104. Control.

The operation of the equalization error detection circuit 108 will be described in more detail. The equalization error detection circuit 108 detects the bit detected by the pattern detection circuit 106 from the reproduction signal output from the waveform equalizer 104 based on the bit position signal and the pattern position signal output from the pattern detection circuit 106. The pattern is detected, and the level difference for each bit between the bit pattern and the known pattern stored in the memory device 107 is obtained.

Specifically, the sample value series for each bit period T of the bit pattern detected by the pattern detection circuit 106 is {yn}, and the sample value series of the known pattern stored in the memory device 107 is {an}. , And the sample value series of the equalization error is {en}, the equalization error is represented by en = yn-an.

Here, the equalization error detection circuit 108 equalizes the sample value yi at the time iT corresponding to the bit that does not match the known pattern among the bit strings forming the bit pattern detected by the pattern detection circuit 106. The error amount ei of the digitization error is obtained by one of the following methods (a) (b) (c).

(A) ei is obtained in the same manner as when the bits match. That is, ei = yi-ai. In this case, the error amount ei includes erroneous reading of bits caused by sudden noise or dropout.

(B) Bits that do not match the known pattern are excluded from the information for obtaining the error amount ei. This is effective when the error amount is obtained after performing the averaging process on the patterns detected several times. (c) The error amount ei is obtained by distinguishing the pseudo patterns.

The method (c) will be described in more detail. When a pattern that can know the time when a pattern appears, such as a synchronous pattern, is set as the known pattern, the pseudo patterns that are very similar to the known pattern among the bit patterns detected by the pattern detection circuit 106 are compared. In order to make it easier, if there is a bit that does not match the known pattern stored in the memory device 107, the evaluation of the error en can be changed depending on whether the pattern is a known pattern or a pseudo pattern. For example, when the pattern detection circuit 106 detects a bit pattern including a bit that does not match the stored known pattern of the memory device 107 as the known pattern, the unmatched bit causes a large signal deterioration and is distorted enough to cause misreading. Means large. Therefore, the equalization error en is obtained in the same manner as above.

On the other hand, when the pattern detection circuit 106 detects a pseudo pattern including a bit that does not match the known pattern stored in the memory device 107, the bit that does not match is caused by the difference between the known pattern and the known pattern. Or bit error due to distortion cannot be distinguished. Therefore, the equalization error en is to give the result of the past equalization error. For example, the same value as the equalization error en obtained for the previously detected pattern is used, or the average value of the equalization error values obtained at the past several times of pattern detection is used.

Next, the operation of the tap gain control circuit 105 will be described in detail. The tap gain control circuit 105 outputs from the variable equalizer 104 based on the bit position signal from the pattern detection circuit 106 and the sequence {en} of the equalization error en obtained by the equalization error detection circuit 108. The bit pattern detected by the pattern detection circuit 106 is detected from the reproduction signal, and the correction amount of the tap gain of the transversal filter in the variable equalizer 104 is calculated. Then, the tap gain is corrected and updated by the calculated correction amount. The above operation is performed every time the pattern detection circuit 106 detects a pattern, and waveform equalization is performed so that the reproduction signal waveform of the known pattern becomes an optimum waveform.

According to this embodiment, the pattern detection circuit 106
By allowing a certain number of bit errors in the known pattern detection judgment in step 1, even if there are many bit errors in the reproduced signal due to dropouts or fluctuations in frequency characteristics, the number of pattern detections must be ensured and The number of detections of the digitization error signal can be made relatively large. As a result, the opportunities for waveform equalization increase, the convergence time of the equalization characteristics (tap gain) is shortened, and good adaptation performance can be obtained even with respect to the distortion of the reproduced signal that fluctuates at short time intervals.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention, which again shows only the structure on the reproducing side.
In this embodiment, the pattern detection circuit 106 is configured to control the tolerance for a bit error that is included in the determination reference when detecting a known pattern according to the error rate of the reproduced signal.

The pattern detection circuit 106 is basically the third circuit.
In the same manner as in the first embodiment, the bit pattern of the input reproduced signal waveform is compared with the known pattern stored in advance in the memory device 107 in bit units to determine a match, and both patterns are set to a predetermined number of bits (n. ) If they match over the above, the bit pattern is detected as a known pattern. In this embodiment, the value of the minimum matching bit number n, which is the criterion for pattern detection in the pattern detection circuit 106, is controlled according to the code error of the reproduced signal.

That is, when the error rate of the reproduced signal is large, it can be determined that the number of tap gain corrections is insufficient.
Equalization accuracy is sacrificed somewhat, and the value of n is made small to increase the tolerance for bit errors. As a result, the number of times the equalization error information is acquired is increased by increasing the number of times of detecting pseudo patterns close to the known pattern. On the contrary, when the error rate of the reproduced signal is small, it can be determined that the number of tap gain corrections is sufficient. Therefore, by increasing the value of n and lowering the tolerance for the bit error rate, the accuracy of the known pattern is reduced. To obtain equalization error information.

Next, the configuration for controlling the minimum matching bit number n as described above will be specifically described. In FIG. 4, the output signal of the variable equalizer 104 guided to the terminal 109 is input to the decoder 110, and the output signal of the decoder 110 is further input to the code error detection / correction circuit 111. Decoded data is obtained at the output of the code error detection / correction circuit 111.

An accumulator 112 is connected to the code error detection / correction circuit 111. The integrator 112 counts the number of times of code error detection / correction of the code error detection / correction circuit 111 per unit time. The count result is input to the pattern detection circuit 106, and n is output according to the count result.
The value of is selected.

With this configuration, the pattern detection circuit 1
An appropriate number of tap gain corrections can be ensured by controlling the tolerance for bit errors, which is included in the determination standard when detecting the known pattern according to 06, according to the error rate of the reproduction signal.

As another embodiment, the variable equalizer 104
Bit error in the judgment standard when detecting a known pattern depending on whether the equalization error amount of the reproduced signal waveform is due to the bit of the bit pattern in the output signal of No. and the bit of the known pattern do not match You may change the tolerance for.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention, in which parts corresponding to those in FIG. 3 are designated by the same reference numerals and only the differences from the embodiment of FIG. 3 are described. In this embodiment, the pattern detection circuit 106 detects a plurality of types of known patterns contained in the reproduced signal output from the variable equalizer 104. Here, among a plurality of types of known patterns detected by the pattern detection circuit 106, at least one type is a pattern that is periodically repeated, such as a synchronization signal pattern, and other known patterns are output from the waveform equalizer 104. An appropriate pattern that is expected to be included in the output reproduction signal is selected. In addition, the memory device 107
In the table, plural types of known patterns to be detected by the pattern detection circuit 106 are stored in advance.

FIG. 6 shows an example of a reproduced signal waveform output from the variable equalizer 104. As shown in (a) of the same figure, the reproduction signal is framed, and each frame is composed of a plurality of blocks in the figure. Each block includes a synchronization signal pattern (SYNC), an information signal (DATA) such as video signal data, and redundant bits for error detection or correction (hereinafter referred to as error detection / sync), as shown in FIG.
It is called a correction code) (ECC). As an example of the data length of each part, for example, in the D-2 format digital VTR, the synchronization signal pattern SYNC is 2
The bytes, the information signal DATA is 85 bytes, and the inner code corresponding to the error detection / correction code ECC is 8 bytes.

The known pattern detected by the pattern detection circuit 106, that is, the known pattern stored in the memory device 107, is a pattern which is periodically repeated.
Several bits in the sync signal pattern SYNC in FIG. 6 are selected, and as other known patterns, several kinds of patterns of several bits that can appear in the information signal DATA are selected. Further, as another known pattern, an error detection / correction code ECC
You may use the pattern of several bits contained in. Figure 6
In (b), the area indicated by the broken line is the pattern detection circuit 10.
It is used as a known pattern detected in 6.

As described above, as the known pattern detected by the pattern detection circuit 106, another pattern is used in combination with the pattern that is periodically generated to secure the number of times of detection of the known pattern per unit time, It is possible to increase the number of times that the digitization error signal is detected. Therefore, as in the previous embodiment, the opportunities for waveform equalization can be increased, the convergence time of the equalization characteristics (tap gain) can be shortened, and good adaptation can be made even to the distortion of the reproduced signal that fluctuates at short time intervals. Performance is obtained.

It is possible to further develop the embodiment shown in FIG. 5 and use a plurality of patterns having different frequency components for at least two kinds out of a plurality of known patterns detected by the pattern detection circuit 106. For example, a suitable pattern expected to be included in a part of the information signal DATA is "111".
When using two types of patterns of "10000" and "11001100", if the fundamental frequency component of the former pattern is f, that of the latter pattern is 2f, and the frequency received by these two types of frequency components is Distortion and phase distortion can be detected respectively.

Therefore, by using a plurality of various patterns for each frequency from among the frequency components of the information signal DATA, the equalization effect can be more appropriately applied to the information signal including the frequency component that needs to be equalized. You can sort. For example, by using a large number of patterns containing frequency components with large deterioration, it becomes possible to more optimally equalize the information signal containing the frequency components. In this example, the known patterns having different frequency components are selected from the information signal DATA, but they may be selected from the synchronization signal pattern SYNC.

As the two types of known patterns having different frequency components, for example, the pattern "110011" out of the patterns "101100111000",
For example, the patterns "111000" may be selected so that the patterns partially overlap each other.

Next, an example of a multi-channel magnetic recording / reproducing apparatus will be described. Conventionally, waveform equalization in a VTR has generally coped with a very fast frequency characteristic variation due to a variation in spacing between a head and a tape, and a temporal change in recording / reproducing characteristics due to wear of a head, and a recording medium (tape). When performing automatic equalization for the purpose of ensuring compatibility when there is a change, a so-called fixed equalizer with fixed equalization characteristics is installed in front of the automatic equalizer. Then, the fixed equalizer removes the distortion of the reproduced signal to some extent, and the automatic equalizer is responsible for only the adaptive equalization operation against the rapid fluctuation of the frequency characteristic and the temporal change of the recording / reproducing characteristic that occurs over a long period of time. Let

However, as typified by the characteristics of the head, in the VTR having multiple channels, the recording / reproducing characteristics of each channel vary, and the desired equalization characteristics differ from channel to channel. Therefore, since a waveform equalization circuit including an automatic equalizer and a fixed equalizer installed in the preceding stage is required for each channel, the amount of hardware increases.

Therefore, the sixth to eleventh embodiments relating to the multi-channel magnetic recording / reproducing apparatus which solves the above problems and is capable of stable waveform equalization without increasing the amount of hardware of the waveform equalization circuit. explain.

FIG. 7 is a block diagram showing the structure of the reproducing side of a multi-channel digital VTR according to the sixth embodiment of the present invention. In the figure, information signals such as video signals recorded on a magnetic recording medium (tape) 201 wound around a rotating drum (not shown) and reproduced are reproduced by reproducing heads 202a to 202n for each channel mounted on the rotating drum. , And is amplified by the preamplifier 203.

The reproduction signal output from the preamplifier 203 is supplied to the first variable equalizer 20 provided for each channel by the first switching circuit 204 controlled by the timing pulse generated from the timing circuit 211.
5a to 205n are selectively distributed as needed, and waveform equalization is performed. The signals waveform-equalized by the variable equalizers 205a to 205n are guided to the input of a decoder (not shown) via the second switching circuit 207 controlled by the timing pulse generated from the timing circuit 211.

On the other hand, in addition to the variable equalizers 205a to 205n provided for each channel, the second variable equalizer 20 is provided.
8. An automatic equalizer common to each channel including the equalization error detection circuit 209 and the arithmetic circuit 210 is provided.
The switching circuits 204 and 207 are the preamplifier 2
The reproduction signals output from 03a to 203n are input to the automatic equalizer by bypassing the waveform equalizers 205a to 205n.

In this automatic equalizer, the variable equalizer 2
The equalization error of the output signal of 08 is detected by the equalization error detection circuit 209, and the arithmetic circuit 210 performs the automatic equalization operation of controlling the equalization characteristic of the variable equalizer 208 based on the detection error.
The control of the equalization characteristics of the variable equalizers 205a to 205n is performed by adjusting the equalization characteristics of the variable equalizer 208 which is adjusted in the process of the automatic equalization operation of the automatic equalizer.
5a to 205n are reflected, so that they are sequentially performed.

Specifically, each time a timing pulse is generated by the timing circuit 211, the switching circuits 204 and 207 cause the variable equalizer 205i (i = a, b, ... N) whose equalization characteristics are controlled. The channel i corresponding to is selected. Therefore, the equalization characteristic of the waveform equalizer 205i of any one channel i is always controlled.

The timing circuit 211 is configured to generate a timing pulse at the time when the synchronizing signal repeatedly included in the reproduced signal is detected a predetermined number of times, and the timing pulse is generated by the switching circuits 204 and 207 and the arithmetic circuit. Supply to 210. Arithmetic circuit 21
When 0 receives a timing pulse, 0 sends a transfer command to the variable equalizer 208. Upon receipt of this transfer command, the variable equalizer 208 receives parameters of its own equalization characteristic, for example, information on the tap gain of the transversal filter forming the variable equalizer 208, for each channel.
Transfer to 05n.

The switching circuits 204 and 207 are
Each time a timing pulse is received from the timing circuit 211, the reproduction signal of each channel is input to the variable equalizer 208 in the automatic equalizer. Then, the equalization error detection circuit 2
The equalization error (distortion) of the output signal of the variable equalizer 208 is detected by 09, and the equalization characteristic of the variable equalizer 208, for example, the tap gain of the transversal filter is corrected and controlled by the arithmetic circuit 210 based on this. It

As a method of detecting the equalization error, a method of obtaining a difference between a reference signal included in the reproduction signal output from the variable equalizer 208 and a reference signal stored in advance, or RWLu
cky "Techniques for Adaptive Equalization of Digita
l Communication Systems ", BSTJ, 45,2, pp.255-286 (196
As shown in 6), it is possible to use a known method such as a method in which the difference between the reproduction signal and the identification reproduction signal obtained by data identification of the reproduction signal is used as the equalization error signal.

The above operation is repeated each time a timing pulse is generated from the timing circuit 211, and the equalization characteristics of the variable equalizers 204a to 205n of each channel are sequentially controlled.

FIG. 8 is a block diagram showing the structure on the reproducing side of a multi-channel digital VTR according to the seventh embodiment of the present invention. In FIG. 8, parts corresponding to those in FIG. 7 are assigned the same reference numerals and only the differences are described. The variable equalizers 205a to 205n and the second switching circuit 2 for each channel are described.
07 and the equalization error detection circuits 206a to 206n are provided.

In this embodiment, the variable equalizer 205 is usually used.
The equalization error of the output signals of a to 205n is detected by the equalization error detection circuits 206a to 206n provided for each channel. These equalization error detection circuits 206a to 206n
The information of the distortion of the reproduced signal of each channel which is the detection result of
It is input to the arithmetic circuit 210. The arithmetic circuit 210 compares the distortion of the reproduced signal of each of these channels with a threshold value, that is, an allowable value of the reproduced signal distortion stored in advance in a memory inside the arithmetic circuit 210.

When there is a channel (i) in which the distortion of the reproduced signal exceeds the threshold value, the arithmetic circuit 210 causes some change in the recording / reproducing characteristics of the channel i, which causes the variable equalizer 205i to change. Equalization of the variable equalizer 205i is performed by determining that the equalization characteristic deviates from the optimum characteristic and transferring the equalization characteristic of the variable equalizer 208 in the automatic equalizer 205i to the variable equalizer 205i. Control characteristics. In this case, in the switching circuits 204 and 207, only the reproduction signal of the channel i does not pass through the variable equalizer 205i,
It is controlled by the arithmetic circuit 210 to pass through the variable equalizer 208 in the automatic equalizer. Therefore, the reproduced signal of channel i is equalized by the variable equalizer 208, and the equalization error detection circuit 2
At 09, the equalization error is detected.

The detected equalization error is input to the arithmetic circuit 210, and based on this, the arithmetic circuit 210 causes the variable equalizer 20 to operate.
8 equalization characteristics, for example, the tap gain of the transversal filter is corrected and controlled. The error detection circuits 206a to
206n and 209 may have the same configuration or different configurations.

In the above operation, the equalization error of the output signal of the variable equalizer 208 detected by the equalization error detection circuit 209 becomes equal to or less than the permissible value of the reproduction signal distortion stored in the memory in the arithmetic circuit 210. Is repeated until. When the equalization error of the output signal of the variable equalizer 208 becomes equal to or less than the allowable value, the arithmetic circuit 21
With 0, the switching circuits 204 and 207 are switched so that the reproduction signal of channel i does not pass through the variable equalizer 208 but passes through the variable equalizer 205i corresponding to channel i. At the same time, the arithmetic circuit 210 operates the variable equalizer 208.
Send a transfer command to. Upon receiving this transfer command, the variable equalizer 208 receives its own equalization characteristic parameter at this time,
For example, information about the tap gain of the transversal filter that constitutes the variable equalizer 208 is provided to the variable equalizer 2 of the channel i.
Transfer to 05i.

In this way, the control of the equalization characteristic of the variable equalizer 205i for channel i is completed. Subsequently, the distortion of the reproduction signal of each channel is monitored by the arithmetic circuit 210, and when there is a channel including distortion exceeding the allowable value, the same equalization characteristic control is performed on the variable equalizer of that channel. ..

FIG. 9 is a block diagram of a multi-channel digital VTR according to the eighth embodiment of the present invention. In FIG. 9, instead of the equalization error detection circuits 206a to 206n provided for each channel in FIG. 8, a code error detection / correction circuit 221 of the data of the reproduction signal output from the variable equalizers 205a to 205n. And an integrator 222 for accumulating the number of code errors / corrections per unit time.

In this case, the arithmetic circuit 210 uses the integrator 222.
The number of code errors / correction times per unit time is compared with the allowable value (called a threshold value) of the number of code errors / correction times stored in advance in the memory inside the arithmetic circuit 210. As a result of this comparison, when there is a channel i including a code error whose code error / correction count exceeds the threshold value, some change occurs in the recording / reproducing characteristics of the channel i, and therefore the equalization of the variable equalizer 205i is performed. It is determined that the characteristic deviates from the optimum characteristic, and thereafter, the variable equalizer 205i is tuned as in the embodiment of FIG.
The equalization characteristic of the variable equalizer 205i is controlled by transferring the equalization characteristic of the variable equalizer 208 in the automatic equalizer. This operation is repeated until the number of code error detections / corrections input from the integrator 222 to the arithmetic circuit 210 becomes equal to or less than the threshold value.

FIG. 10 is a block diagram showing the structure of the reproducing side of a multi-channel digital VTR according to the ninth embodiment of the present invention. In this embodiment, the equalization error detection circuit 209 in the automatic equalizer in the embodiment shown in FIG. 8 is also used as the equalization error detection circuits 206a to 206n provided for each channel. For this purpose, the second switching circuit 20
7 is provided between the variable equalizers 205a to 205n of each channel and the equalization error detection circuits 206a to 206n.

FIG. 11 is a block diagram of a multi-channel digital VTR according to the tenth embodiment of the present invention. This embodiment corresponds to the variable equalizer 20 in the embodiment shown in FIG.
8 and the automatic equalizer composed of the equalization error detection circuit 209 and the arithmetic circuit 210 are replaced with a new arithmetic circuit 230, and the basic algorithm is the same as that of the embodiment of FIG. Therefore, in the present embodiment, similarly to the embodiment shown in FIG. 7, each time the timing circuit 211 generates a timing pulse, the switching circuits 204 and 207 include the variable equalizer 205i to be subjected to equalization characteristic control. The channels are configured to be switched, and the equalization characteristics of the variable equalizer of any channel are always controlled. The arithmetic circuit 230 uses the variable equalizers 205 a to 2 a based on the reproduction signal input via the switching circuit 204.
The equalization error of the output signal of 05n is estimated, and the equalization characteristic of the variable equalizer is controlled by sequentially correcting the tap gain of the transversal filter which constitutes the variable equalizer based on the estimated error.

Instead of actually controlling the tap gain, it is also possible to control the tap gain once by performing a simulation of tap gain correction inside the arithmetic circuit 230.

FIG. 12 is a block diagram showing the structure on the reproducing side of a multi-channel digital VTR according to the eleventh embodiment of the present invention. In this embodiment, the automatic equalizer comprising the variable equalizer 208, the equalization error detection circuit 209 and the arithmetic circuit 210 in the embodiment shown in FIG. 7 is replaced with a new arithmetic circuit 230 as in the embodiment of FIG. The basic algorithm is the same as that of the embodiment shown in FIG.

The arithmetic circuit 230 fetches the detection results of the equalization error detection circuits 206a to 206n of each channel, compares them with the allowable value of the reproduction signal distortion stored in advance in the memory inside the arithmetic circuit 230, and compares them with the allowable value. A channel including the above distortion is determined. When there is a channel i including distortion equal to or more than the allowable value, it is determined that the recording / reproducing characteristic of the channel i changes, and the equalizing characteristic of the variable equalizer 205i deviates from the optimum characteristic. Then, the equalization characteristic of the variable equalizer 205i is controlled.

The control of the equalization characteristic is performed by the transversal filter of the variable equalizer 205i for minimizing the distortion of the reproduction signal based on the distortion value which is the detection result of the equalization error detection circuit 206i. It is realized by calculating the tap gain by the arithmetic circuit 230. For example, similar to the embodiment shown in FIG. 8, the correction amount of the tap gain of the variable equalizer 205i is obtained based on the distortion value from the equalization error detection circuit 206i, and the tap of the variable equalizer 205i is tapped each time. By updating the gain and successively correcting the tap gain until the distortion detected by the equalization error detection circuit 206i becomes equal to or less than the allowable value,
A tap gain that provides the optimum equalization characteristic is required.

In this case, instead of actually correcting the tap gain of the variable equalizer 205i, a similar simulation is performed only inside the arithmetic circuit 230, so that the tap gain of the variable equalizer 205i can be controlled once. It is also possible to finish. After that, the arithmetic circuit 230 outputs the timing to the switching circuits 204 and 207 when the detection result of the equalization error detection circuit 206i becomes equal to or less than the allowable value or the equalization characteristic of the variable equalizer 205i becomes the optimum characteristic. A pulse is sent so that the reproduced signal from the preamplifier 203i is guided to the decoder input through the variable equalizer 205i.

This completes the control of the equalization characteristic of the variable equalizer 205i for channel i. Subsequently, the distortion of the reproduced signal of each channel detected by the equalization error detection circuits 205a to 205n of each channel is monitored by the arithmetic circuit 230, and if there is a channel including a distortion exceeding the allowable range, that channel is changed. The same equalization characteristic control as described above is performed on the equalizer.

According to the sixth to eleventh embodiments described above, since one set of automatic equalizers is common to each channel, a fixed equalizer and an automatic equalizer are conventionally provided for each channel. Compared with the configuration of the multi-channel magnetic recording / reproducing device of
The amount of hardware of the waveform equalization circuit can be significantly reduced.

In the sixth to eleventh embodiments, control of equalization characteristics (tap gain) of the variable equalizers 205a to 205n for each channel is performed by the variable equalizer 208 and the equalization error detection circuit 20.
9 and an arithmetic circuit 210 or an automatic equalizer or an arithmetic circuit 230. In such a configuration,
The tap gain value of the variable equalizer 205i may be used as the initial value of the tap gain of the variable equalizer 208 or the arithmetic circuit 230 during the equalization characteristic control of the variable equalizer 205i. To this end, for example, a signal line between the variable equalizer 208 or the arithmetic circuit 230 and the variable equalizers 205a to 205n is used as a bidirectional transmission line, and when the equalization characteristic control of the variable equalizer 205i is started. The tap gain value of the variable equalizer 205i may be transferred to the variable equalizer 208 or the arithmetic circuit 230. This makes it possible to reduce the time required to control the equalization characteristics, as compared with the case where another value is used as the initial value.

[0095]

As described above, according to the present invention,
Instead of removing the noise of the reproduced signal, by averaging only the specific pattern signal in the reproduced signal that is actually used as error information for equalization, the amplitude variation due to noise is eliminated and the noise is removed from the reproduced signal. Without using a new device for, it is possible to suppress the erroneous correction of the tap coefficient due to noise, shorten the convergence time of equalization, and reduce the residual equalization error. As a result, a low error rate can be achieved.

By changing the number of times of averaging according to the value of the equalization error, it is possible to control the number of times of averaging according to the noise level. As a result, it is possible to avoid an increase in processing time due to unnecessary averaging, and it is also possible to avoid a situation in which the influence of noise on the equalization operation cannot be suppressed because the number of averaging is insufficient.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a magnetic recording / reproducing apparatus according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 6 is a diagram for explaining an example of a reproduced signal waveform according to a fifth embodiment.

FIG. 7 is a block diagram showing a sixth embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 8 is a block diagram showing a seventh embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 9 is a block diagram showing an eighth embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 10 is a block diagram showing a ninth embodiment of the magnetic recording / reproducing apparatus according to the present invention.

FIG. 11 is a block diagram showing a tenth embodiment of a magnetic recording / reproducing apparatus according to the present invention.

FIG. 12 is a block diagram showing an eleventh embodiment of a magnetic recording / reproducing apparatus according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Magnetic recording medium 2 ... Reproducing head 3 ... Preamplifier 4 ... A / D converter 5 ... Transmission path 6 ... Delay element 7 ... Gate circuit 8 ... Averaging circuit 9 ... Amplifier 10 ... Adder 11 ... Memory 12 ... Gate circuit 13 ... Automatic equalizer 14 ... Pattern detection circuit 15 ... Frequency divider 16 ... Signal output terminal 21 ... Equalization error detection circuit 22 ... Pattern detection circuit 23 ... Gain control circuit 24 ... Frequency divider 25 ... μCPU 101 ... Magnetic recording Medium 102 ... Playback head 103 ... Preamplifier 104 ... Variable equalizer 105 ... Tap gain control circuit 106 ... Pattern detection circuit 107 ... Memory device 108 ... Equalization error detection circuit 109 ... Decoder input terminal 110 ... Decoder 111 ... Code error Detection / correction circuit 112 ... Accumulator 201 ... Magnetic recording medium 202a-2
02n ... reproducing head 203a-203n ... preamplifier 204 ... switching circuit 205a-205n ... first variable equalizer 206 ... equalization error detection circuit 208 ... variable equalizer 209 ... equalization error detection circuit 210 ... arithmetic circuit 211 ... Timing circuit 221 ... Code error detection / correction circuit 222 ... Accumulator 230 ... Operation circuit

Claims (5)

[Claims] 1. A reproducing head for reproducing a signal recorded on a magnetic recording medium to obtain a reproduced signal, and averaging means for averaging noise of a specific pattern signal in the reproduced signal obtained by the reproducing head. A magnetic recording / reproducing apparatus comprising: an automatic equalizer that equalizes the waveform of the reproduction signal by using a specific pattern signal whose noise is averaged by the averaging means as error information. 2. A reproducing head for reproducing a signal recorded on a magnetic recording medium to obtain a reproduced signal, and an averaging means for averaging noise of a specific pattern signal in the reproduced signal obtained by the reproducing head. An automatic equalizer that equalizes the waveform of the reproduction signal by using a specific pattern signal whose noise is averaged by the averaging means as error information, and an equalization error that detects an equalization error of the output of the automatic equalizer. Detection means, first control means for controlling the equalization characteristic of the automatic equalizer based on the detection signal obtained by the equalization error detection means, and detection signal obtained by the equalization error detection means And a second control means for controlling the averaging degree of the averaging means based on the above. 3. A recording unit for recording a signal on a magnetic recording medium, a reproducing unit for reproducing a signal recorded on the magnetic recording medium, and a variable equalization characteristic for equalizing a waveform of the signal reproduced by the reproducing unit. Of the variable equalizer means and the bit pattern included in the output signal of the variable equalizer means match the known pattern except for a bit error of a predetermined number of bits, the bit pattern is detected as the known pattern. And a equalization error detection means for detecting an equalization error of the output signal of the variable equalizer from the output signal waveform of the variable equalizer corresponding to the known pattern detected by the pattern detector. A magnetic recording / reproducing apparatus comprising: a control unit that controls the equalization characteristic of the variable equalization unit based on a detection signal obtained by the equalization error detection unit. 4. A recording means for recording a signal on a magnetic recording medium, a reproducing means for reproducing a signal recorded on the magnetic recording medium, and a variable equalization characteristic for equalizing a waveform of the signal reproduced by the reproducing means. Variable equalizer, a pattern detector included in the output signal of the variable equalizer, at least one type of which detects a plurality of types of known patterns that are periodically repeated; and a pattern detector that detects the pattern. An equalization error detection means for detecting an equalization error of the output signal of the variable equalization means from an output signal waveform of the variable equalization means corresponding to a known pattern; and a detection signal obtained by the equalization error detection means. And a control means for controlling the equalization characteristic of the variable equalization means based on the above. 5. Recording means for recording signals of a plurality of channels on a magnetic recording medium, reproducing means for reproducing signals of a plurality of channels recorded on the magnetic recording medium, and corresponding to each of the plurality of channels. A plurality of first variable equalizing means having variable equalization characteristics for equalizing waveforms of the signals of the respective channels reproduced by the reproducing means; and equalization characteristics of a number smaller than the number of the plurality of channels. A variable second variable equalizing means and a signal of each channel reproduced by the reproducing means are selectively input to the first variable equalizing means and the second variable equalizing means at any time. Switching means, equalization error detection means for detecting an equalization error of the output signal of the second variable equalization means from the output signal waveform of the second variable equalization means, and the equalization error detection means. Based on the obtained detection signal And a control means for controlling the equalization characteristic of the second variable equalization means and for controlling the equalization characteristic of the first variable equalization means for equalizing the waveform of the signal of the corresponding channel. A magnetic recording / reproducing apparatus characterized by being provided.