JPH05250410A - Hierarchical symbol correcting system - Google Patents

Abstract

PURPOSE:To provide the hierarchical symbol correcting system which can execute automatically a correction of a hierarchical symbol. CONSTITUTION:In the system constituted of a CPU 1 for executing various control, a memory 2 for storing various information, an instruction input part 3 for inputting various information, and a display part 4 for displaying an editing screen, a hierarchical symbol store part 10 for storing circuit information as a hierarchical symbol is provided in the memory 2. Also, this system is constituted by providing an entry part 20 for displaying the information read out of this hierarchical symbol store part 10 as graphic information on the display part 4, executing editing of addition, deletion, etc., of a pin, and storing its result in the hierarchical symbol store part 10 again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical symbol correction system for correcting a hierarchical symbol in a drawing entry tool.

When a hierarchical symbol is modified during editing of a drawing, there is a demand for a function of checking the spreading range of the hierarchical symbol and automatically replacing all of them with the modified hierarchical symbol.

[0003]

2. Description of the Related Art In the conventional hierarchical symbol correction, when correcting a hierarchical symbol having a module, it is manually searched for the same hierarchical symbol in other modules and replaced one by one. It has become.

[0004]

In the conventional system,
We are taking steps to manually check if the same symbol as the corrected hierarchical symbol is used in other modules and correct it. Therefore, searching for the symbol manually is a difficult task. Therefore,
For the modified hierarchical symbol to be replaced, the system is required to search the spread range so that it can be automatically modified.

The present invention has been made in view of the above problems, and an object thereof is to provide a hierarchical symbol correction system capable of automatically correcting a hierarchical symbol.

[0006]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a CP that performs various controls
U, 2 are memories for storing various information, 3 is an instruction input unit for inputting various information, and 4 is a display unit for displaying an editing screen. Reference numeral 10 denotes a hierarchical symbol storage unit that stores the circuit information provided in the memory 2 as a hierarchical symbol, and 20 causes the display unit 4 to display the information read from the hierarchical symbol storage unit 10 as graphic information to add a pin. , Is an entry section for storing the result again in the hierarchical symbol storage section 10 after editing such as deletion. A control unit 21 controls the operation of the entry unit 20.

[0007]

The function of the entry unit 20 is that of the hierarchical symbol storage unit 10.
Display the hierarchical symbol information read from the display unit 4,
Processing such as pin addition and deletion is automatically performed according to an instruction from the instruction input unit 3. Next, control unit 21 sequentially reads the hierarchical symbols from hierarchical symbol storage unit 10 and checks whether the same hierarchical symbol is included in another portion. The same hierarchical symbol is re-stored in the hierarchical symbol storage unit 10 after the same correction. As described above, according to the present invention, the hierarchical symbols can be automatically corrected, and the processing efficiency can be improved.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a diagram showing an example of the data structure of the entry tool used in the present invention. In the figure, 30 is a system, for example, an LSI. Reference numeral 31 is a plurality of modules that configure the system. Although only one module 31 is shown in the figure, there are a plurality of modules 31.
Each module 31 is composed of common information 32, interface information 33, management information 34, and a plurality of page information 35.

FIG. 3 is a diagram showing an example of the data structure inside the module. In one page information 35, a plurality of hierarchical symbols are interconnected as a hierarchical symbol information table 11 by a link identifier “next”. In the illustrated example, there are three hierarchical symbol information tables 11. The hierarchical symbol information table 11 includes a symbol name,
Pin data, shape data and link identifier "next"
It is composed of

The pin data is linked to the pin information table 12. If there are a plurality of pins in the same hierarchical symbol information table 11, the pin data are interconnected by the link identifier "next". The example shown in the figure shows the case where the number of pin information tables 12 is two. In addition, each pin information table 12 has a pin name,
It is composed of a pin display position, a pin name display position, a pin direction, and a link identifier "next". Among the constituent elements of these pin information tables, the pin display position is linked to the coordinate table 13.

FIG. 4 is a diagram showing a configuration example of a module corresponding to the data structure shown in FIG. Corresponding to FIG. 3, there are only three symbols S1 to S3. Also,
The symbol S1 has only two pins, one for each input and one for each output. The entry unit 20 displays the circuit information as shown in FIG. 4 on the display unit 4 based on the data read from each module 31 of the hierarchical symbol storage unit 10.

FIG. 5 is a flow chart showing the update sequence of the hierarchical symbol information table according to the present invention. The sequence shown in the figure is performed by the control unit 21 in the entry unit 20 based on an instruction from the instruction input unit 3. That is, when a command to delete a symbol pin is issued from the instruction input unit 3, the CPU 1 that has received the deletion command transfers control to the control unit 21, and the control unit 21 performs the operation shown in FIG. become. Further, in this example, assuming that the module has already been determined as a specific module, the case of deleting the pin of the symbol in the module will be described as an example.

First, the control unit 21 searches the hierarchical symbol storage unit 10 in the memory 2 and checks whether the read symbol name is the same as the one designated from the instruction input unit 3 (S1). If they are the same, it is checked whether the pin is added or deleted (S2). If it is an addition, the pages being used are sequentially displayed to perform the addition work (S3). Here, the case where the size of the hierarchical symbol is increased in addition is not considered.

When the pin is deleted, it is checked whether the pin information table 12 is the pin table to be deleted (S4). If it is the table to be deleted, the pin information table is deleted and linked again (S5). FIG. 6 shows an example of relinking. With the hierarchical symbol information table 11 and the # 1 pin information table 12 linked, the # 1 pin information table 12 is linked.
Is deleted, the hierarchical symbol information table 11 and #
The two pin information tables 12 are linked as shown in the figure.

Next, the next pin information table is Null.
It is checked whether it is (0) (S6). If it is not 0, the next table is searched (S7) and step S
Return to 4. If it is 0, it is checked whether the next hierarchical symbol information table 11 is 0 (S8).
If it is not 0, the next table is searched (S9) and the process returns to step S1. Hierarchical symbol information table 11 is 0
In the case of, it is checked whether the next page information table is 0 (S10). If it is not 0, the next table is searched (S11), and the process returns to step S1. If the next page information table is 0, the pin deletion sequence ends. As a result, the corrected hierarchical symbol data is stored again in the hierarchical symbol storage unit 10.

FIG. 7 is a diagram showing a screen display example before correction. Two hierarchical symbols SB1 and SB2 are displayed in one module. Data D input to SB1
ATA0-DATA3 enter SB2 and exit from SB2 as outputs OUT0-OUT3. Here, it is assumed that the hierarchical symbol SB2 is the correction target. Then, as shown in FIG. 8, the correction is to input pin I3 and output pin O3.
Is to be deleted.

This pin deletion sequence is performed in the sequence as shown in FIG. The result of the correction is as shown in FIG. As can be seen from comparison with FIG. 7, the input pin I3 and the output pin O3 of SB2 are deleted.

[0018]

As described above in detail, according to the present invention, it is possible to provide a hierarchical symbol correction system capable of automatically correcting hierarchical symbols.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an example of a data structure of an entry tool used in the present invention.

FIG. 3 is a diagram showing an example of a data structure inside a module.

FIG. 4 is a diagram showing a configuration example of a module.

FIG. 5 is a flowchart showing an update sequence of a hierarchical symbol information table according to the present invention.

FIG. 6 is a diagram showing an example of relinking a pin information table.

FIG. 7 is a diagram showing an example of a screen display before correction.

FIG. 8 is an explanatory diagram of correction.

FIG. 9 is a diagram showing an example of a screen display after correction.

[Explanation of symbols]

 1 CPU 2 Memory 3 Instruction Input Section 4 Display Section 20 Entry Section 21 Control Section

Claims (4)

[Claims] 1. A CPU (1) for performing various controls, a memory (2) for storing various information, an instruction input unit (3) for inputting various information, and a display unit (4) for displaying an editing screen. In the system configured by, the memory (2) is provided with a hierarchical symbol storage section (10) for storing circuit information as a hierarchical symbol, and
The information read out from the hierarchical symbol storage unit (10) is displayed as graphic information on the display unit (4), editing such as addition and deletion of pins is performed, and the result is stored again in the hierarchical symbol storage unit (10). A hierarchical symbol correction system comprising an entry section (20). 2. The entry unit (20), when the correction of the hierarchical symbol is completed, the hierarchical symbol storage unit (1).
2. The hierarchical symbol correction system according to claim 1, wherein 0) is searched for, and the same correction is performed on other portions using the same hierarchical symbol. 3. The hierarchical symbol storage section (10) is configured such that hierarchical symbol information tables existing in the same module are interconnected by a link identifier, and pin data existing in each hierarchical symbol is similarly pinned. 2. The hierarchical symbol correction system according to claim 1, wherein the tables are interconnected by link identifiers. 4. When deleting a specific pin, the pin information table corresponding to that pin is deleted, and the link identifier skips the deleted pin information table and connects the pin information tables of the preceding stage and the succeeding stage. The hierarchical symbol correction system according to claim 3, wherein