JPH05250202A - Test device for information processor - Google Patents

Abstract

PURPOSE:To easily search for the fault of a device to be tested when an error is detected by applying a start-small test method which starts its operation at first with a combination of a small number of instructions and then gradually increases the subject instructions. CONSTITUTION:A tested device 1 is connected to an information processor 2 and consists of a test instruction train generating means 5 including a test execution pass time timer 3 and an instruction group number pointer 4, a test instruction train executing means 7 including a simulator 6, an error detecting means 8 to detect error, an error information output means 9 which outputs the detected error information to the outside, and a storage part 10 which stores the information on all test subject instructions. Then the device 1 divides all test subject instructions into (n) groups to add the group numbers into the information on these instructions and selects a test subject instruction among those instructions having the group numbers following the group number (i) shown by a pointer. Then '1' is added to the number of the number (i) stored in the pointer at each fixed time for generation of a new test instruction train.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for an information processing apparatus, and more particularly to a test apparatus for an information processing apparatus for executing a test by executing a test instruction sequence generated by combining a plurality of instructions with random numbers.

[0002]

2. Description of the Related Art A conventional tester for an information processing apparatus holds information on all test target instructions, and a test command sequence generating means sequentially selects a test from all the test target instructions according to a pseudo random number sequence for testing. The instruction sequence is generated and applied to the device under test, the simulator simulates the instruction operation, and the test instruction sequence generated by the test instruction sequence generation means is executed by the device under test and the simulation result by the simulator. The error was detected by comparing with the error detecting means.

[0003]

The above-described conventional information processing apparatus testing apparatus generates a test instruction sequence by combining a plurality of instructions from all test target instructions by random numbers when generating the test instruction sequence, Because it is carried out by the method to execute,
The instructions that make up the test instruction sequence are all test target instructions.First, it is not a start small test method that starts with a combination of a small number of instructions and gradually increases the target instructions, so assuming the worst condition However, there is a problem in that all the test instructions included in the test instruction sequence when the error is detected may be illegal in operation, which may make it difficult to search for a failure in the device under test.

An object of the present invention is to enable a start small test method in which a combination of a small number of instructions is first started and the number of target instructions is gradually increased, and it is easy to search for a fault in a device under test when an error is detected. It is to provide a test device for an information processing device.

[0005]

A test apparatus for an information processing apparatus according to the present invention holds information of all test target instructions in a storage unit in advance, and a test instruction sequence generating means selects pseudo random numbers from all the test target instructions. The test instruction sequence is sequentially selected according to the sequence to generate the test instruction sequence, the test instruction sequence is applied to the device under test, and the simulator simulates the instruction operation, and the test instruction sequence generated by the test instruction sequence generation means is tested. In a test apparatus of an information processing apparatus for detecting an error by comparing an execution result in the apparatus and a simulation result in the simulator with an error detecting means, all the test target instructions are divided into n groups, and all the test target are tested. A group number from 1 to n, which is different for each test target instruction group, is added to the instruction information, and one group number i among the group numbers 1 to n is held in the test instruction sequence generation means. Poi By providing a timer mechanism for measuring the elapsed time of the test and test execution, a test target instruction is selected from the instructions having a group number less than or equal to the group number i indicated by the pointer to generate a test instruction sequence, and the timer is generated. The configuration is such that a new test instruction sequence is generated by adding 1 to the value of the group number i stored in the pointer every time a predetermined time set by the mechanism elapses.

The test apparatus of the information processing apparatus according to the present invention holds the information of all the test target instructions in the storage unit in advance, and the test instruction sequence generating means sequentially selects the instructions from the all test target instructions according to the pseudo random number sequence. To generate a test instruction sequence, apply the test instruction sequence to the device under test and simulate the instruction operation with a simulator, and execute the test instruction sequence generated by the test instruction sequence generation means on the device under test. In a test apparatus of an information processing apparatus that compares an error detection means with a simulation result by the simulator to detect an error, all the test target instructions are divided into n groups, and each of the test target instructions contains information on each test target. A group number from 1 to n, which is different for each test target instruction group, is added, and a pointer and a test instruction for holding one group number i among the group numbers from 1 to n in the test instruction sequence generation means. By providing a counter mechanism that counts the number of times a column is generated, a test target instruction is selected from instructions having a group number i or less indicated by the pointer to generate a test instruction sequence, and the counter mechanism preliminarily operates. Each time the predetermined number of generations is counted, 1 is added to the value of the group number i stored in the pointer to generate a new test instruction sequence.

In the test apparatus for the information processing apparatus of the present invention, the test instruction sequence generation means always generates the test instruction sequence including the instruction of the group number i which is the group number at the time of error detection after the error detection means detects the error. You may go.

In the test apparatus for the information processing apparatus according to the present invention, the test instruction sequence generating means generates the test instruction sequence after excluding the instruction of the group number i which is the group number at the time of error detection after the error detection means detects the error. You may go.

[0009]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The test apparatus 1 of the present invention is connected to the information processing apparatus 2 and has a test instruction sequence generation means 5 having a test execution elapsed time timer 3 and an instruction group number pointer 4, and a test instruction sequence execution means having a simulator 6. 7, an error detection unit 8 for detecting an error, an error information output unit 9 for outputting the detected error information to the outside, and a storage unit 10 for holding information of all test target instructions.

FIG. 2 is a flow chart showing the basic operation of the test apparatus of the present invention. The names and reference numerals will be described below using those in FIG.

In the test apparatus 1 of the information processing apparatus of the present invention, when the test is started, the test instruction sequence generating means 5 generates a test instruction sequence in step (hereinafter referred to as S) 1 and the test instruction sequence executing means in S2. 7 is on the information processing device 2 and the simulator 6
The error detecting means 8 detects the error by executing the test instruction sequence generated in S1 and comparing the execution results of the same test instruction sequence executed on the information processing device 2 and the simulator 6 in S3. If an error is detected due to a mismatch in execution results, the error information output means 9 outputs the error information in S4 and returns to S1. If an error does not occur in S3, the process immediately returns to S1. The flow is set as one cycle, the above test is repeated until the operator gives an instruction to stop the execution, and the test instruction sequence is recreated by a pseudo-random number each time to be executed to detect the error of the device under test by the combination of various instructions. .. Also, the test execution elapsed time timer 3 is "0".
Further, the instruction group number pointer 4 is initialized to "1" at the start of the test execution, and when the test execution elapsed time timer 4 takes a value exceeding 1 hour, it is determined that the predetermined time has elapsed.

FIG. 3 is a flow chart showing the operation in the test instruction sequence generating means of the first embodiment of the present invention.

When the test instruction sequence generating means 5 enters the test instruction sequence generation operation, it determines in S5 whether or not the addition of all test target instructions has been completed. If not, then in S6 the test execution elapsed time is determined. The timer 3 is checked to determine whether or not the test execution elapsed time has elapsed. If it has elapsed, the instruction group number pointer 4 is incremented by "1" in S7, and the test execution elapsed time timer 3 is initialized in S8. Then, in S9, a test instruction sequence assembling process is performed. In addition, if the addition of all test target instructions has been completed in S5 and the test execution elapsed time timer 3 is set to 1
If the time has not passed, the process immediately jumps to S9 to assemble the test instruction sequence.

FIG. 4 is a flow chart showing the operation of the test instruction sequence assembling process in FIG.

In the test instruction sequence assembling process, a pseudo random number j is generated in S10, and then the group number (test target instruction j) that has just occurred is compared with the value of the instruction group number pointer 4 in S11 to determine the magnitude. .. If the value of the test target instruction j is larger than the value of the instruction group number pointer 4, the pseudo random number j is again determined in S10.
To occur. If the value of the test target instruction j is less than or equal to the value of the command group number pointer 4, the instruction string assembling process of the test target instruction j is performed in S12, and then it is determined in S13 whether the test instruction string assembly is completed. Discrimination processing is in progress.

FIG. 5 shows the storage unit 10 according to the first embodiment of the present invention.
5 is a storage format diagram of data of all test target instruction information stored in FIG.

All test target instruction information in the storage unit 10 has a group number corresponding to each test target instruction group, instruction number data added in descending order, and test target instruction individual information such as an operation code. ing.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIGS. 1, 3 and 4. Those not shown in FIG. 1 are those in FIG.

After the test is started in the test apparatus 1, first, the test instruction sequence generation processing means 5 executes the test instruction for all the test target instructions by the test being executed by the all test target instruction addition end determination processing (FIG. 3: S5). Determine whether it is used for column generation. At this time, since the initial value of the instruction group number pointer 4 is "1", it is determined that the addition of all test target instructions has not been completed, and the test execution elapsed time determination processing (FIG. 3: S6) is performed.
In this test execution elapsed time determination processing, since the test execution elapsed time timer 3 has not reached a value of 1 hour or more, it is determined that the test execution elapsed time timer 3 has not elapsed, and the instruction group number pointer stepping processing (FIG. 3: S7).
Of the test instruction sequence (FIG. 3: S
Execute 9). In this test instruction sequence assembling process, a pseudo random number j is generated by the pseudo random number j generation process (FIG. 4: S10), and the pseudo random number j is associated to select the instruction j to be used for the test instruction sequence, and the group number (test Target instruction j) and instruction group number pointer comparison / discrimination processing (FIG. 4: S1
It is determined whether the instruction j selected in 1) is an instruction having a group number equal to or less than the value stored in the instruction group number pointer 4. When the instruction j is an instruction having a group number larger than the value stored in the instruction group number pointer 4 and it is determined that the test instruction sequence cannot be used, the pseudo random number j generation process (FIG. 4: S10) is performed again. ), The instruction j is an instruction having a group number equal to or less than the value stored in the instruction group number pointer 4, and can be used in test instruction sequence generation (FIG. 3: S5 to S9). If determined, the instruction j is incorporated into the test instruction sequence by the instruction sequence incorporation process of the test target instruction j (FIG. 4: S12), and subsequently the test instruction sequence assembly end determination process (FIG. 4: S13).
Is used to determine the end of test instruction sequence assembly. As a result of the determination by the test instruction sequence assembly completion determination process, if the test instruction sequence assembly is not completed, the pseudo random number j is again generated.
Returning to the generation process (FIG. 4: S10), when it is determined that the test instruction sequence assembly is completed, the test instruction sequence assembly process (FIG. 3: S9) is completed and the execution of the test instruction sequence generation means 5 is completed. The generated test instruction sequence is used as the test instruction sequence execution means 7
The error detection means 8 determines whether or not an error has occurred. The test instruction sequence generation means 5, the test instruction sequence execution means 7, and the error detection means 8 are repeatedly executed until the test execution elapsed time timer 3 reaches a value exceeding 1 hour. As a result of continuous execution, if the test execution exceeds 1 hour and the test execution elapsed time timer 3 exceeds 1 hour, the test execution elapsed time determination process (FIG. 3: S6) determines that
Execution of the instruction group number pointer stepping process (FIG. 3: S7) is selected, and the value of the instruction group number pointer 4 is changed from “1” to “2”.
Advance to. By updating the instruction group number pointer 4, the test target instruction whose value is equal to or less than the updated value of the instruction group number pointer 4 is used in the subsequent test instruction sequence generation,
Instructions to be tested are added.

Instruction group number pointer stepping process (FIG. 3: S
After the instruction group number pointer 4 is updated by 7), the value of the test execution elapsed time timer 3 is initialized by the test execution elapsed time timer initialization processing (FIG. 3: S8), and the continuous execution of the test again exceeds 1 hour. The test target instructions having the group number 2 or less are used to generate the test instruction sequence, and the test instruction sequence is generated by the test instruction sequence assembling process (FIG. 3: S9).

Also in the execution of the subsequent tests, as described above, the instruction group number pointer stepping process after the elapse of a certain time (FIG. 3: S7).
Test target elapsed time timer 3 by test target instruction addition and test execution elapsed time timer initialization process (FIG. 3: S8)
Is performed while initializing. By repeating the above processing, the value stored in the instruction group number pointer 4 is updated to "n", and after all the test target instructions are used for generating the test instruction sequence, all test target instructions are added. According to the determination by the end determination process (FIG. 3: S5), all the test target instructions are used for the test instruction sequence until the operator gives an instruction to suspend the execution without further adding the test target instruction, and the test is performed. Continue to run.

Next, a second embodiment of the present invention will be described with reference to the drawings. However, as compared with the above-described first embodiment of the present invention, only the processing by changing the test execution elapsed time timer to the test instruction string execution frequency counter is different, and therefore only the differences will be described.

FIG. 6 is a block diagram of the second embodiment of the present invention.

The test apparatus 11 of the present invention is the information processing apparatus 2
And a test instruction sequence generation means 15 having a test instruction sequence execution counter 13 and an instruction group number pointer 4.
A test instruction sequence execution means 7 having a simulator 6, an error detection means 8 for detecting an error, an error information output means 9 for outputting the detected error information to the outside, and a storage section 10 for holding information of all test target instructions. Includes and.

It is also assumed that the test instruction sequence execution count counter 13 is initialized to "0", the instruction group number pointer 4 is initialized to "1", and all are initialized at the start of the test execution.

FIG. 7 is a flow chart showing the operation in the test instruction sequence generating means of the second embodiment of the present invention.

When the test instruction sequence generation operation is started, the test instruction sequence generation means 15 determines in S21 whether or not the addition of all test target instructions has been completed, and if not completed, next executes the test instruction sequence in S22. The number-of-times counter 13 is checked to determine whether or not the number of executions of the test instruction sequence has exceeded a predetermined number. If the number has been exceeded, the instruction group number pointer 4 is incremented by "1" in S23, and the test instruction is issued in S24. The column execution frequency counter 13 is initialized, then the test instruction sequence is assembled in S25, and the value of the test instruction sequence execution frequency counter 13 is updated by adding "1" in S26. If all test target instruction additions have been completed in S21 and the test instruction sequence execution count counter 13 does not exceed the predetermined number of test instruction sequence executions in S22, the process immediately jumps to S25. The test instruction sequence is assembled, and the value of the test instruction sequence execution counter 13 is updated by adding "1" in S26.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7. Those not shown in FIG. 6 are those in FIG.

After starting the test in the test apparatus 11, first,
The test instruction sequence generation means 5 determines whether or not the test being executed uses all the test target instructions for the test instruction sequence generation by the all test target instruction addition end determination process (FIG. 7: S21). At this time, since the initial value of the instruction group number pointer 4 is "1", it is determined that the addition of all the test target instructions has not been completed, and the test instruction string execution count determination process (FIG. 7: S22) is performed. Based on the initial value “0” of the test instruction string execution count counter 13, it is determined that the test instruction string is not exceeded, the execution of the instruction group number pointer stepping process (FIG. 7: S23) is avoided, and the test instruction string assembling process (FIG. 7: In S25), only the test target instructions of group number 1 or less among all the test target instructions are combined by random numbers to generate the test instruction sequence. After the test instruction sequence is generated, the test instruction sequence execution counter is incremented by the test instruction sequence execution counter updating process (FIG. 7: S26), and then the test instruction sequence execution means 7 executes the test instruction sequence to detect an error. The means 8 determines whether or not an error has occurred. As described above, the only difference from the first embodiment is that the trigger for adding a test target instruction is not the test execution elapsed time but the number of test instruction sequence generations and executions.

Next, a third embodiment will be described with reference to the drawings. However, the main points of this embodiment are the first and second
In the configuration shown in the second embodiment, the processing for adding the test target instruction added immediately before the detection at the time of error detection to the test instruction sequence is added. Therefore, the description applies to the first embodiment. The explanation will focus on the differences between the cases.

FIG. 8 is a block diagram of the third embodiment of the present invention.

The test apparatus 21 of the present invention is the information processing apparatus 2
Connected to the test instruction string execution number counter 3 and the instruction group number pointer 4, and a test instruction string generating means 25 having an error detection flag 26 for raising a flag when the error detecting means detects an error, and the simulator 6. A test instruction sequence executing means 7, an error detecting means 8 for detecting an error, an error information outputting means 9 for outputting the detected error information to the outside, and a storage section 10 for holding information of all test target instructions. Contains.

FIG. 9 is a flow chart showing the operation in the test instruction sequence generating means of the third embodiment of the present invention.

When the test instruction sequence generating means 25 starts the test instruction sequence generation operation, it determines in S31 whether or not the addition of all the test target instructions has been completed. If not, then in S32 the error detection flag 26 is detected. Is checked to determine whether an error has been detected. If not detected, the test execution elapsed time timer 3 is checked in S33 to determine whether the test execution elapsed time has elapsed. If so, the instruction group number pointer 4 is incremented by “1” in S34, the test execution elapsed time timer 3 is initialized in S35, the test instruction sequence is assembled in S36, and then the error detection flag is generated in S37. 26, it is determined whether or not an error is detected, and if an error is detected, the instruction of the group number i used for assembly in S36 in the subsequent test target instruction sequence generation processing is always included in S38. Test instruction sequence The test subject instruction insertion process to perform. In addition, whether it is determined in S31 that the addition of all test target instructions has been completed first, or whether it is determined in S32 that an error has been detected by checking the error detection flag 26, the test execution elapsed time timer 3 executes the test execution in S33. If it is determined that the elapsed time has not elapsed, the process immediately jumps to S36 and the test instruction sequence assembling process is performed.

With this configuration, the test device does not require a special time-measuring mechanism, and thus the test device can be constructed at low cost.

Next, the operation of the third embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9. Those not shown in FIG. 8 are those in FIG.

In the test instruction sequence generation means 25, the test execution elapsed time timer 3 is set to "0", the instruction group number pointer 4 is set to "1", and all are initialized at the start of the test execution. Time discrimination processing (FIG. 9: S33)
Then, when the test execution elapsed time timer 3 takes a value exceeding 1 hour, it is determined that a predetermined time has elapsed.

After starting the test in the test apparatus 21, first,
The test instruction sequence generation processing means 25 determines whether or not the test being executed uses all the test target instructions for the test instruction sequence generation by the all test target instruction addition end determination process (FIG. 9: S31). At this time, since the initial value of the instruction group number pointer 4 is "1", it is determined that the addition of all test target instructions has not been completed, and then the error detection determination process (FIG. 9: S32) is performed. Since the test execution is started and no error has been detected yet, the error detection flag 26 remains in the “error undetected” state, the judgment is not detected, and the test execution elapsed time judgment process (FIG. 9: S33). Since the test execution elapsed time timer 3 has not exceeded 1 hour, it is determined that the test execution elapsed time timer 3 has not elapsed, the execution of the instruction group number pointer stepping process (FIG. 9: S34) is avoided, and the test instruction sequence assembling process (FIG. 9: S3
According to 6), only the test target instructions up to the group number 1 of all the test target instructions are combined by the random number to generate the test instruction sequence. After the test instruction sequence is generated, the error detection determination process (FIG. 9: S37) is executed again, and if the error detection flag 26 remains in the “error undetected” state as in the previous case, the test target instruction insertion process (FIG. 9: The execution of S38) is avoided.

The generated test instruction sequence is executed by the test instruction sequence execution means 7 after the error detection determination process (FIG. 9: S37), and the error detection means 8 determines whether or not an error has occurred. The test instruction sequence generation means 25, the test instruction sequence execution means 7 and the error detection means 8 are repeatedly executed, and the test execution elapsed time timer 3 exceeds 1 hour.
Alternatively, the process is performed until the error is detected by the error detecting means 8.

As a result of the continuous execution, when the test execution exceeds 1 hour while the error is not detected and the test execution elapsed time timer 3 exceeds 1 hour, the subsequent operation is the same as the above processing flow. Therefore, the description will be omitted, and the case where the error detecting means 8 detects an error when the instruction group number pointer 4 is taking the value "i" will be described below.

When an error is detected by the error detection means 8, the error detection flag 26 in the test instruction sequence generation means 25 is set to the "error detection" state, and after the error information output means 9 is executed, the test instruction sequence generation means 25 is restarted. Run. In the test instruction sequence execution means 25, first, it is determined whether or not all the test instructions are used to generate the test instruction sequence by the all test target instruction addition end determination process (FIG. 9: S31), and in this case, an error is detected. Since the value of the instruction group number pointer 4 at that time is "i", it is determined that the instruction has not ended, and then the error detection determination process (FIG. 9: S32) is executed. Here, since the execution is performed after the error is detected by the error detection means 8 and the error detection flag 26 is set to the "error detection" state, the determination here is different from the previous processing and is determined to be the detection, and further In the instruction group number pointer stepping process (Fig. 9: S34), the instruction group number pointer 4 is not stepped to add the test target instruction, and the test target instruction up to the group number i up to that point is used. Assemble the test instruction sequence. After assembling the test instruction sequence by the test instruction sequence assembling process (FIG. 9: S36),
The error detection determination process (FIG. 9: S37) is executed again, the determination here also becomes an error detection, and the test target instruction insertion process (FIG. 9: S38) is executed, and the group indicated by the instruction group number pointer 4 is executed. The test target instruction of number i is inserted into the test instruction sequence to be assembled in the test instruction sequence assembly process (FIG. 9: S36).

The test instruction insertion by the test target instruction insertion process (FIG. 9: S38) is performed by sequentially adding the instructions in the instruction group number i to the generated test instruction sequence. All the subsequent processing is error detection determination processing (FIG. 9:
By the determination of the error detection in S37), the test target instruction after the group number i is not added, and the test execution sequence by always executing the test instruction sequence including the test target instruction of the group number i is continued. By repeating the generation, all the instructions in the instruction group number i are included in the test instruction sequence. Note that the execution of the test is continued until the operator gives an instruction to interrupt the execution, as in the other embodiments.

Also, when the error detection is performed, for example, when the instruction group number pointer 4 is taking the value "n", the instruction to be tested of the group number i in the above-mentioned embodiment is the group number n.
Other operations are the same except that the instruction to be tested is replaced.

With this configuration, by adopting a means for repeatedly testing the instruction added immediately before that in the test execution after the error detection,
It is possible to execute the test target instruction under various conditions as to what kind of instruction combination causes the error.
This has the effect of facilitating error analysis.

Although the above description is applied to the first embodiment, it can be applied to the second embodiment and the operation is almost the same. Description is omitted to avoid redundancy.

Finally, a fourth embodiment of the present invention will be described with reference to the drawings. However, since only the processing at the time of error detection and the processing after the error detection is different from the third embodiment of the present invention which has already been described, the explanation will be given with an emphasis on the difference.

FIG. 10 is a block diagram of the fourth embodiment of the present invention.

The test apparatus 31 of the present invention is the information processing apparatus 2
Connected to the test instruction string execution number counter 3 and the instruction group number pointer 4, and a test instruction string generating means 35 having an error detection flag 26 for raising a flag when the error detecting means detects an error, and the simulator 6. A test instruction sequence executing means 7, an error detecting means 8 for detecting an error, an error information outputting means 9 for outputting the detected error information to the outside, and a storage section 10 for holding information of all test target instructions. Contains.

FIG. 11 is a flow chart showing the operation in the test instruction sequence generation processing of the fourth embodiment of the present invention.

When the test instruction sequence generation means 35 starts the test instruction sequence generation operation, it determines whether or not the addition of all the test target instructions has been completed in S41, and if not completed, then the error detection flag 26 in S42. Is checked, it is determined whether or not an error is detected, and if detected, the test target instruction deletion processing is performed in S43, the test execution elapsed time timer 3 is initialized in S44, and the test execution progress is performed in S45. The time timer 3 is checked to determine whether or not the test execution elapsed time has elapsed. If the test execution elapsed time has elapsed, the instruction group number pointer 4 is incremented by "1" in S46, and the test execution elapsed time timer 3 is set in S47. Initialization is carried out, and then a test instruction sequence assembling process is performed in S48. If it is determined in S41 that the addition of all test target instructions has been completed, or if it is determined in S45 that the test execution elapsed time timer 3 has not elapsed the test execution elapsed time, immediately S4 is executed.
Step 8 is executed to assemble the test instruction sequence. Also, S42
If the error detection flag 26 is checked and it is determined that no error is detected, the process immediately jumps to S45 to check the test execution elapsed time timer 3 to determine whether the test execution elapsed time has elapsed. The subsequent operation has already been described, and will be omitted.

FIG. 12 is a flow chart showing the operation in the test instruction sequence assembling process of the fourth embodiment of the present invention.

In the test instruction sequence assembling process, a pseudo random number j is generated in S51, and then the group number (test target instruction j) that has just occurred is compared with the value of the instruction group number pointer 4 in S52 to determine the magnitude. .. If the group number of the test target instruction j is larger than the value of the instruction group number pointer 4, the pseudo random number j is generated again in S51. If the group number of the test target instruction j is less than or equal to the value of the command group number pointer 4, the executable flag in the data stored in the storage unit 10 described later is confirmed in S53, and the value of the test target instruction j is the group number. Is selected. If it is selectable, an instruction sequence assembling process of the test target instruction j is performed in S54, and then it is determined in S55 whether the test instruction sequence assembly is completed.

FIG. 13 shows a storage unit 1 according to the fourth embodiment of the present invention.
3 is a storage format diagram of data of all test target instruction information stored in 0. FIG.

All test target instruction information in the storage unit 10 includes a group number corresponding to each test target instruction group, an executable flag indicating a possibility of selection for each group number, and instruction number data added in descending order. And the test target instruction individual information such as an operation code.

Next, the operation of the fourth embodiment of the present invention will be described in detail with reference to FIGS. Those not shown in FIG. 10 are those in FIG.

In the test instruction sequence generation means 35, the test execution elapsed time timer 3 is set to "0", the instruction group number pointer 4 is set to "1", and the error detection flag 26 is set to "error not detected" state. The executability flags of all test target instruction information in the unit 10 are all initialized to "executable" at the start of test execution, and the test execution elapsed time timer 3 is used in the test execution elapsed time determination process (FIG. 11: S45). Is 1
If a value exceeding the time is taken, it is judged that a certain time has passed.

After starting the test in the test apparatus 31, first,
The test instruction sequence generation processing unit 35 determines whether or not the test being executed uses all the test target instructions for the test instruction sequence generation by the all test target instruction addition end determination process (FIG. 11: S41). At this time, since the initial value of the instruction group number pointer 4 is "1", it is determined that the addition of all test target instructions has not been completed, and then the error detection determination process (FIG. 11: S42) is performed. Since the test execution is started and no error has been detected yet, the error detection flag 26 remains in the “error undetected” state, the determination becomes undetected, and the test target instruction deletion process (FIG. 11: S43) is executed. Then, the test execution elapsed time determination process (FIG. 11: S45) is performed. Since the test execution elapsed time timer 3 has not exceeded 1 hour, it is determined that the test execution elapsed time timer 3 has not elapsed, and the instruction group number pointer stepping process (FIG. 11:
By avoiding the execution of S46), the test instruction sequence assembling process (FIG. 11: S48) is used to generate a test instruction sequence by combining only the test subject instructions up to the group number 1 of all the test subject instructions with random numbers.

Test instruction string assembly processing (FIG. 11: S4
For details of 8), as shown in FIG. 12, a pseudo random number j is generated by the pseudo random number j generation process (FIG. 12: S51), and the pseudo random number j is associated with the instruction j to be used for the test instruction sequence. , The group number (test target instruction j) and the instruction group number pointer comparison / discrimination processing (FIG. 12: S52) determine whether the instruction j selected is an instruction having a group number less than or equal to the value of the instruction group number pointer 4, When j is an instruction having a group number larger than the value of the instruction group number pointer 4 and it is determined that the test instruction sequence cannot be used, a pseudo random number j is generated again by the pseudo random number j generation process (FIG. 12: S51). On the other hand, if the instruction j is an instruction having a group number less than or equal to the value of the instruction group number pointer 4 and it is determined that the instruction can be used in the test instruction sequence generation, the executable flag (group number (test pair Instruction j)) determination process (FIG. 12: S5
By 3), it is determined whether the executable flag corresponding to the group number including the instruction j is in the "executable" state. As a result, when the executability flag indicates "unexecutable" and it is determined that the instruction of the corresponding group number cannot be selected in the test instruction sequence generation, the pseudo random number j generation process (FIG. 12: S) is performed again.
51), a pseudo-random number will be generated, but the executable flag at this point indicates the “executable” state and can be selected in the generation of the test instruction sequence, so the instruction sequence incorporation processing of the test target instruction j (see FIG. 12: S54), the instruction j is incorporated into the test instruction sequence, and the test instruction sequence assembly end determination process (FIG. 12: S55) is performed to determine the end of the test instruction sequence assembly. As a result of the discrimination, if the assembly of the test instruction sequence is not completed, the pseudo random number j generation process (see FIG.
2: S51) and if it is determined that the test instruction sequence assembly is completed, the test instruction sequence assembly process (FIG. 11: S48).
The test instruction sequence generation means 35 terminates the execution of the test instruction sequence generation means 35, the test instruction sequence execution means 7 executes the generated test instruction sequence, and the error detection means 8 subsequently determines whether or not an error has occurred.

The execution of the test instruction sequence generation means 35, the test instruction sequence execution means 7 and the error detection means 8 described above is repeated, and the test execution elapsed time timer 3 has a value exceeding 1 hour, or an error is detected. This is carried out until the error is detected by the means 8.

As a result of the continuous execution, the test execution has passed one hour with no error detected, and the test execution elapsed time timer 3 is set to 1
When the time is measured, the processing is the same as the above-described processing flow. Therefore, in the case where the error detection means 8 detects an error while the value of the instruction group number pointer 4 is "i-1". This will be described below.

When the error detection means 8 detects an error, the error detection flag 26 in the test instruction sequence generation means 35 is set to the "error detection" state, and the error information output means 9
After execution of, the test instruction sequence generating means 35 is executed again. In the test instruction sequence execution means 35, first, it is determined whether or not all the test instructions are used to generate the test instruction sequence by the all test target instruction addition end determination process (FIG. 11: S41), and in this case, an error is detected. Since the value of the instruction group number pointer 4 is "i-1", the error detection determination process (FIG. 11: S42) is then executed. Since the execution is performed after the error is detected by the error detection means 8 and the error detection flag 26 is set to the "error detection" state, the determination here is different from the previous processing and is determined as the detection, and the test target Instruction deletion processing (FIG. 11: S43) is executed.

Test target instruction deletion processing (FIG. 11: S43)
Then, the executable flag in all test target instruction information of the group number i-1 indicated by the instruction group number pointer 4 is set to the "unexecutable" state, and the value of the instruction group number pointer 4 is stepped to i. After that, the error detection flag 26 is set to the “error not detected” state, and then the test execution elapsed time timer 3 is initialized to “0” again by the test execution elapsed time timer initialization processing (FIG. 11: S44). As a result of the initialization of the test execution elapsed time timer 3, subsequent test execution elapsed time determination processing (see FIG.
1: The determination by S45) has not been completed and the test target instruction of the group number i or before, but the test target instruction whose executable flag in all the test target instruction information is set to the “executable” state is used. , Test instruction sequence assembly processing (FIG. 11: S
The test instruction sequence is assembled according to 48). All the subsequent processing is performed in the same manner except that the test target instruction whose executable flag in all the test target instruction information is set to the “unexecutable” state is not used. Note that all the test target instructions are used as the test target except for the commands whose instruction group number pointer 4 is "n" and the executable flag in the all test target instruction information is in the "unexecutable" state. As in the previous embodiment, the test execution is continued until the operator gives an instruction to suspend the execution.

With this configuration, when an error is detected, a measure is added to guard the instruction added immediately before that as a test instruction so that it will not be used in the subsequent tests, which causes an error in all the instructions to be tested. There is an effect that it is possible to detect all the instructions having a factor, and it is possible to continuously execute the test without an operator.

[0066]

As described above, according to the present invention, all test target instructions are divided into n groups, and the group number from 1 to n which is different for each test target instruction group in the information of all test target instructions. Is added to the test instruction sequence generation means, a pointer for holding one group number i out of the group numbers 1 to n, a timer mechanism for measuring the elapsed time of the test execution, and a counter for measuring the number of times the test instruction sequence is generated. At least one of the mechanisms is provided, the test target instruction is selected from the instructions having the group number i or less indicated by the pointer to generate the test instruction sequence, and the timer mechanism is used for a predetermined time. Each time it passes, or every time the counter mechanism counts a predetermined number of generations,
A start small test method in which 1 is added to the value of the group number i stored in the pointer to generate a new test instruction sequence, starting from a combination of a small number of instructions and gradually increasing the number of target instructions. This makes it possible to easily search for a fault in the device under test when an error is detected.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flow chart showing the basic operation of the test apparatus of the present invention.

FIG. 3 is a flow chart showing an operation in the test instruction sequence generating means of the first exemplary embodiment of the present invention.

FIG. 4 is a flow chart showing an operation of a test instruction sequence assembling process in FIG.

FIG. 5 is a storage format diagram of data of all test target instruction information stored in the storage unit 10 according to the first embodiment of this invention.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a flow chart showing an operation in the test instruction sequence generating means of the second exemplary embodiment of the present invention.

FIG. 8 is a block diagram of a third embodiment of the present invention.

FIG. 9 is a flowchart showing the operation in the test instruction sequence generating means of the third exemplary embodiment of the present invention.

FIG. 10 is a block diagram of a fourth embodiment of the present invention.

FIG. 11 is a flowchart showing an operation in a test instruction sequence generating process according to the fourth embodiment of the present invention.

FIG. 12 is a flowchart showing an operation in a test instruction sequence assembling process according to the fourth embodiment of the present invention.

FIG. 13 is a storage format diagram of data of all test target instruction information stored in the storage unit 10 according to the fourth embodiment of the present invention.

[Explanation of symbols]

 1, 11, 21, 31 Test apparatus 2 Information processing apparatus 3 Test execution elapsed time timer 4 Instruction group number pointer 5, 15, 25, 35 Test instruction sequence generation means 6 Simulator 7 Test instruction sequence execution means 8 Error detection means 9 Error Information output means 10 Storage unit 13 Test instruction string execution count counter 26 Error detection flag

Claims (4)

[Claims] 1. Information of all test target instructions is held in a storage unit in advance, and a test instruction sequence generation unit sequentially selects an instruction according to a pseudo random number sequence from among all the test target instructions to generate a test instruction sequence, Applying the test instruction sequence to the device under test and simulating the instruction operation by the simulator, and making an error between the execution result of the test instruction sequence generated by the test instruction sequence generation means in the device under test and the simulation result by the simulator. In a test device of an information processing device for comparing with a detection means to detect an error, all the test target instructions are divided into n groups,
A group number from 1 to n, which is different for each test target instruction group, is added to the information of all the test target instructions, and one group number among the group numbers 1 to n is added to the test instruction sequence generation means. By providing a pointer holding i and a timer mechanism for measuring the elapsed time of the test execution, the test target instruction is selected from the instructions having the group number less than or equal to the group number i indicated by the pointer to generate the test instruction sequence. A test apparatus for an information processing apparatus, wherein the test mechanism performs a new test instruction sequence by adding 1 to the value of the group number i stored in the pointer every time a predetermined time has elapsed. 2. The information of all the test target instructions is held in a storage unit in advance, and the test instruction sequence generating means sequentially selects the instructions according to the pseudo random number sequence from the all test target instructions to generate the test instruction sequence, Applying the test instruction sequence to the device under test and simulating the instruction operation by the simulator, and making an error between the execution result of the test instruction sequence generated by the test instruction sequence generation means in the device under test and the simulation result by the simulator. In a test device of an information processing device for comparing with a detection means to detect an error, all the test target instructions are divided into n groups,
A group number from 1 to n, which is different for each test target instruction group, is added to the information of all the test target instructions, and one group number among the group numbers 1 to n is added to the test instruction sequence generation means. By providing a pointer that holds i and a counter mechanism that counts the number of times the test instruction sequence is generated, a test target instruction is selected from the instructions having a group number equal to or smaller than the group number i indicated by the pointer to generate a test instruction sequence. And a new test instruction sequence is generated by adding 1 to the value of the group number i stored in the pointer every time the counter mechanism counts a predetermined number of generations. apparatus. 3. The test instruction sequence generation means always generates the test instruction sequence including the instruction of the group number i which is the group number at the time of error detection after the error detection means detects the error. A test apparatus for the information processing apparatus according to 1 or 2. 4. A group number i which is a group number when an error is detected by the test instruction sequence generation means after the error is detected by the error detection means.
The test apparatus for an information processing apparatus according to claim 1 or 2, wherein the test instruction sequence is generated by excluding the instruction of.