JPH05250011A - Inverse compile method for programmable controller - Google Patents

Abstract

PURPOSE:To attain high speed execution with minimum work memory space by transforming the X coordinate of a physical coordinate system expressed by X and Y coordinates which stipulate the storage region to a logical X coordinate. CONSTITUTION:The commands of main flow such as A, t31, B, t32, D..., etc., are stored at the position of physical S coordinate 0 of a picture element information memory 40 for display. The branched commands such as t41, C, t39, E, t37, G, etc., are written at the position of physical X coordinate 1, 2, 3 in order of branching along with the extension paths of commands branched previously such as 40-1, 40-2, etc. At this time, the logical X coordinate corresponding to the physical X coordinate is reloaded from (1), (FF), (FF), to (2), (1), (FF) and further to (3), (2), (1). When the picture element information which completed the inverse compile is read out of the memory 40, it is read and screen displayed with the physical X coordinate for the Y coordinate and the logical X coordinate in order of (0), (1), (2), (3), that is, the physical X coordinate is order of 0, 3, 2, 1, for the X coordinate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decompile method for a programmable controller.

[0002]

2. Description of the Related Art Conventionally, a programmable controller (hereinafter referred to as a PC) has been widely used as a device for performing a predetermined output control (sequence control) according to various physical quantity information or logical information in the field. ..

This PC programming method allows a user, who has conventionally been distant from both hardware and software with respect to a computer, to easily construct a program without being aware that the PC is a computer. Based on the purpose from the beginning of development, it usually involves a completely different description format from computer programming. Generally, contacts (switches) 6 shown in Fig. 7 (a), which were used in the field before the PC was used
A developed connection diagram of a relay circuit by symbol marks such as 1, 62 and a coil (relay) 63 is used.

In recent years, SFC has been used for programming PCs.
A PC-specific international standard program description format called (Sequencial Function Chart) is often used. This is done by step 64 (steps A'64-1, B'64-2 or C'as shown in FIG. 7B).
64-3) and a transition part 65
The description part called (t1 or t2) is arranged alternately. The step 64 represents each process to be controlled, and the content of work to be performed in the process, that is, a series of controls is described. Further, the transition 65 represents the selection condition of the next subsequent step. If the output value of the result of the logical operation of the program described therein is ON, the next subsequent step is selected, and if it is OFF, it is not selected. To do. The description of the step 64 and the transition 65 is almost the same as the above-mentioned relay circuit diagram shown in FIG.

Then, the user uses the SFC programming device (program loader) and inputs the combination of the graphic information consisting of the relay circuit diagram for each of the steps and transitions by the input keys symbolically representing the contacts and the coils. For example, a program figure (SFC program) having an SFC description as shown in FIG. 8A is created. The created SFC program is converted (compiled) into a PC execution file formed by an intermediate code connecting a machine language (machine code) for the PC to operate as a computer and the SFC program.

[0006] By the way, in general, since the mode of progress of a process at a work site, work procedure, and the like are fluid, a sequence control procedure (a description of programming, that is, an SFC program) often changes. To do. In such a case, in order to confirm whether or not the changed sequence control operates as prescribed, the PC is monitored by displaying the SFC program being processed while the PC is performing a test operation. Also, when debugging an SFC program (searching for and correcting a defective part), the PC execution file is similarly converted (decompiled).
Then, the SFC program of FIG. 8 (a) is displayed on the display device.

Further, even when the PC is actually in operation,
In order to monitor and grasp the situation at the site, the SFC program being processed is displayed in the same manner as above, and the operating state of the sequence circuit is monitored. The dynamic monitor (actual monitor in operation) for such a PC is extremely important and real-time display speed is required.

In this case, the SFC program decompiled from the PC execution file is created as a dot image on a display pixel file composed of a RAM (Random Access Memory), as shown in FIG. It is called and displayed on the screen of the display device. The partition frame shown by the dotted line in FIG. 9B shows the pixel storage area represented by the X and Y coordinates on the display pixel file. For example, the display pixel information of step A ′ is stored in the area of coordinates (0, 0) (X coordinate is 0, Y coordinate is 0), and the pixel information of the transition t1 is coordinates (0, 1) (X coordinate is 0,
The Y coordinate is stored in the area 1).

Conventionally, in the process of creating an SFC program decompiled from the PC execution file as display data (pixel information) in a memory (display pixel file), the pixel information once created in the memory is created. Physical movements were frequent.

For example, the SFC on the memory shown in FIG. 8 (b)
As for the pixel information of the program, as shown in FIG. 9A, first, the pixel information of the steps A ′, B ′, and C ′ respectively has coordinates (0, 0), (0, 2), and ( 1 and 2), and two pieces of transition pixel information related to those steps are stored at coordinates (0, 1) and (1, 1) (the description of the transition will be omitted hereafter).

Next, when the subsequent branch from step B'is read by the PC execution file, the display data (pixel information) of step C'which is branched from the main flow first is displayed at the coordinates (1, 2). The area is moved to the area of coordinates (2, 2) as shown in FIG. Then, the same figure
As shown in (c), step D'which branches from step B'is stored in the area of coordinates (0, 4), and step E'which branches from step B'is also stored at coordinates (1,
Store in area 4).

Next, when the branch after the step D'is read out, the pixel information of the step C'and the step E'branched in the previous step is also converted into the coordinates (2, 2) and (1,
4), again as shown in FIG. 10A, to the regions of coordinates (3, 2) and (2, 4), respectively.

Then, as shown in FIG. 3B, step F'and step G'which branch from step D'are stored in the areas of coordinates (0, 6) and (1, 6), respectively.
Following FIG. 2B, steps H ′, I ′, and J ′ are coordinates (0, 8), (0, 1) as shown in FIG.
0) and (0, 12) are stored in the respective regions, and the branch end of each branched step is read out, and pixel information indicating that they are sequentially merged with the main step is coordinate (0, 7), (1,7), (2,5) to (2,9),
(0, 9), (1, 9), (3, 3) to (3, 11),
And (0, 11) to (2, 11)).

Thus, in decompiling an SFC program, every time a step branch is read,
The pixel information in the memory shown in FIGS. 9 (b) and 10 (a) is sequentially moved to complete the pixel information of the display SFC program shown in FIG. 8 (b) on the memory. This is then displayed on the screen.

[0015]

However, in the above-mentioned conventional method, there is a problem that the frequent movement of the pixel information causes a time loss, the program / debug takes too much time, and the debug efficiency decreases. there were.

Further, in a test run or a dynamic monitor during actual operation, which requires a high decompilation speed, there is a risk that the monitor display may not follow the PC operating speed.

In addition, the work memory space for temporarily saving the pixel information to be moved may require a memory space equivalent to all the data for display at the maximum, and thus a program with a limited memory space. There was also a problem that it could not be handled in the case of a loader.

The present invention has been made in view of the above conventional circumstances, and an object thereof is to provide a decompile method for a programmable controller which can be executed at high speed and using a minimum work memory space. It is to be realized.

[0019]

The means of the present invention are as follows (see the principle block diagram of the present invention in FIG. 1). The storage means 1 converts the command information read from the command file of the programmable controller into SFC program graphic information and stores it.

The conversion means 2 is an X-axis of a physical coordinate system represented by X-coordinates and Y-coordinates defining the storage area of the storage means 1.
Convert coordinates to logical X coordinates. Conversion by the same means
For example, as described in claim 2, the physical coordinate system of the storage area of the storage means 1 is divided into blocks for each predetermined area, and the physical X coordinate is converted into the logical X coordinate for each block.

The display means 3 reads the SFC program graphic information from the storage area of the storage means 1 line-sequentially based on the values of the X and Y coordinates and displays it on the screen. The control unit 4 controls the display unit 3 to sequentially read the X-coordinates of the SFC program graphic information read line-sequentially from the storage area of the storage unit 1 based on the logical X-coordinates converted by the conversion unit 2.

[0022]

The operation of the means of the present invention is as follows. When the command information read from the command file of the programmable controller is converted into SFC program graphic information and stored in the storage means 1, the physical coordinate system defined by the X coordinate and the Y coordinate defining the storage area is The conversion unit 2 forms, for example, a predetermined area into blocks, and the physical X coordinates are converted into logical X coordinates for each block. When the display means 3 reads the SFC program graphic information line-sequentially based on the values of the X coordinate and the Y coordinate and displays it on the screen, the control means 4 sequentially reads it based on the converted logical X coordinates. Is controlled as follows.

This makes it possible to realize a decompile method for a programmable controller which can be executed at high speed using a minimum work memory space.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 2A and 2B are diagrams showing an example of the data configuration of the array buffer 20 that manages the physical X coordinate system on the memory in association with the logical X coordinate system calculated by calculation.

In FIGS. 2A and 2B, the array buffer 20
Are four array data parts 20-0, 20-1, 20-2.
And 20-3. Each array data section 20-i (i =
0, 1, 2 or 3) has a physical coordinate part 20-a and a logical coordinate part 20-b.

A representative value of the physical X coordinate area is stored in the physical coordinate section 20-a. In the present embodiment, the physical coordinate parts 20-a of the array data parts 20-0, 20-1, 20-2 and 20-3 respectively have representative values "0", "1", ""2" and "3" are stored.

In the logical coordinate section 20-b, the physical X
The representative value of the logical X coordinate area corresponding to the coordinate area is stored at any time. Figure (a) shows the state at the time of initial setting.
In the logical coordinate section 20-b of the array data section 20-0, the representative value "0" of the logical X coordinate area corresponds to the representative value "0" of the physical X coordinate area of the physical coordinate section 20-a. Is stored,
In the logical coordinate parts 20-b of the other array data parts 20-1, 20-2, and 20-3, for example, "FF" indicating unused is stored.

The coordinate area represented by each of the above representative values is an area made up of a plurality of continuous coordinate values, and the Y coordinate area described later also conforms to this. Hereinafter, the representative value of the physical X coordinate area and the representative value of the logical X coordinate area described above are simply referred to as the physical X coordinate and the logical X coordinate, respectively.

In the same figure (b), the display data (pixel information) of the physical X coordinate "1" on the memory is converted into the physical X coordinate "2".
When it is necessary to move the pixel information to the memory, the actual physical movement of the pixel information in the memory is not performed, but instead, the physical coordinate portion of the array data portion 20-1 in which the physical X coordinate “1” is stored is stored. 20-b shows a state in which the logical X coordinate "2" is stored. Then, after the pixel information is originally moved to the physical X coordinate “2”, new pixel information that should be stored in the physical X coordinate “1” where the pixel information becomes blank due to the movement is the next physical information in the memory. A physical coordinate unit 20-a stored in the X coordinate "2" and in which the physical X coordinate "2" is stored.
Logical coordinate part 20-b of the array data part 20-2 corresponding to
Shows a state in which the logical X coordinate "1" is stored.

Here, the above-mentioned SFC program and PC
Execution file (intermediate code instruction file of program)
Will be described. FIG. 3 (a) shows an example of the SFC program, and FIG. 3 (b) shows a PC executable file converted (compiled) from the SFC program shown in FIG. 3 (a).

In FIG. 6B, the instructions of the compiled intermediate code are declared at the addresses FA00 to FA41 of the PC execution file. That is, since the beginning step A of the SFC program shown in FIG. 9A is branched, FA00, which is the beginning address of the PC executable file shown in FIG. 7B, declares a "branch start block". ing. Subsequently, at address FA01, "from A" indicating that the branch is a branch from step A is declared, and at the next address FA02, "t31" indicating that one route of the branch passes through transition t31. Via'is declared. And the next address FA
In 03, "to B" indicating that step B comes after the transition t31 is declared. Further, at the next address FA04, "via t41" indicating that the other branching route goes through the transition t41 is declared, and at the subsequent address FA05, it is shown that step C comes after the above transition t41. "C
“To” is declared, and at the next address FA06, “block end” indicating that the declaration of the branch start block is finished is declared.

Even in the branch from the main step B to the step D and the step E of the SFC program shown in FIG.
It is declared in A13 as above. Further, for the branch from the next step D to step F and step G, the addresses FA14 to FA20 are similarly declared.

Step G merges into the flow from step F to step H of the SFC program, and the branch of step G is completed. For this, at the address FA21 of the PC execution file, a "branch end block" is declared, which indicates that the steps whose branches have ended merge. Then, at the next address FA22, "from F" indicating that one of the joining steps is the step F is declared, and at the next address FA23, it is shown that the joining from the above step F goes through the transition t34. via t34 ”is declared. Further, at the next address FA24, "from G" indicating that the other merging step is the step G is declared, and at the next address FA25, "t38" indicating that the step G merges via the transition t38. Via "is declared. And the next address F
At A26, "to H" indicating that the merge destination of the above two steps is step H is declared, and the following address FA
At "27", "block end" indicating that the branch end block has been declared is declared.

Similarly, regarding the merging to the step I by the step H following the SFC program and the step E previously branched, the address FA28-
FA34 is also declared, and the subsequent step I and the merging to step J by the previously branched step C are similarly declared at the addresses FA35 to FA41.

Next, referring to FIG.
FIG. 4 (a) shows an operation of decompilation in which the PC execution file shown in FIG. 3 (b) is inversely converted into the SFC program shown in FIG. 3 (a) by using the array buffer 20 shown in FIGS. 4 (a) and 4 (a). , (b) and FIGS. 5 (a) and 5 (b).

The display data memory 40 is used in this process. This display data memory 40
Is the physical position on the memory, the horizontal direction is the X coordinate "0"
~ "3", 4x13 XY coordinate area (hereinafter simply referred to as coordinates) represented by Y coordinates "0" to "12" in the vertical direction.
Has a pixel information storage area.

In FIG. 4 (a), first, the instruction of the addresses FA "00" to "06" of the PC execution file (FIG. 3 (b)).
Is analyzed, and as a result of the analysis, the step A of the inversely transformed (inverse compiling) SFC program is stored in the coordinate (0, 0), and the transition t31 and a part of the branch route 40-1 are coordinate ( 0, 1), the transition t41 and the rest of the branch path 40-1 are stored at coordinates (1, 1), and steps B and C are set at coordinates (0, 2) and (1, 2), respectively. It is stored (all are shown with diagonal lines).

As described above, the main steps A and B are stored at the position of the physical X coordinate "0", and the step C branched from the main step is the physical X coordinate "1" adjacent to the right of the physical X coordinate "0". Is stored in the position.

In the above process, since the pixel information is not moved, the physical X coordinates "0" and "1" in which the pixel information of the logical coordinate part 20-b of the array buffer 20 is stored during this period.
The logical X coordinate values corresponding to are also "0" and "1".
(In FIG. 4 (a), the logical X coordinate is shown in parentheses. The same applies to the following drawings).

Next, the address FA of the PC execution file
When the instructions of "07" to "13" are analyzed and the branch from the main step B is determined, originally, in order to store the pixel information of the branching step in the position of the physical X coordinate "1". , The branch of the previously branched step C is not completed, and the pixel information of the step C and the transition t41 and the remaining portion of the branch path 40-1 are stored as physical coordinates (1, 2) and (1, From 1), move to the physical coordinates (2,2) and (2,1) on the right side, and move to physical X
It becomes necessary to clear the position of the coordinate "1".

At this time, as shown in FIG. 7B, the pixel information of the step C and the transition t41 and the remaining part of the branch path 40-1 is not moved on the memory, but instead its physical coordinates (1, 2) are used. ) And (1, 1), the logical X coordinate corresponding to the physical X coordinate "1" is set to "2". Next, the physical coordinates (2, 0) to (2,
The logical X coordinate corresponding to the physical X coordinate “2” of 12) is set to “1”. The main step D branched from step B, the transition t32, and the branch path 4
A part of 0-2 is stored in the physical coordinates (0, 4) and (0, 3), respectively, and the step E and the transition t39 branching from the step B and the rest of the branching route 40-2 are respectively described above. The pixel information is stored in the physical coordinates (2, 4) and (2, 3) which have not been stored,
Further, the extension of the branch route 40-1 of step C described above is stored in the physical coordinates (2, 1) (both are shaded).

As described above, at this point, the step E, the transition t39, etc. which should be originally stored at the position of the physical X coordinate "1" are the physical X for which the pixel information is not stored.
It is stored at the position of the coordinate “2” and the corresponding logical X coordinate is set to “1”. Further, regarding the pixel information already stored, only the logical X coordinate of the related array buffer 20 is reset, and the pixel information is not actually moved in the memory.

Subsequently, when the instruction of the addresses FA "14" to "20" of the next PC execution file is analyzed and the branch from the main step D is discriminated again, in this case also, the step that originally branches is executed. In order to store the pixel information of step C at the position of the physical X coordinate "1", the branch of step C and step E that have branched previously has not been completed, so those steps C and E, transitions t41 and t3.
9. Move the pixel information of the remaining part of the branch path 40-1 and the remaining part of 40-2, etc. from the physical coordinates in which they are stored to the physical coordinate on the right, and clear the position of the physical X coordinate “1”. The need arises.

Also in this case, as shown in FIG. 5 (a), pixel information such as steps C and E, transitions t41 and t39, the remaining part of the branch path 40-1 and the remaining part of 40-2, etc. is moved in the memory. Instead, the logical X coordinates "2" and "1" (see FIG. 4 (b)) corresponding to the physical X coordinates "1" and "2" where the pixel information is stored are changed to "1".
Increment to "3" and "2". This completes the movement of the pixel information on the logical X coordinate.

Next, the logical X coordinate corresponding to the physical X coordinate "3" of the physical coordinates (3,0) to (3,12) in which the pixel information is not stored is set to "1". Then, the main step F branched from step D, the transition t34, and a part of the branch path 40-3 are stored in the physical coordinates (0, 6) and (0, 5), respectively, and the step branched from step D is also performed. G, the transition t37, and the rest of the branch path 40-3 are stored in the physical coordinates (3, 6) and (3, 5) in which the pixel information has not been stored, respectively, and further, the branch of step C described above. The new extension of path 40-1 is at physical coordinates (3, 1),
The extension of the branch route 40-2 of step E is stored in the physical coordinates (3, 3) (all are shown by hatching).

As described above, the step G and the transition t which should originally be stored at the position of the physical X coordinate "1".
37 and the like are stored in the position of the physical X coordinate "3" in which pixel information is not stored, and the corresponding logical X coordinate is set to "1". Then, for the pixel information already stored, the logical X coordinate of the related array buffer 20 is only incremented by "1" and reset, and the pixel information is not actually moved in the memory. ..

After that, the instructions of the addresses FA "21" to "41" of the PC execution file are further analyzed, and the result is shown in FIG. 5 (b).
As shown in, the main steps H, I, and J are stored in the physical coordinates (0, 8), (0, 10), and (0, 12), and their transitions and branch / merging paths are stored in the physical coordinates (0. , 7), (0, 9), and (0, 11) are stored in the physical coordinates (1, 3) to (1, 11) ( 2,
5) to (2, 9), (2, 11), (3, 7), (3,
9) and (3, 11), respectively (indicated by diagonal lines).

In FIG. 6A, the pixel information completed on the memory is reproduced again with the hatched display removed. in this way,
"0", "3", "2" and "1" are set in the logical X coordinates corresponding to the physical X coordinates "0", "1", "2" and "3".

When this pixel information is read from the memory for screen display, the Y coordinate is read as it is as the physical Y coordinate, as shown in FIG.
Regarding the X coordinate, "0" based on the logical X coordinate,
“1”, “2”, and “3” are sequentially read. Therefore, the pixel information on the memory is read out in the order of physical X coordinates "0", "3", "2" and "1" corresponding to the logical X coordinates and displayed on the screen.

As described above, in the present embodiment, in the process of storing the pixel information in the display data memory 40, the previously stored pixel information is not moved and the logical X coordinate of the array buffer 20 is simply set. Only by changing the value, new branch information can be stored in a new memory area, and the same screen display as if the pixel information was moved on the memory can be displayed.

[0051]

As described above, according to the present invention, the physical movement of pixel information on the memory can be eliminated, and decompilation can be performed at high speed and using the minimum work memory space. Since the time loss due to the frequent movement of pixel information is eliminated, the efficiency of program / debug is improved. Further, since the monitor display that follows the operating speed of the PC can be performed by high-speed decompilation, real-time dynamic monitoring can be performed during the trial run or actual operation of the PC, and the efficiency of work management work is improved. Also,
Since the work memory space for temporarily saving the pixel information to be moved is unnecessary, a program loader having a limited memory space can also be used, so that cost performance is improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

2A and 2B are diagrams showing an example of a data configuration of an array buffer.

FIG. 3A is a diagram showing an example of an SFC program, and FIG.
FIG. 6 is a diagram showing a PC execution file compiled from an SFC program.

4A and 4B are diagrams illustrating an operation of decompiling a PC executable file into an SFC program.

5A and 5B are diagrams illustrating an operation of decompiling a PC executable file into an SFC program.

6A is a diagram showing pixel information completed on a memory, and FIG. 6B is a diagram explaining a state in which the pixel information on the memory is read out to a display screen.

7A is a developed connection diagram of a relay circuit by a symbol mark, and FIG. 7B is a diagram illustrating an SFC program description format.

8A is a diagram showing a screen display example of a conventional SFC program, and FIG. 8B is a diagram showing a configuration of display data on a conventional memory.

9A, 9B, and 9C are diagrams for explaining movement performed on pixel information on a conventional memory.

FIGS. 10A, 10B, and 10C are diagrams for explaining movement performed for pixel information on a conventional memory.

[Explanation of symbols]

 20 array buffer 20-0 to 20-3 array data part 20-a physical X coordinate part 20-b logical X coordinate part A to J steps t31 to t42 transition

Claims (2)

[Claims] 1. A storage means (1) for converting command information read from a command file of a programmable controller into SFC program graphic information and storing the same, and X-coordinates and Y-coordinates defining a storage area of the storage means (1). A conversion means (2) for converting the X coordinate of the physical coordinate system represented by to a logical X coordinate, and the SFC program graphic information from the storage area of the storage means (1) based on the values of the X coordinate and the Y coordinate. Display means (3) for line-sequentially reading and displaying on the screen, and the X-coordinate of the SFC program graphic information which the display means (3) reads line-sequentially from the storage area of the storage means (1) by the conversion means ( 2. A decompilation method for a programmable controller, comprising: a control means (4) for controlling the sequential reading based on the logical X coordinate converted by 2). 2. The conversion means (2) includes the storage means (1).
2. The decompile method for a programmable controller according to claim 1, wherein the physical coordinate system of the storage area is divided into blocks for each predetermined area, and the physical X coordinate is converted into a logical X coordinate for each block.