JPH05249150A - Abnormal voltage monitoring system - Google Patents

Abstract

PURPOSE:To achieve monitoring for an allowable range which is determined by a level in reference to a reference voltage and a width for a time base. CONSTITUTION:An input signal S which is level-converted by a level converter 1 is sampled by a sampling clock CL1 using a sample/hold circuit 2 and is coded by an A/D converter 4. A code comparison operator 5 compares a code from the A/D converter 4 with that of a criterion value for judging whether a voltage of the input signal S is normal or not and outputting an alarm when the failure criterion continues for a predetermined number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal voltage monitoring system for power supply voltage and signal voltage.

[0002]

2. Description of the Related Art A conventional abnormal voltage monitoring system is composed of a comparator circuit, and the comparator circuit is adapted to judge whether the voltage to be monitored is higher or lower than a certain reference voltage.

[0003]

By the way, the permissible range of the monitored voltage is often set to include not only the voltage width but also the time exceeding the permissible voltage width. However, in the above-described conventional abnormal voltage monitoring method, only the voltage to be monitored is compared with the reference voltage in terms of direct current, and the time determination function cannot be arbitrarily provided as required.

An object of the present invention is to provide an abnormal voltage monitoring system capable of monitoring an allowable range determined by the height of a reference voltage and the width of a time axis.

[0005]

SUMMARY OF THE INVENTION An abnormal voltage monitoring system of the present invention comprises a sampling means for sampling a voltage to be monitored with a sampling signal having a predetermined cycle, and an output voltage of the sampling means having the predetermined cycle. And a determination means for determining whether or not the predetermined range has been exceeded continuously for a predetermined number of times.

Further, the abnormal voltage monitoring system of the present invention includes a plurality of the sampling means which operate with the sampling signals having mutually different phases, and one of the judging means outputs the output voltage of the sampling means. It may be configured to determine each voltage in synchronization with each sampling phase.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart of the operation of the embodiment shown in FIG.

First, the input signal S to be monitored is input to the level converter 1 of FIG. The level converter 1 uses the input signal S
This is to match the change range of the above with the dynamic range of the A / D converter 4. The voltage level-converted by the level converter 1 is periodically sampled by the sampling and holding circuit 2 at the timing of the sampling clock CL1 from the clock generation circuit 3 and held for a certain period of time. This signal is encoded by the A / D converter 4 into a binary code. For example, a 4-bit A / D converter outputs 4-bit information.

Next, this information is compared by the sign comparison calculator 5 with the judgment reference bit information which is logically obtained in advance, and it is judged whether or not it is within the allowable range in the high and low directions.
Subsequent to the determination of the elevation direction, the determination of the time axis is performed. As illustrated in the output of the sampling and holding circuit 2 in FIG. 2, only when the sampled voltage is outside the range of the judgment criterion continuously for two times or more with the timings 21 and 22.
An alarm is issued from the sign comparison calculator 5. In other words, the determination on the time axis does not generate an alarm unless an abnormal voltage is found twice or more consecutively in the sampling cycle. Although the spike noise 23 is present in the input voltage S shown in FIG. 2, the first sampling timing is determined to be abnormal in the high and low directions, but the second sampling timing is normal and no alarm is output.

Here, the judgment in the high and low directions by the sign comparison calculator 5 will be described with reference to FIG. Assuming that the sign comparison calculator 5 outputs 4-bit information b0 to b3, the input voltage S = reference value when all of b0 to b3 are “0”. b0 is the least significant bit and b3 is the most significant bit. The state of the most significant bit b3 is determined on the plus side and the minus side of the input voltage S centering on the reference value.
As shown in FIG. 3, when the judgment value is determined, the A / D
The output of the converter 4 is "b3, b2, b1, b0" = "011.
When it is "0", b3 is "0", so it is compared with the determination value on the plus side. Since it is greater than the determination value "0100", it is determined to be abnormal.

Next, a multipoint abnormal voltage monitoring system according to another embodiment of the present invention will be described with reference to FIGS. The multipoint abnormal voltage monitoring system shown in FIG. 4 is realized by adding some of the circuits of the embodiment shown in FIG.

As shown in FIG. 4, two input signals S1 and S
Add an input part to monitor 2. In these input parts, the level converter 1 and the sampling and holding circuit 2 constitute one channel board, and two channel boards 41 and 42 are prepared. These channel boards 4
The clock generating circuit 43 controls the circuits 1 and 42.
As shown in FIG. 5, the clock generation circuit 43 generates sampling clocks with phase shifts such as CL11 and CL12 for the channel boards 41 and 42. Channel signals sampled by the channel boards 41 and 42 at the timings of the sampling clocks CL11 and CL12 are input to the A / D converter 4 as shown in FIG. 5 and sequentially encoded. The information from the A / D converter 4 is supplied to the sampling clocks CL11, C by a sign comparison calculator 44 having a comparison calculation function for two channels.
Judgment is made at the timing of clocks CL21 and CL22 which are phase-locked to L12, and when the judgment criterion is exceeded, an alarm signal is output to that channel.

[0014]

As described above, the present invention has an effect that it is possible to monitor the allowable range determined by the height of the reference voltage and the width of the time axis. Further, there is an effect that the configuration can be simplified by using the determination means for a plurality of monitored signals in a time division manner.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart corresponding to the operation of the embodiment shown in FIG.

FIG. 3 is a diagram for explaining determination of high and low directions by a sign comparison calculator 5 of FIG.

FIG. 4 is a block diagram of another embodiment of the present invention.

5 is a time chart of the operation of the embodiment shown in FIG.

[Explanation of symbols]

 1 Level converter 2 Sampling and holding circuit 3,43 Clock generation circuit 4 A / D converter 5,44 Sign comparison calculator 41, 42 Channel board

Claims (2)

[Claims] 1. A sampling means for sampling a voltage to be monitored with a sampling signal of a predetermined cycle, and an output voltage of the sampling means exceeds a predetermined range continuously for a predetermined number of times of the predetermined cycle. An abnormal voltage monitoring method, comprising: a determining unit that determines whether or not the abnormal voltage is present. 2. A plurality of said sampling means, each of which operates with said sampling signal having a different phase from each other,
2. The abnormal voltage monitoring method according to claim 1, wherein one of the determination means determines the output voltage of the sampling means in synchronization with each sampling phase of each of the output voltages.