JPH0524595B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a reference voltage generation circuit in a digital logic circuit and a memory circuit, and particularly to a signal generation circuit suitable for a memory cell reference voltage generation circuit. .

[Background of the invention]

Hereinafter, when explaining the present invention, an example in which the present invention is applied to a bipolar memory circuit will be described in detail, but this is only for the purpose of explanation, and the present invention can be widely applied to logic circuits and memory circuits. It is.

Now, in bipolar memory, the memory cell
As the array, its drive, and sense circuit, the first
The one shown in the figure has been widely used. In this figure, the collector load of the memory cell MCOO etc. is composed of a parallel circuit of a resistor R _L01 etc. and a diode D ₀₁ etc. This diode may be a junction diode or a Schottky diode. The operation of this circuit will be briefly explained below. First, one of the word line drivers, say XDO, is selected and its output,
In other words, the word line XO becomes a high level V _XH . All other word line driver outputs are low level
Located in V _XL . In a selected cell, for example MCOO, if transistor Q ₀₁ is on and Q ₀₀ is off, the read current I _R flows out of transistor Q ₀₁ . The base voltage of transistor Q ₀₁ at this time,
Let the collector voltages be V _CH and V _CL , respectively. Output of read/write control circuit R/W0, R/W1
When reading, V _r0 and V _r1 are at a level approximately midway between V _CH and V _CL (that is, the reference voltage during reading).
Located in V _RH . Therefore, read current I _R00 flows from transistor Q _r00 , I _R01 flows from transistor Q ₀₁ of the cell, and does not flow from transistor Q _r01 . Therefore, a read current flows through the resistor R _s00 , causing a voltage drop, while a base current flows through the resistor R _s01 , resulting in a small voltage drop. By detecting which resistor causes a large voltage drop,
The information stored in the cell can be read.

On the other hand, in order to write, one of the outputs of the read and write circuits R/W0 and R/W1, for example, V _r1 becomes a low level V _RL . In this case, V _RL must be lower than V _CL for a write to occur (ie, to cause I _R00 to flow from transistor Q ₀₀ that was off). Also,
During writing, V _XL must be lower than V _CL so that current is not shunted away from cells connected to other word lines.

The above potential relationships are summarized in Figure 2.

By the way, even if the design center value is taken as shown in Figure 2, in reality, device parameters fluctuate due to temperature and other factors, and there are various variations, so the potential difference between each potential may decrease or increase. do. This decrease or increase requires designing each potential difference to be large at the design center value as a noise margin, which makes it impossible to drive the circuit with a low amplitude, making it impossible to increase the speed of the circuit.

The above-mentioned prior art will be described in more detail below.

In FIG. 1, diodes _D01 and the like are Schottky diodes (hereinafter abbreviated as SBD).
On the other hand, current source transistors Q ₁₀₀ of read/write circuits (hereinafter abbreviated as R/W circuits) R/W1, etc., word line drive circuits (hereinafter abbreviated as WD circuits) XD0, etc.
Voltage applied to the base of Q ₁₁₀ etc. V _cs-1 , V _cs-2
Conventionally, as shown in FIG. 3, the voltage is taken out from a point 40 in a series circuit of a resistor and a diode through an emitter follower transistor 41. In this case, the output voltage V _cs of this circuit can be approximately approximated by V _cs = α (Vcc - V _EE ) + βV _BE . Here, V _BE represents both the diode forward voltage and the transistor base-emitter forward voltage. This power supply is connected to the R/W circuits R/W0, R/W1 and
Current source transistor Q ₁₀₀ such as WD circuit XD0,
When applied to the base of a Q ₁₁₀ etc., its output will have a voltage of V _put = a × [α (Vcc - V _EE ) + (β - 1) V _BE ] = α' (Vcc - V _EE ) + β' V _BE appears. Here, α, β, α′, and β′ are constants (determined at the time of design) that satisfy V _EE V _cs and V _put Vcc (=GND potential in this example).

As is clear from the expression, this output voltage V _put is the voltage generated in the parallel circuit of the SBD and the resistor that is the collector load of the memory cell of the load circuit.
Their characteristics are different.

Furthermore, here I=0, J=3, resistance R ₄₁ =0Ω
At this time, V _cs in Figure 3 becomes as follows.

V _cs = V _EE + 2V _BE For example, when V _cs-1 is driven with this V _cs , the memory cell reference voltage V _RH is expressed by the following equation.

V _RH =-(Rc/R _E +1) V _BE On the other hand, V _XH is determined by the following formula, regardless of V _cs-2 .

_{V _ _ _ _}
It is no longer determined simply by V _BE alone.

V _{CH =} V _XH − [ _{R L00} //V _{F ] ×} I _{R / H FE V CL} = _V Therefore, as will be described later, there is a drawback that the operating margin against variations in V _F is reduced.

Also, as a characteristic of integrated circuits, within the same chip, V _BE is the same as V _BE , and SBD's forward voltage V _F is V _F
If they are like-minded people, there will be very little variation. However, V _BE
The relationship between VF and _VF varies greatly depending on the chip.
Therefore, in conventional circuits, increasing the speed by reducing the cell amplitude is limited by this point.

[Purpose of the invention]

The purpose of the present invention is to provide a reference voltage that moves while maintaining the relative relationship between potentials as shown in Figure 2 even if device parameters change, and therefore does not require a large noise margin. Generation circuit (first
In the figure, read/write circuits R/W0, R/W1)
The goal is to provide the following.

[Summary of the invention]

In order to achieve the above object, the present invention includes a load circuit configured with two or more types of elements, a current source circuit that supplies current to the load circuit, and a logic state of the output of the load circuit. In the semiconductor circuit having a reference voltage generation circuit for the purpose of It was decided that this would occur. More specifically, the voltage drop in two logic states of a load circuit (for example, a memory cell) is measured by a pseudo circuit having the same configuration as each logic state of the load circuit, and a current source that supplies current to the load circuit. By combining two voltage drops generated by a current source circuit of the same type as the circuit, an intermediate value of the detection terminal voltage in the two logic states of the load circuit is generated and used as a reference voltage.

According to the invention, as part of the V _cs generation circuit,
Load circuit, for example memory collector load inserted,
As a result, the above-mentioned limitations can be overcome, so it is possible to reduce the amplitude of the cell signal and increase the speed.

[Embodiments of the invention]

The main part of an embodiment of the present invention is shown in FIG. This embodiment uses the read/write circuit R/W described in FIG.
0, R/W1 is configured with a current switching circuit formed by transistors Q50 to Q52, and its current source circuit is formed by transistors Q53 and Q54 and a resistor R50.
and R51. Then, the base of transistor Q53 is driven with a potential V _CSL related to V _CL of the memory cell, and the base of transistor Q54 is driven with a potential V _CSH related to V _CH of the memory cell.
It is driven by This generation of V _CSL generates a read current I _R00 or I _R01 in the diodes D60 and 61, the resistors R60 and R61, and the transistor Q60, and the collector load of the memory cell transistor (formed by the diode _D01 and the resistor R _L01 ). The potential difference caused by this read current flowing, that is, V _XH − _{V CL}
is generated, and this potential difference is applied to the resistor R50. Furthermore, V _CSH similarly generates a potential difference of V _XH - V _CH and is applied to resistor R51.

By doing this, the potential drop ΔV _R52 at the resistor R52 can be determined by the following equation.

ΔV _R52 = R52/R50 ₍ V _XH − V _CL ) + _R52 /R51 (V _XH − V _CH ) where V ΔV _CL , and V _XH −V _CH is the potential drop ΔV _CH in the collector load of the memory cell when the base current of the read current flows.

Here, setting the reference voltage V _RH at the time of reading to an intermediate value between V _CL and V _CH can be achieved by setting the resistors R50 and R51 to be equal and setting the value to be twice the value of R52.

Furthermore, by forming resistors R61 and R63, etc. in the same shape and configuration as the I _R00 and I _R01 generation circuits shown in Figure 1, it is possible to compensate for variations in the read current, and in addition to compensating for the collector load of the memory cell, it becomes more stable. It becomes possible to generate a reference voltage.

In the current switching circuit, during reading, transistor Q52 is conductive, and during writing, Q50 or Q51 is conductive depending on the write data, and V _r0 or
Generates V _r1 .

FIG. 5 shows a memory cell in Japanese Patent Application Laid-Open No. 53-75829. The feature of this memory cell is that a resistor R600 is connected in series with the diode D600, and the potential drop across the resistor R600 due to the read current determines the operating margin of the memory cell. Furthermore, the resistor R600 is formed using an N ⁺ BL layer in order to reduce the memory cell size. Therefore, in order to stabilize the memory cell operation, the read current needs to be controlled by the resistance value formed by the N ⁺ BL layer. Therefore, in the read current generation circuit, the resistance R600 of the memory cell
It uses a resistor whose value is determined by a correlation with the That is, in FIG. 6, the resistor R71, in FIG. 7, the resistor R72, and the resistor R6 of the memory cell.
It has the same shape and structure as 00. By doing this, when the resistance 600 of the memory cell formed by N ⁺ BL becomes small, the read current increases, and conversely, when the resistance R600 becomes large, the read current becomes small, and the potential of the memory cell becomes smaller than the resistance R6.
Compensation is made so that the change in value of 00 remains constant.

FIG. 8 is another embodiment of the present invention,
Resistors R90 and R91 are the resistance R6 of the memory cell.
It is formed in the same shape and structure as 00, generates a read current, and the current flows to the memory cell shown in Figure 5, generating V _CSL and V _CSH corresponding to the potential drop due to the load of the memory cell. I'm letting you do it.

At this time, V _CSH and V _CSL are as follows.

V _CSH = V _EE + V _BE + [R603//(V _F + R601)] × I _B V _CSL = V _EE + V _BE + [R602// (V _F + R600)] × I _C where I _R is the read current Yes, [R603//(V _F
+R601)]×I _B is a diode D601 and a low resistance R601 (generally 200 to 300Ω) connected in series,
Q600 of the read current I _R for the collector load of the memory cell with high resistance R603 in parallel with it.
This term corresponds to the potential drop due to the base current, and the same term of V _CSL corresponds to the potential drop due to the collector load of the memory cell due to the collector current.

Therefore, by applying V _CSL and V _CSH to the bases of transistor Q53 and transistor Q54 in FIG. 4, the emitter currents of Q50 and Q51 are respectively determined by a potential difference corresponding to the potential drop in the memory cell. By setting the value of resistor R52 to approximately 1/2 of resistors R50 and R51, V _RH (V _r0 and V _r1 are equal at the time of reading) _is
It is possible to make it determined by the amount of potential drop at the collector load of the memory cell.

By doing this, the devices that make up the memory cell, such as diodes (P-n diodes or Schottky diodes), the resistance formed by the N ⁺ BL layer, and the high resistance (the high resistance formed by the Imbra layer) It is also possible to generate a memory cell reference voltage that compensates for variations in the values of the resistors R602 and R603 in FIG. 5 during manufacture.

Furthermore, the diode and resistor connected to the collector of the transistor Q610 in the V _CSH generation circuit can be omitted due to the principle of operation.

〔Effect of the invention〕

With the present invention, even when there are variations in temperature and device parameters (V _BE , V _F , N ⁺ BL resistance, etc.),
It is possible to always place the memory cell reference voltage (V _RH ) in the center of V _CH and V _CL .

By taking advantage of these features of the present invention, it is possible to reduce the amplitude of the cell signal to 400mV or less, and depending on the design, the delay time of the memory circuit can be reduced by 20% to 40% compared to conventional methods. You can also do that.

Although the present invention has been described above in connection with a memory circuit, the present invention is not limited to memory circuits and can be applied to similar circuits. Furthermore, in the case of memory circuits, we have specifically discussed memory cells that have SBDs, resistors, and their parallel circuits as loads, but
The present invention can be similarly applied even if linear and nonlinear loads are used as the load circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a memory cell drive circuit as a conventional example, FIG. 2 is a diagram showing potentials at various points in the circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram explaining one embodiment of the present invention, FIG. 5 is a memory cell circuit diagram in Japanese Patent Application Laid-Open No. 53-75829, and FIGS. 6 and 7 are read current source circuit diagrams. FIG. 8 is another example,
6 is a diagram of a reference voltage generation circuit suitable for the memory cell of FIG. 5. FIG.

Claims (1)

[Claims] 1. A first of a pair of multi-emitter transistors whose bases and collectors are cross-coupled connected.
a memory cell whose emitters are connected in common, and a load circuit having a parallel connection of a resistor and a diode is connected to the collectors of the pair of multi-emitter transistors; a read/write control circuit connected to two emitters of the first transistor, a first transistor, a second transistor, and a third transistor whose emitters are commonly connected; a first resistor whose one end is connected to the collector of the second transistor; a second resistor whose one end is connected to the collector of the second transistor; and one end of which is connected to the other end of the first resistor and the second resistor. a third resistor connected to the other end of the resistor and the collector of the third transistor; and a third resistor whose base and emitter are connected to the collector of the first transistor and the second emitter of the pair of multi-emitter transistors. a fourth transistor whose base and emitter are respectively connected to the collector of the second transistor and the other of the second emitters of the pair of multi-emitter transistors; a first current source to which a first reference voltage generated from a first reference voltage generation circuit is applied to its base and whose collector is connected to the common emitter of the first, second, and third transistors; a second current source to which a second reference voltage generated from a second reference voltage generation circuit is applied to its base and whose collector is connected to the common emitter of the first, second, and third transistors; The first reference voltage generating circuit includes a parallel connection of a resistor and a diode, and a series connection of a collector-base short-circuited transistor, and by supplying current to the series connection, the first reference voltage generation circuit The base and collector of the second reference voltage generating circuit are connected to one end of a parallel connection between a resistor and a diode and one end of another parallel connection between another resistor and another diode, respectively. the second reference voltage is generated by commonly connecting the other end of the parallel connection and the other end of the other parallel connection and supplying a current. circuit.