JPH05244129A - Sdh interface circuit - Google Patents

Abstract

PURPOSE:To simplify the memory capacity, the gate scale and the hardware configuration by executing functions of speed matching and stuff control in a cell terminal part. CONSTITUTION:A cell terminal part 4 has an absorbing function for a jitter and a wander caused by speed matching by clock loading conversion, and stuff control, in addition to format converting and cell length converting functions. Also, the function of speed matching is executed in the cell terminal part 4 instead of a clock loading converting part of a conventional path terminal part. Moreover, the path terminal part constituted heretofore of a clock loading converting part, a pointer terminal part and a POH terminal part is constituted of a pointer terminal part 2 and a POH terminal part 3. In such a way, the function for absorbing a jitter, a wander and a frame phase difference is also executed by clock loading conversion and stuff control executed in the cell terminal part 4 instead of the clock loading converting part of the conventional pass terminal part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous digital hierarchy (hereinafter referred to as SDH) interface circuit in a wide band integrated service digital network (hereinafter referred to as wide band ISDN).

[0002]

2. Description of the Related Art A configuration example of an SDH interface circuit in a conventional broadband ISDN will be described with reference to FIGS. The interface structure of the SDH-based physical layer has a transmission frame conforming to Recommendations G707, G708, and G709 that define the SDH network node interface structure. FIG. 11 shows an example of the structure.
The information has 8 bits as 1 byte and a cell C of 53 bytes as a unit. To accommodate this cell C in the interface structure for the 155.52 Mbit / s interface, the continuous full cell stream of cell C is S
It is stored in the C-4 area which is the VC-4 payload of the DH virtual container. Next to this VC-4 VC-4
Add path overhead to form AU-4. The cell boundary is aligned with the STM-1 byte boundary, but the C-4 capacity (2340 bytes) is equal to the cell length (53b).
y)), the cell may exist across a C-4 boundary on two different transmission frames.

FIG. 10 is a block diagram of a conventional SDH interface circuit. A signal flow from right to left is shown as a transmission system, and a signal flow from left to right is shown as a reception system, which are independent of each other. Is provided as a signal system. Here, the reception system will be mainly described. In the figure, the SDH interface circuit includes a section termination unit 101, a clock transfer unit 100, a pointer termination unit 102, a POH termination unit 103, and a cell termination unit 104. STM-1 to the section end part 101
Signal is transmitted in this state, and the clock transfer unit 100 is set to AU-4 after the pointer, the pointer terminating unit 102 separates the pointer to VC-4, and the POH terminating unit 103 separates POH to C-4. Finally, in the cell terminating unit 104, the transmission format conversion for converting the container and the full cell stream and the cell length conversion such as removing the cell having no information in C-4 are performed to perform the full cell stream. I am trying. The section terminating unit 101 operates according to the transmission path clock, and the pointer terminating unit 102, the POH terminating unit 103 and the cell terminating unit 104 operate according to the in-station clock. Then, the transmission line clock and the in-station clock are input to the clock transfer unit 100, and when the frequencies of the transmission line clock and the in-station clock are different, the frequency is changed by clock conversion to perform speed matching. ing.

The clock transfer unit 100, the pointer terminating unit 102 and the POH terminating unit 103 are composed of one element and are called a path terminating unit. Further, in this path termination portion, the in-station clock and the transmission path clock absorb the jitter, wander, and frame phase difference that occur as a time shift from the normal position.

Therefore, in the conventional SDH interface circuit, the speed matching and the absorption of jitter, wander and frame phase difference are absorbed in the path terminating unit constituted by the clock transferring unit 100, the pointer terminating unit 102 and the POH terminating unit 103. I'm doing it. FIG. 11 shows the conventional S
It is a block diagram of speed matching of a DH interface circuit. In the figure, conventional speed matching will be described.

Cell C is stored in a container of C-4 and PO
The STM-1 constructed by adding the AU-4PTR pointer and SOH to the VC-4 with H added
-C transfer unit 100 according to the transmission clock of C
To enter. Transmission clock CLK-C and station clock C
If the frequency is the same as that of LK-C0, it is not necessary to perform speed matching, and therefore the signal is transmitted as it is to the station.

When the frequency of the transmission clock CLK-C is higher than the frequency of the in-station clock CLK-C0, the pointer value is incremented by 1 using the next byte of the pointer AU-4PTR in the figure as the stuff byte, and vice versa. When the frequency of the in-station clock CLK-C0 is higher than the frequency of the transmission clock CLK-C, the pointer value of the pointer AU-4PTR in the figure is decremented by 1 to give a negative stuff byte, and the pointer AU-4PTR stores the same data in the frame. It accommodates and transmits VCs. In this way, absorption of small frequency fluctuations is dealt with by stuff control that increases or decreases the pointer value by one.

Next, as a conventional example for absorbing jitter, wander, and frame phase difference, Masahiro Takatori (4 others) announced at the 1990 Spring National Convention of the Institute of Electronics, Information and Communication Engineers, "SDH for maintaining frame phase difference. Pointer conversion method "(1990 Spring National Convention of the Institute of Electronics, Information and Communication Engineers, B-764), and FIG. 12 is a block diagram of the pointer conversion circuit.

This pointer conversion circuit includes a VC buffer 110 for temporarily storing a VC, an input control unit 111 for decoding a reception pointer from the VC and controlling writing to the VC buffer 110, and a read control from the VC buffer 110. The output control unit 113 controls output pointer generation including output stuffing control, and the stuffing determination unit 112 determines the stuffing by comparing the difference between the write address and the read address.

These processes are performed by the stuff control of the clock transfer unit 100 at the path termination unit.

[0011]

However, the above method has the following problems. At the path termination part, speed matching and jitter, wander and frame phase difference absorption are performed by stuff control, etc., and since the cell termination part performs transmission format conversion and cell length conversion,
Since the memory is provided at both the path terminating portion and the cell terminating portion, there is a drawback that the gate scale increases and the hardware configuration becomes complicated.

Further, since a plurality of VCs are multiplexed in the frame, the pointer conversion circuits at the above-mentioned path terminating parts are required for the number of VCs. Generally an individual VC
Are independent signals having different frame phases, it is necessary to independently perform pointer conversion on a plurality of multiplexed VCs. However, if the VCs are controlled independently, the frame phase difference between the VCs may differ. Therefore, in order to realize a communication service using a plurality of channels at the same time, a large-capacity buffer for phase adjustment and a complicated control circuit are required at the path termination unit.

Therefore, the functions of speed matching and jitter, wander, and frame phase difference absorption in the conventional SDH interface circuit are performed by clock transfer and stuff control of a large amount of information on a frame-by-frame basis at the path termination section. , Requires a large capacity memory and gate, and the hardware configuration becomes complicated. The present invention eliminates the above-mentioned problems, eliminates the drawback that the hardware configuration becomes complicated as the memory capacity and the gate scale increase, and is excellent in the memory capacity and the gate scale and the hardware configuration. The purpose is to provide.

[0014]

According to the present invention, in an SDH interface circuit, a cell terminating section for performing format conversion and cell length conversion, means for introducing a transmission line clock and an in-station clock to the cell terminating section, and the clock are provided. And a means for canceling the phase difference of the clocks, and a means for canceling the phase difference and a means for canceling the phase shift are provided in the cell terminal section. The functions of speed matching and stuff control are performed at the cell end.

[0015]

According to the present invention, in the above-mentioned structure, the terminal section of the SDH interface circuit has a first-in first-out memory for inputting input data and outputting output data, and either a transmission path clock or an in-station clock. A write control unit that controls writing in the first-in first-out memory, and a clock that is either a transmission path clock or an in-station clock that is different from the clock that is introduced into the write control unit. And a read control unit for controlling the reading of the data, and when a mismatch occurs between the input data input to the cell termination unit and the output data output due to the frequency or phase shift between the transmission path clock and the internal clock, the write operation is performed. The control unit discards the data for one cell length and controls reading. It sends an empty cell.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an SDH interface circuit of the present invention. here,
Similar to the description of the above-mentioned conventional example, the receiving system will be mainly described. This is because the fluctuation of the clock that causes the jitter and wander occurs only in the receiving system.

In this structure, the speed matching, the jitter, and the wander absorbing function, which are performed in the conventional path terminating unit, are provided in the cell terminating unit. In FIG. 1, the SDH interface circuit of the present invention is composed of a section terminating unit 1, a pointer terminating unit 2, a POH terminating unit 3, and a cell terminating unit 4 in order toward the receiving device. S from transmission line
TM-1 is AU-4 in the section terminating portion 1,
In the pointer terminating unit 2, the pointer is separated and VC-4
Then, the POH is separated at the POH terminating portion 3 and C
-4, and finally, in the cell terminating unit 4, cell length conversion such as transmission format conversion for converting a container and a full cell stream and removal of cells having no information in C-4 are performed. It is a cell stream. In addition to the format conversion and cell length conversion functions, the cell termination unit 4 has a speed matching by clock switching and a jitter by stuff control, and a wander absorbing function. Also, the section terminating unit 1 and the pointer terminating unit 2
And the POH termination unit 3 is operated by the transmission line clock,
The cell terminating unit 4 and thereafter operate according to the internal clock. In addition to the in-office clock, a transmission line clock is also added to the cell terminal unit 4 for speed matching.

With this configuration, the speed matching function is performed in the cell termination unit 4 instead of the conventional clock transfer unit in the path termination unit. Along with this, the path terminating unit, which is conventionally composed of the clock transferring unit, the pointer terminating unit and the POH terminating unit, is composed of the pointer terminating unit 2 and the POH terminating unit 3. The functions of absorbing jitter, wander, and frame phase difference are also performed by the clock transfer and stuff control performed in the cell termination unit 4 instead of the conventional clock transfer unit in the path termination unit.

Therefore, instead of performing the speed matching and the process of absorbing the jitter, the wander, and the frame phase difference by the processing of a large amount of information in units of frames in the conventional path terminating unit by this configuration, the cell terminating unit is replaced. In step 4, a small amount of information is processed in units of cells, so that the amount of processed information and the memory required for the processing can be reduced. This reduction in memory is due to the reduction in the amount of information processed from the frame unit to the cell unit, and the reduction in the memory at both the path termination unit and the cell termination unit being only the cell termination unit. There are two. The speed matching and the jitter, wander, and frame phase difference absorption functions at the cell end will be described with reference to FIGS.

Referring to FIG. 2, a configuration example of cell length conversion including speed matching and jitter in the cell terminating portion 4 and a wander absorbing function will be described. The cell termination unit 4 is a first-in first-out memory (hereinafter referred to as FIFO) 4
1, a write control unit 42 that controls writing of the FIFO 41, and a read control unit 43 that controls reading of the FIFO 41.

The reception system will be described below.
The cell C of C-4 is written to the input section of the cell by the transmission system clock CLK1 under the control of the write control section 42. On the other hand, the full cell stream with the cell length converted as shown in the figure is output to the output section of the FIFO 41 by the read control section 43 with the in-station clock CLK0. For speed matching, jitter, and wander absorption, cell stuffing is determined by comparing the address difference between the write address and the read address. The empty cell transmitted by the stuff determination of this cell and the empty cell indicated by * in FIG. 2 have different contents. Empty cells indicated by * in FIG. 2 are SOH, PO
It is a cell that fills the gap in the H region and is invalid data.

The operation of the FIFO 41 of FIG. 2 will be described with reference to the flowchart of FIG. S1 to S5 of the flowchart of FIG. 3A are steps for writing input data to the FIFO 41, and S6 to S10 of the flowchart are steps for reading output data from the FIFO 41. First, the steps for writing will be described. Writing is started at the start of step S1, and the FIFO 41 for one cell length of input data is started at step S2.
It is determined whether the writing to the memory has been completed.

When it is determined in step S2 that the writing of the input data into the memory of the FIFO 41 for one cell length is not completed, the determination is NO and the process is repeated until the writing is completed. FIFO 41 for one cell length of input data
When the writing to the memory is completed, the determination in step S2 is YES, the process proceeds to step S3, and the process of writing into the memory of the FIFO 41 is performed.

Next, in step S4, step S3
It is determined whether or not the memory used for writing is the same as the memory being read at that time. In this determination, if the memory used for the writing is different from the memory being read at that time, the determination in step S4 is NO, the process returns to step S2, and the writing for one cell length is performed in the memory. If the memory used for writing is the same as the memory being read at that time, step S
4 determines YES, and discards data for one cell length in the writing process in step S5. This writing step is performed by the transmission system clock CLK1 in FIG.

Next, steps for reading will be described with reference to FIG. FIFO4 to be read at the start of step S6 and to be read at step S7
It is determined whether or not the data for one cell length is stored in the memory No. 1. In the determination in step S7, if the memory of the FIFO 41 to be read does not contain data for one cell length, it is determined as NO, and the process proceeds to step S10. In step S10, an empty cell containing no data is transmitted.
This empty cell is different from the empty cell that is a cell that fills the gap between the SOH and POH regions shown by * in FIG. After the empty cell is transmitted in step S10, the process returns to step S7 again, and it is determined whether or not the memory of the FIFO 41 to be read contains one cell length of data. Further, in the determination of step S7, if the memory of the FIFO 41 to be read contains the data for one cell length, it is determined as YES,
Move to step S8.

In step S8, the memory data in the process of reading from the FIFO 41 is sent out. When the data transmission is completed, the process proceeds to the next step S9, the next memory reading is performed, and the process returns to step S7. This reading step is performed by the in-office clock CLK0 in FIG. Next, speed matching will be described. At this time, for ease of explanation, it is assumed that there is no jitter, wander or frame phase difference.

4 to 6 are conceptual diagrams for explaining the speed matching function. When the frequency CL1 of the transmission system clock is equal to the frequency CL0 of the in-station clock, the frequency CL1 of the transmission system clock is equal to the in-station clock. 3 and the frequency CL0 of the intra-station clock is higher than the frequency CL1 of the clock of the transmission system. The case will be described along the flow of the flowchart of FIG. Note that the FIFO 41 is a first-in first-out memory in which the first input data is first output, and is made up of two memories, a first memory 44 and a second memory 45, for ease of explanation. explain.

First, the frequency CL1 of the transmission system clock
The case where the frequency CL0 of the in-station clock is the same will be described with reference to FIG. 4A is premised on that the signal is transmitted from the left side to the right side in the receiving system.
The frequency CL is stored in the FIFO 41 at the cell end (not shown).
A transmission system clock of 1 and an in-station clock of frequency CL0 are introduced.

In FIG. 4B, one cell length of data 1
Is written in the first memory 44, and the next data is written in the second memory 45 in step S2. In step S4, the second memory 45 is not the memory that is being read, so writing to this memory 45 is advanced. When the writing of the data 2 for one cell length into the second memory 45 is completed again in step S2, the process moves to (c) of FIG. 4, which is the step of writing the data 3.

In FIG. 4C, the determination in step S4 is NO, so the input of data 3 to the first memory 44 is continued. The determination of NO in step S4 is because the data 1 recorded in the first memory 44 at this point has already been read. That is, in the determination of step S7, the frequency CL1 of the transmission system clock is equal to the frequency CL0 of the in-station clock, and there is no phase shift, so that data 1 for one cell length has already been stored in FIG. This is because the data 1 is sent out in S8 and the data is empty in the first memory 44.

Therefore, the frequency C of the clock of the transmission system
When L1 and the frequency CL0 of the internal clock are equal,
It is transmitted to the station as it is. Next, a case where the frequency CL1 of the clock of the transmission system is higher than the frequency CL0 of the in-station clock will be described with reference to FIG. Also in FIG. 5A, it is assumed that the signal is transmitted from the left side to the right side in the receiving system. Into the FIFO 41 of the cell terminal unit 4, a transmission system clock having a frequency CL1 and an in-station clock having a frequency CL0 are introduced.

In FIG. 5B, data 1 for one cell length
Is written in the first memory 44, and the next data is written in the second memory 45 in step S2. In step S4, the second memory 45 is not the memory that is being read, so the writing of data 2 to this memory 45 proceeds. When the writing of the data 2 for one cell length into the second memory 45 is completed again in step S2, the process moves to (c) of FIG.

In FIG. 5C, the determination in step S4 is YES, so the process proceeds to step S5 and the data 3 which is the data for one cell length is discarded. The determination of YES in step S4 is made at this point in the first memory 4
This is because the data 1 recorded in No. 4 has not been completely read out. That is, the frequency CL of the clock of the transmission system
Since 1 is higher than the frequency CL0 of the in-station clock,
The writing speed for writing the data 2 in the second memory 45 is faster than the reading speed for the data 1 recorded in the memory 44, and the first memory 44 for the data 3 is written in step S4.
This is because the reading of the data 1 from the first memory 44 is not yet completed at the time of starting the writing to the memory.

Next, in step S5, the data for one cell length is discarded, and then the next data is written. At this time, since the position of the memory to be written next does not change, the next data 4 is written in the first memory 44. In step S4, it is determined whether the next data 4 can be written in the first memory 44. At this point, since the data 1 stored in the first memory 44 has been read, it is determined as YES in step S4, and the data 4 is written in the first memory 44.

In FIG. 5E, when the transmission of the data 2 is completed, the first memory 44 is read out in step S7 according to step S9. Since the writing of the data 4 to the first memory 44 is not completed at this point, it is determined as NO in Step S7, and Step S10
Will send an empty cell. Therefore, at this stage, writing of data 4 to the first memory 44 and sending of empty cells are performed. When the writing of the data 4 to the first memory 44 is completed, YES is determined in step S2, and the writing of the data 5 to the second memory 45, which is the next memory, is performed in step S3. In the determination in step S4, the memory being read is the first memory 44.
Therefore, it is determined to be NO and the data 5 to the second memory 45 is
Writing continues.

In FIG. 5 (f), when the writing of the data 5 into the second memory 45 is completed, the frequency CL1 of the clock of the transmission system is higher than the frequency CL0 of the in-station clock as described above. The reading of the data 4 from the first memory 44 has not been completed yet. Therefore,
In the next writing of the data 6 to the first memory 44, the determination in step S4 is YES, and the data of one cell length of the data 6 is discarded in step S5.

After this, the state becomes almost the same as in FIG. 5B again, and the frequency difference is repeated for the same period. Next, a case where the frequency CL0 of the in-station clock is higher than the frequency CL1 of the transmission system clock will be described with reference to FIG. 6A also assumes that the signal is transmitted from the left side to the right side in the receiving system. FIF of cell termination unit 4
In O41, a transmission system clock of frequency CL1 and frequency C
The L0 internal clock is introduced.

In FIG. 6B, the data 1 for one cell length is stored in the first memory 4 in step S2 of the flow chart.
4 and the next data is written in the second memory 45 in step S2. Then, as shown in FIG. 6C, since the second memory 45 is not the memory which is being read in step S4, the writing of the data 2 to the second memory 45 is proceeded. At this time, the frequency CL0 of the in-station clock is the frequency CL1 of the transmission system clock.
Therefore, the reading of the data 1 from the first memory 44 is finished before the writing of the data 2 to the second memory 45 is finished. Next, in FIG. 6D, when the data transmission is completed in step S8, the process proceeds to step S9 to read the next memory. Control of reading of the next memory is performed in step S7, but since writing of data 2 to the second memory 45 is not yet completed, N
When it is determined to be O, an empty cell is transmitted in step S10.

As shown in (e) of FIG. 6, when the timing of writing the data 3 to the first memory 44 comes while the empty cell is being sent, the data of the first memory 44 has already been read. Since it is empty, it is determined as NO in step S4, and the process proceeds to step S2 to write the data for one cell length. In (e) and (f) of FIG. 6, when the transmission of the empty cell from the second memory 45 is completed, the process of reading the data of the next memory is started. Since the position of the memory to be read next after the empty cell is transmitted does not change, the next data 2 is read from the second memory 45. After reading from the second memory 45, the next reading of the data 3 stored in the first memory 44 is performed in step S9. The subsequent state is almost the same as that in (b) of FIG. 6, and is repeated for the same frequency difference.

Therefore, data and empty cells are transmitted within the station. Since this frequency difference is a rare phenomenon, it is possible to perform speed matching by discarding some data and sending empty cells. Next, absorption of jitter, wander, and frame phase difference will be described. 7 and 8 are conceptual diagrams for explaining the functions of absorbing jitter, wander and frame phase difference. The wander is a long-period fluctuation due to the fluctuation of the transmission delay time of the transmission line due to the temperature change, and its periodic fluctuation is much longer than the jitter, and its absorption operation can be explained in the same way as the jitter. Therefore, the jitter will be described here.

Taking the jitter of the clock of the transmission system as an example, description will be given according to the flow of the flowchart of FIG. 3 in two cases, that is, a case where the time shifts from the normal position forward and a case where the time shifts backward. To do. Note that the FIFO 41 is a first-in first-out memory in which the first input data is first output, and is made up of two memories, a first memory 44 and a second memory 45, for ease of explanation. explain.

First, the case where the jitter of the clock of the transmission system is caused by the forward shift in time from the normal position will be described with reference to FIG. In FIG. 7A, a signal is transmitted from the left side to the right side in the receiving system. The FIFO 41 at the cell end is supplied with the transmission system clock having the frequency CL1 and the in-station clock having the frequency CL0. Figure 7
7B corresponds to the time t2 in FIG. 7A, and the data 1 for one cell length corresponds to the first time t2 in step S2.
The data is written in the memory 44, and the next data is written in the second memory 45 in step S2. In step S4, the second memory 45 is not the read memory, so
Writing of data 2 into this memory 45 is advanced. In step S2 again, the second memory 4 of the data 2 for one cell length
When writing to data 5 is completed, the process moves to (c) of FIG. 7, which is a step of writing to data 3.

FIG. 7C shows time t3 'in FIG. 7A.
The time t3 ′ is shifted forward from the regular time t3. Therefore, time t2 and time t
The clock interval becomes shorter between 3'and the clock interval becomes longer between time t3 'and time t4. Time t
At the time of 3 ′, the data 2 shows that the time t3 ′ is the regular time t3.
Although the writing to the second memory 45 is completed due to the shift to the front, the reading of the data 1 from the first memory 44 is not completed. Therefore, if the writing of the data 3 into the first memory 44 is determined in step S4, the determination of YES is made because the reading of the data 1 from the first memory 44 has not been completed. Then, in step S5, the data 3 which is the data for one cell length is discarded.

Next, (d) of FIG. 7 corresponds to the time t4 of (a) of FIG. 7, the reading of the data 2 stored in the second memory 45 is completed, and the next step S9 is executed. In step S7, it is determined whether or not the first memory 44 to be read next contains data for one cell length. In this determination, since the data 3 has been discarded at the above-mentioned stage, it is determined to be NO, and step S
At 10, the empty cell is sent out. Further, in step S4 of the writing process, it is determined whether the first memory 44 in which the data 4 is written next is the memory being read. Since the position of the memory where the next data is written does not change after the data is discarded, the data 4 is written in the first memory 44. At this stage, the data is stored in the first memory 4 as described above.
Since the empty cell is sent from 4, the step S4 makes a NO determination and continues writing the data 4 to the second memory 45.

By discarding data and sending empty cells in this way, it is possible to eliminate the influence on the station side of the jitter caused by the time shift from the regular position of the clock of the transmission system forward in time. Next, the case where the jitter of the clock of the transmission system is caused by the backward shift in time from the normal position will be described with reference to FIG. In (a) of FIG. 8, a signal is transmitted from the left side to the right side in the receiving system. The FIFO 41 at the cell end is supplied with the transmission system clock having the frequency CL1 and the in-station clock having the frequency CL0. For example, the clock CL1 of the transmission system shifts backward at time t3 ″ with respect to the regular time t3, and the interval between time t2 and time t3 ″ becomes longer and the interval between time t3 ″ and time t4 becomes shorter.
8B corresponds to the time t2 in FIG. 8A, the data 1 for one cell length is written in the first memory 44 in step S2 of the flowchart, and the second memory in step S2. The process moves to writing the next data of 45. Since the memory to be written in is the second memory 45 and the memory to be read in is the first memory 44 in step S4, the determination is NO, and the data 2 is written to the second memory 45.

Next, FIG. 8C corresponds to the time t3 in FIG. 8A, the reading of the data 1 from the first memory 44 is completed, and the data transmission of step S8 is completed. , In step S9, the next data reading is started. At this time, if the jitter of the clock of the transmission system deviates from the normal position backward in time and the time t3 ″ corresponding to the time t3 is delayed, the writing of the data 2 into the second memory 45 is not completed. Therefore, in step (d) of FIG. 8 corresponding to time t3 ″, the determination in step S7 is NO.
An empty cell is transmitted in step S10. At this point, writing of data 3 into the first memory 44 is started.

FIG. 8E corresponds to time t4 in FIG. 8A. At this point, the writing of the data 3 to the first memory 44 is completed, the reading of the empty cells from the second memory 45 is also completed, and then the reading of the data 2 is performed. Although the data 4 is written to the second memory 45, since the data 2 is read from the second memory 45 in step S4, one cell of data 4 is discarded in step S5. In this way, it is possible to eliminate the influence on the station side of the jitter caused by the time shift from the normal position of the clock of the transmission system to the rear side.

As described above, the stuff control for taking in and out the staff such as discarding cells and sending empty cells is executed to absorb speed matching, jitter, and wander. Next, the transmission system will be described with reference to FIG. The configuration of the transmission system is composed of a cell terminating unit 4, a POH terminating unit 3, a pointer terminating unit 2, and a section terminating unit 1 in this order from the receiving end to the transmission line as described in the receiving system. In the cell terminating unit 4, the full cell stream is converted into C-4 by the transmission format conversion or the cell length conversion for converting the container and the full cell stream. In the POH terminating unit 3, POH is added to this C-4 and VC is added. -4, a pointer is added to this VC-4 in the pointer terminating unit 2 to be AU-4, and the STM is used in the section terminating unit 1.
-1 is transmitted to the transmission line.

The configuration and flow chart of the termination section of the present invention described with reference to FIGS. 2 and 3 are the same for the transmission system although the signal flow direction is opposite. Therefore, here, a part different from the transmission system and the reception system will be described. As described above, the function of the receiving system in the cell termination section of the SDH interface circuit of the present invention is to remove the jitter and wander caused by the fluctuation of the clock generated only in the receiving system, while the function of the transmitting system is The purpose is to absorb the phase shift of the clock that occurs in the device.

With reference to FIG. 9, the function in the transmission system of absorbing the phase shift of the clock generated in the device will be described. The left side of the broken line in the figure is the transmission path side, and the right side is the device side. On the device side, for example, a clock source CLK of 150 MHz and L driven by this clock source CLK
There are SI1 and LSI2. LSI1 is the clock source CL
It operates at the same frequency of K, 150 MHz, and LSI2
Frequency 1 to process, for example, 8 parallel data
It operates at a frequency of 150/8 MHz obtained by dividing 50 MHz.

At this time, the frequency of the clock source CLK is 15
A phase shift occurs between the phase of 0 MHz and the data sent from the LSI 2 at the frequency of 150/8 MHz due to the clock slack in the device. Therefore, the function of the transmission system in the cell termination section of the SDH interface circuit of the present invention is to absorb the phase shift of the clock generated in the device, unlike the reception system.

[0052]

As described above, according to the present invention,
In the conventional SDH interface circuit, a large amount of information per frame is carried out by clock transfer and stuff control in the path termination portion which has a structure for speed matching and jitter, wander and frame phase difference absorption. It is possible to provide a SDH interface circuit excellent in simplification of memory capacity, gate scale, and hardware configuration by eliminating the drawback that the hardware configuration becomes complicated as memory capacity and gate scale increase.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an SDH interface circuit of the present invention.

FIG. 2 is a configuration diagram of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 3 is a flowchart of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 4 is a conceptual diagram for explaining a speed matching function of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 5 is a conceptual diagram for explaining the speed matching function of the cell termination unit of the SDH interface circuit of the present invention.

FIG. 6 is a conceptual diagram for explaining a speed matching function of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 7 is a conceptual diagram for explaining the function of absorbing jitter, wander, and frame phase difference in the cell termination portion of the SDH interface circuit of the present invention.

FIG. 8 is a conceptual diagram for explaining a function of absorbing jitter, wander, and frame phase difference at the cell end portion of the SDH interface circuit of the present invention.

FIG. 9 is a block diagram illustrating functions of a transmission system of the present invention.

FIG. 10 is a block diagram of a conventional SDH interface circuit.

FIG. 11 is a block diagram of speed matching of a conventional SDH interface circuit.

FIG. 12 is a block diagram of a conventional pointer conversion circuit.

[Explanation of symbols]

 1 Section Termination Unit 2 Pointer Termination Unit 3 POH Termination Unit 4 Cell Termination Unit 41 FIFO 42 Write Control Unit 43 Read Control Unit 44 First Memory 45 Second Memory 100 Clock Transfer Unit 101 Section Termination Unit 102 Pointer Termination Unit 103 POH Termination Unit Unit 104 Cell Termination Unit 110 VC Buffer 111 Input Control Unit 112 Stuff Judgment Unit 113 Output Control Unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 12/48

Claims (6)

[Claims] 1. A cell terminating unit for performing format conversion and cell length conversion, (b) means for introducing a transmission path clock and a local clock to the cell terminating unit, and (c) a frequency between the clocks. The cell terminating section is provided with (1) means for performing matching and (d) means for eliminating the phase shift of the clock, and (e) means for performing the frequency matching and means for eliminating the phase shift. An SDH interface circuit characterized by the above. 2. The cell terminating unit introduces (a) a first-in first-out memory for inputting input data and outputting output data, and (b) introducing either the transmission path clock or the intra-station clock, A write control unit for controlling writing in the first-in-first-out memory; and (c) a clock that is either the transmission path clock or the in-station clock and is different from the clock introduced into the write-control unit, The SDH interface circuit according to claim 1, further comprising a read control unit that controls reading of the memory. 3. The write control section, when a mismatch occurs between input data input to the cell termination section and output output data due to a frequency or phase shift between the transmission path clock and a local clock, The SDH interface circuit according to claim 2, wherein the data for one cell length is discarded. 4. The read control unit, when a mismatch occurs between input data input to the cell termination unit and output data output due to a difference in frequency or phase between the transmission path clock and the internal clock, The SDH interface circuit according to claim 2, which transmits an empty cell. 5. The SDH interface circuit according to claim 1, wherein the phase shift is jitter or wander generated in a transmission line. 6. The S according to claim 1, wherein the phase shift is caused by clock misalignment in the station.
DH interface circuit.