JPH02226831A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency and reliability by recovering an FiFo memory without resetting it by using a redundancy signal called a cell head discrimination signal, and precluding a data slip due to the frequency difference between two clocks. CONSTITUTION:When the cell head discrimination signal RHC is not at the position where a read frame synchronizing signal RFRM should originally be, a read clock RCLK is outputted without resetting the FiFo memory 200 until a next cell head discrimination signal RHC is found to control the transmission of read data RDATA during period to a low-order device 101. Read timing, on the other hand, is controlled so that the data slip due to the frequency difference between the two clocks CLK is not generated. Consequently, the circuit transmission efficiency and reliability which are reciprocal can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to first-in, first-out
) This invention relates to a synchronization circuit for an asynchronous data transmission device using memory.

[Prior Art] FIGS. 2 and 3 show an example of a conventional asynchronous data conversion circuit disclosed in Japanese Patent Application Laid-Open No. 140529/1982, and
? Using the iFo memory 1, data writing and reading operations can be performed independently using different clocks.

Each received burst data RVD T includes a signal called a unique word UW, and when this unique word UW is detected, the unique word sets the flip-flop 2 and resets the FiFo memory l. A detection pulse UWP is output at the previous stage. After that, following the unique word UW (data D, ATA
The column is successfully written to the FiFo memory l.

Reading of data DATA from the FIFo memory 1 is performed by the local clock LCCK of the own station, but the read clock RDCK is stopped by the output of the flip 70 block 2 set by the unique word detection pulse LJWP. Signal U after which the detection pulse is delayed for a certain period of time
The flip-flop 2 is reset by WDP, and data DATA is read out.

This transmission method uses a highly redundant synchronizing signal SY and a unique word UW, drops these during reading, and reads only data DATA. Therefore, it is effective when the amount of communication is small and the added synchronization bits and overhead information can be lost.

Further, malfunctions of the FiFo memory 1, such as idle reading and erroneous writing, can be minimized because the FiFo memory 1 can be reset for each burst data.

[Problems to be Solved by the Invention] In the conventional configuration, as described above, in addition to the data string, redundancy of a frame synchronization signal and a unique word is required. Therefore, in controlling the FiFo memory using the redundant signal, it is possible to synchronize asynchronous devices and recover from malfunctions such as noise.

However, since all received data cannot be used as effective information, there is a drawback that transmission efficiency is reduced.

To solve this problem, contrary to the above-mentioned conventional technology, a circuit that does not use redundant signals may be considered in order to pursue transmission efficiency.

However, in such a circuit, if the frame synchronization is disturbed by disturbances such as noise and the Ii'i FO memory malfunctions, there is no way to recover other than to reset and initialize the FiFO memory. However, there was a drawback that all data in the FiFo memory would be lost.

The purpose of the present invention is to eliminate the tradeoff problem that transmission efficiency decreases when redundant signals are used to recover from malfunctions, while reliability decreases when redundant signals are not used to pursue transmission efficiency. An object of the present invention is to provide a highly efficient and highly reliable synchronization circuit.

[Means for Solving the Problems] The synchronization circuit of the present invention uses a FiFo memory that operates with two clocks, a write clock and a read clock, which have approximately the same period, to communicate frame data called cells. In the synchronization circuit between asynchronous devices, a circuit that uses the write frame synchronization signal of the upper asynchronous device to generate a cell head identification signal and writes this to the FiFo memory, and a circuit that reads data from the FiFo memory. A circuit that outputs a read clock until the next cell start identification signal is output when the cell start identification signal is not at the same position as the read frame synchronization signal sent from the lower asynchronous device, and this read clock. A circuit that suppresses the sending of read data to lower-order devices while outputting a read frame synchronization signal, and a circuit that stops outputting a read clock when the data stored in the FiFo memory is less than a predetermined amount when sending a read frame synchronization signal. The present invention also includes a circuit for preventing data slippage due to the frequency difference between the two clocks.

[Operation] When a write frame synchronization signal is sent from the upper asynchronous device, a cell start identification signal is generated at the same position as the start bit of the frame data also sent from the asynchronous device, and this cell start identification signal is used as the frame data. FiF in parallel with data.

written to memory.

When reading data from the F i F o memory, the header identification signal added at the time of writing is also read, but if the read cell header identification signal is not at the same position as the read frame synchronization signal sent from the lower asynchronous device. In this case, the read clock is outputted and the data read operation continues until the next cell head identification signal is output without resetting the FiFo memory.

The read data while this read clock is output is stopped from being sent to the lower device by the suppression circuit, but is held within the suppression circuit without being discarded.

When the next cell head identification signal is found, the read clock is stopped, and when the next read frame synchronization signal comes, the read clock is output again and the data is stored in the FtFo memory together with the data held in the suppression circuit. Data is transferred to the lower device.

Additionally, in these cases 1, when the read frame synchronization signal is sent and the data stored in the FiFo memory is less than the predetermined 1, the output of the read clock stops and the above two clocks Data slip due to frequency difference is prevented.

If the amount of data m exceeds the data slip prevention margin, a read clock is output from the time the read frame synchronization signal is sent, and the data is read from the FFo memory.

[Example 7] Examples of the present invention will be described below with reference to FIGS. 1 and 4 to 5.

FIG. 1 is a block diagram showing an example of an asynchronous matching circuit according to the present invention. Although a case of unidirectional communication in which data is transferred from a higher-level device to a lower-level device is shown here, it is also possible to add another same circuit that transfers data in the opposite direction to achieve full duplex.

The upper bag m1oo is the FiFo memory 2 which has human output data IN+2 with redundancy of 1 bit in the data bus width N bits.
Connected to 00.

Same as the write frame sent from the upper bag M100.

A synchronization signal obtained by extracting the period signal via the cell monitor 201 and the upper clock CLK also output from the host device 100 are input to the AND circuit 204, and the write clock W synchronized with the write frame synchronization signal WFRM is inputted to the AND circuit 204.
CLK is output.

The write data W D A i' A from the host device 100 is F i F by this write clock WCLK.
.

written to memory 200.

The cell monitor 201 forms a cell head identification signal WHO from the write data WDA i'Δ and the write frame synchronization signal WFRM, and uses the formed cell head identification signal WF.
■F i F o via 1 bit line with redundant C
Output to memory 200.

An output corresponding to the data width of the FiFo memory 200 is connected to the lower device 101 via an output buffer gate 203. The output buffer gate 203 suppresses the read data RDATA so as not to send it to the lower device 101 when the gate signal G is not present. Read data RD A from FiFo memory 200 when gate signal G is present
TA is sent to the lower device 101, but when there is no gate signal, the sending is stopped and 1 byte worth of data can be held. In other words, suppression means both the function of stopping transmission of data and the function of holding data.

The reason why the output buffer gate 203 is provided with a holding function is that once data is read in the FiFo memory, the read data does not remain in the FiFo memory.

A control circuit 202 is further interposed between the FiFo memory 200 and the lower-order device 101.

This control circuit 202 controls the read frame synchronization signal RFRM sent from the lower device 101 and the lower clock CLK.
and the cell destination rJfI identification signal RHC added when writing from the FiFo memory 200.

The read clock RC is synchronized with the read frame synchronization signal RFRM based on the empty signal EF (empty flag) that is output when the data in the FiFo memory 200 is empty.
LK and gate signal G are generated, and F i I? o Controls the reading of read data RD AT A from the memory 200 and controls the output buffer gate 203.

The cell monitor 201 and the control path 202 can be constructed from logic circuits, especially integrated circuits.

FIG. 4 shows an example of a frame data structure called a cell transferred by the above circuit.

The cell length of this fixed length cell may be any value within the system using this circuit. Headers I-i and t in the illustrated example
The size of the UU field F is determined by the system in which the cell is used. The header section H in the figure includes information as to whether the contents of the information field F are valid or not, and valid cells are transmitted to the lower device 101. Now,
In the circuit shown in FIG. 1, the entire cell including header information is written to the FiFo memory 200 using the write clock WCLK only when the host device 100 synchronizes with the write frame synchronization signal WFRM and sends a valid cell. . When writing the first byte of a cell, the cell monitor 201 to which the write data WDATA and the write frame synchronization signal WFRM are input sends a signal indicating the cell start to the redundant bit (N+1) of the FiFo memory 200, that is, cell start identification. Write the signal WHO at the same time.

Next, the cell data written in the FiFo memory 200 is transferred to the read frame synchronization signal RF of the lower device fK101.
The data is read using the RM and the lower clock CLK, and at this time the control circuit 202 performs functional control that satisfies the following conditions (1) to (2). Note that the following explanation will be made along the timing diagram of FIG. 5, which is divided into sections a to d and a normal recovery section.

■If data DATA is not stored in the FiFo memory 200, the empty signal EFI is sent from the FiFo memory 200.
is output. When the control circuit 202 detects this empty signal EFI, the control circuit 202 outputs the read clock R to the FiFo memory 200.
CLK transmission is stopped (section a in FIG. 5).

■To the data DAT in the FiFo memory 200 (DA
'I' A l ) is accumulated in the lower device 10.
When the control circuit 202 receives the read frame synchronization signal RF RM 2 from the read frame synchronization signal RF RM 2 from the FiI? o If the data is not stored in the memory 200, no data is read in that read frame period (section b in FIG. 5).

0th order read frame synchronization signal RI? If n bytes or more of data is accumulated in the FiFo memory 200 when RM 3 is received, the read clock RCL
K is sent, and the read data RDATA1 is read from the FiFo memory 200. At this time, the timing position of the cell head identification signal RHC1 written into the redundant bit at the time of writing is checked. As a result of checking, if the cell head identification signal RHCI is located at the same position as the read frame synchronization signal RFRM3 sent from the lower device lot, the control circuit 202 sends the gate signal c1 to the output buffer gate 203, and gate 203
Open and send data C to the lower device 101.
1 (section C in Figure 5).

■After Sono RD A T A 21: Continue RDATA
3, when checking the cell head identification signal RHC3, if the cell head identification signal RHC3 is not located at the same position as the read frame synchronization signal RFRM6 sent from the lower device 101 due to a malfunction due to noise or the like, The control circuit 202 determines that the frame is out of synchronization,
The output buffer gate 203 is closed to suppress sending of data to the lower device 101.

I here? Data DAT in I F o memory 200
If A has been accumulated (determined by the empty signal EF), the read clock "RCLK" is continuously output until the cell head identification signal RHC3 is found, and the data data3 (RD A 'I' A
3), and the cell start identification signal R is read out.
)l When C3 is found, stop the read clock RCLK. Then, the next read frame synchronization signal RFRM
When 7 comes, the read clock RCLK is outputted again and the normal operation returns.

In this case, the data data3 held in the output buffer gate 203 is sent to the lower device 101 in a state where it is added to the beginning of the data OD A 'r'' A3 read out during normal operation (see section 5). Ifll
d).

Also, during reading from the FiFo memory 200, the FiFo
When the memory 200 becomes empty, the clock RC
LK stops and returns to its initial state.

As described above, according to this embodiment, even if the data DATA is stored in the F i FO memory 200, the read frame synchronization signal RFRM2 from the lower device lot
When the control circuit 202 receives data, if data of n bytes or more, which is a margin for preventing one bit slip, has not been accumulated in the FiFo memory 200, no data is read in that read frame period. Therefore, data slip due to the frequency difference between the two clocks CLK between the upper device lOO and the lower device 101 can be effectively prevented, and bit synchronization can be established.

Furthermore, if the cell head identification signal RHC3 is not at the same position as the read frame synchronization signal RFRM6 sent from the lower-order device 101, the control circuit 202 determines that the frame synchronization is out of order, and adds the read frame synchronization signal RFRM6 without resetting the FiFO memory 200. FiF continues until the cell head identification signal Rl-IC is found.

Reads the memory 200 and outputs the buffer gate 2.
03 to suppress sending of read data to the lower-order device 101. And the next read frame synchronization signal RFRM
When , the suppression is released and the output buffer gate 203
The data RDATA stored in the FiFo memory 200 along with the data held in the lower device 1
01 to return to normal operation, even if frame synchronization is disturbed due to disturbances such as noise, frame synchronization can be re-established in a short time until the next read L frame synchronization signal. Moreover, since the data held in the output buffer gate 203 is sent to the lower device 101 together with the subsequent data in synchronization with the next read frame synchronization signal, data that would otherwise be erroneous after a malfunction is transmitted in synchronization with the next read frame synchronization signal. can be repaired and frame synchronization can be established.

In this way, in this embodiment, a redundant signal called a cell head identification signal is used to restore the FIFo memory without resetting it, so that disturbances such as noise can disturb the frame synchronization and cause the FIFo memory to malfunction. When a redundant signal is not used, there is no means of recovery other than resetting and initializing the FtFo memory, and there is no problem such as the loss of all data in the FtFo memory.

Furthermore, instead of adding the cell start identification signal to determine frame synchronization loss to the data string, it is added to the redundant Ebisoto in the data bus width, so even if the cell start identification signal is used, the data itself is not redundant (therefore, all received data can be used as valid information, so transmission efficiency does not decrease.

[Effects of the invention] This has been described above. According to the present invention, when the cell head identification signal does not arrive at the intended position of the read frame synchronization signal, the read clock continues until the next cell head identification signal is output without resetting the FiFo memory. While controlling the read data to be output to the lower-level device during that time, the read timing is controlled to prevent data slips due to the frequency difference between the two clocks, thereby reducing the conflicting effects of circuit transmission efficiency and reliability. In addition, data loss can be effectively prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronization circuit according to the present invention, FIG. 2 is a block diagram showing a conventional example of the synchronization circuit, and FIG. 3 is a time chart diagram explaining the operation of FIG. 2. FIG. 4 is a configuration diagram of an example of a fixed length cell used in this embodiment, and FIG. 5 is a time chart 1 explaining the operation of FIG. 1.
・It is a diagram. 100 and 101 are asynchronous devices such as an upper device and a lower device, 200 is a FiFo memory (first-in, first-out memory), 201 is a cell monitor as a circuit for providing a cell head identification bit, and 202 is a circuit for providing a next cell head identification signal. 203 is an output buffer gate as a circuit for suppressing data; WCLK is a write clock;
RCLK is the read clock, WFRM is the write frame synchronization signal, RFRM is the read frame synchronization signal, WHO
, RHC are cell head identification signals during writing and reading.

Claims (1)

[Claims] In a synchronization circuit that performs bit and frame synchronization of frame data transmission between asynchronous devices using a first-in, first-out memory, a cell written to the first-in, first-out memory by a write clock and A circuit that uses a write frame synchronization signal to provide a cell start identification bit in the called frame data, and a circuit that uses a write frame synchronization signal to provide a cell start identification bit, and when the cell start identification signal is not at the position of the read frame synchronization signal, the read clock is activated until the next cell start identification signal is found. It is equipped with a circuit for outputting data, a circuit for suppressing the read data so as not to send it to the lower device, and a circuit for controlling the read timing to prevent data slips due to the frequency difference between the write clock and the read clock. A synchronization circuit characterized by: