JPH05244126A - Line timing switching control system - Google Patents

Abstract

PURPOSE:To curtail the number of signal lines, and to miniaturize the device, with regard to the line timing switching control system at the time of fault in an optical transmission system, etc. CONSTITUTION:The system is provided with a receiving part 4 having a timing extracting part 1, an alarm detecting part 2 and a timing sending-out part 3, a timing control part 8 having a detecting part 5, a selector 6 and a selector control part 7, and a transmitting part 9. When it is detected that a receiving signal is disconnected by the alarm detecting part 2, a line timing signal passing trough one piece of signal line from the line timing sending-out part 3 is fixed to '1' (or '0'), and when a line alarm display signal is detected, it is fixed to '0' (or '1'), the detecting part 5 of the timing control part 8 detects abnormality of '1' or '0' fixation of the line timing signal, and the selector control part 7 controls a selector 6, switches to an internal timing signal or an external reference timing signal from the line timing signal, and applies it as a master clock signal MCLK to the transmitting part 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line timing switching control system at the time of a failure in an optical transmission system or the like.
In a synchronous network optical transmission system, the line timing signal extracted from the received signal is used as the master clock signal of the transmitter. Since the signal cannot be extracted, it is switched to the internal timing signal or the external reference timing signal. It is desired to reduce the number of signal lines for the timing control unit that switches such timing signals to simplify the configuration.

[0002]

2. Description of the Related Art In an optical transmission system, for example, as shown in FIG. 3A, terminal equipment (LET) 41, 42 is connected by optical transmission lines 43, 44 to transmit an optical signal. If the distance between the terminal devices 41 and 42 is long, a relay device is provided. Further, as shown in FIG. 3B, an arbitrary number of insertion / removal devices (AD
M; Add Drop Multiplexer) 45, 46 are connected,
In the terminal devices 41 and 42, high speed data is processed and transmitted through the optical transmission lines 43 and 44, and in the insertion / removal devices 45 and 46, a predetermined channel in the high speed data is dropped and the medium speed data is transmitted. There is also known an optical transmission system in which data or medium speed data is inserted into a predetermined channel in high speed data. Further, as a system for synchronously transmitting such an optical signal, SONET (Synchronous Optical Network)
k) is known.

FIG. 4 is an explanatory view of the insertion / removal section, and shows the schematic configuration of the insertion / removal devices 45 and 46 in FIG. 3, in which 47 and 48 are high-speed channel sections, 49 is a medium-speed channel section, and 50 is timing. A control unit, 51 is a selector (SEL), 52 is an internal clock generation unit, and 53 is a path switch unit (PSW).

A timing signal is required to form a synchronous network, and in an optical transmission system, a timing signal is generally extracted from an optical signal. Therefore,
Also in the high-speed channel units 47 and 48 and the medium-speed channel unit 49, the timing signal is extracted from the received signal. This timing signal is referred to as a line timing signal. The selector 51 of the timing control unit 50 receives the line timing signal and the internal timing signal from the internal clock generation unit 52 or the external reference timing signal BITS from the high precision oscillator. In addition, when the line timing signal is normal, one of the line timing signals is selected and becomes the master clock signal MCLK. The high-speed channel units 47, 48 and the medium-speed channel unit 49 use the master clock signal MCLK to send out the optical signal.

In the event of an abnormality such as disconnection of a received signal, the selector 51 of the timing control unit 50 is controlled by a detection signal from an alarm detection unit (not shown), the internal timing signal or the external reference timing signal BITS is selected, and the master clock is selected. It becomes the signal MCLK.

FIG. 5 is an explanatory view of a conventional example. 61 is a receiving unit, 62 is a transmitting unit, 63 is a timing control unit, 64 is a photoelectric conversion unit, 65 is a descrambler, 66 is a synchronizing unit, 67.
Is a section overhead dropper, 68 is a line overhead dropper, 69 is a byte demultiplexer, 70 is an alarm detection unit, 71 is a memory, 72 is a pointer processing unit, 73 is a line overhead inserter, 74 is a section overhead inserter, 7
5 is a scrambler, 76 is an electro-optical converter, 77 is a phase comparator, 78 is a voltage controlled crystal oscillator, 79 is a selector controller, 80 is a selector, 81 is an internal clock generator, 82
Is an OR circuit.

In the receiver 61, an optical signal received through the optical transmission line is converted into an electric signal by a photoelectric converter 64 including a photodiode and added to a descrambler 65, and timing is detected by peak detection. The signal is extracted and supplied to each unit as a clock signal. It is also added to the timing control unit 63 as a line timing signal LT. The descrambler 65 performs descrambling, the synchronization unit 66 synchronizes the frame, the section overhead dropper 67 removes the section overhead SOH from the frame, and the next line overhead dropper 68 removes it. Remove the line overhead LOH in the frame. Then, the byte demultiplexer 69 transfers the data byte by byte to the transmitter 62.

In the transmitter 62, the pointer is temporarily stored in the memory 71, the pointer is replaced by the pointer processor 72, the line overhead LOH is inserted in the line overhead inserter 73, and the section overhead inserter 74 is inserted. At this time, a section overhead SOH is inserted to form a frame, scrambled at a scrambler 75, converted into an optical signal at an electro-optical conversion unit 76 composed of a semiconductor laser or the like, and transmitted to an optical transmission line. ..

The timing control section 63 receives the line timing signal LT from the transmitting section 61 and the internal clock generating section 8.
The internal timing signal or the external reference timing signal BITS from 1 is input to the selector 80, and the selector 80 is controlled by the selector control unit 81. Alarm detector 7
0 indicates a signal loss detection signal LOS (Loss of Signal) or a line alarm display detection signal LAIS (Line Alarm) by detecting a reception signal loss or a line alarm display signal.
Indication Signal) is added to the timing control unit 63, and in a normal state, the selector control unit 79 controls the selector 80 to selectively output the line timing signal LT, which is sent to the transmission unit 62 as a master clock signal MCLK. Add. The transmission unit 62 includes a phase locked loop circuit that compares the phase of the master clock signal MCLK with the clock signal from the voltage controlled crystal oscillator 78 by the phase comparator 77 and controls the voltage controlled crystal oscillator 78 by the comparison output. , A clock signal that is phase-synchronized with the master clock signal MCLK is formed and supplied to each unit.

Further, the selector control unit 79 of the timing control unit 63 receives the signal disconnection detection signal LOS or the line alarm display detection signal LAIS from the alarm detection unit 70 of the reception unit 61.
, The line timing signal LT
From the internal timing signal to the external reference timing signal BITS. Also, when the failure is recovered, or when the signal loss detection signal LOS is recovered,
The control is switched back after a guard time of 10 to 20 seconds, and when the line alarm display detection signal LAIS is restored, the control is switched back immediately. Accordingly, the selector control unit 79 inputs the signal disconnection detection signal LOS and the line alarm display detection signal LAIS via the OR circuit 82, and also inputs that the alarm at that time is the line alarm display detection signal LAIS. It shows the configuration. Such a switching condition is the TA for SONET.
-253.

[0011]

A line timing signal LT is provided between the receiving section 61 and the timing control section 63.
At least three signal lines, that is, a signal line for a signal, a signal line for a signal loss detection signal LOS, and a signal line for a line alarm display detection signal LAIS are required. In addition to the receiving unit 61 and the transmitting unit 62 shown in FIG. 5, an arbitrary number of medium speed channel units 49 are provided as shown in FIG. 4, and the high speed channel units 47 and 48 and the medium speed channel units are provided. Since each of 49 includes a receiving section, the number of signal lines with the timing control section is large.
Therefore, there is a drawback that the device scale becomes large. An object of the present invention is to reduce the number of signal lines and miniaturize the device.

[0012]

A timing switching control system according to the present invention will be described with reference to FIG. 1. A timing extraction unit 1, an alarm detection unit 2, and a line timing transmission unit 3 will be described.
And a detector 5 for detecting an abnormality based on the line timing signal from the line timing transmitter 3.
And a timing control section 8 having a selector 6 for selecting a line timing signal and an internal timing signal or an external reference timing signal, and a selector control section 7 for controlling the selector 6, and a timing signal from the timing control section 8. Is used as a master clock signal MCLK, and the timing sending unit 3 fixes the line timing signal to a high level (or low level) with respect to the signal disconnection detection signal by the alarm detection unit 2 to detect an alarm. The line alarm display detection signal from the unit 2 is sent as a fixed low level (or high level), and the timing control unit 8 determines whether the line timing signal from the timing sending unit 3 is fixed at a high level or a fixed low level. , Signal disconnection detection signal or line alarm display detection signal Detected by the detection unit 5 controls the selector 6 by the selector control section 7 based on the detection result, the transmitting unit 9 performs switching between the line timing signal and the internal timing signal or the external reference timing signal
In addition to.

[0013]

The function of the line timing transmitting section 2 is to apply the line timing signal extracted by the receiving section 4 to the timing control section 8
In addition, when the alarm detector 2 detects a signal break or a line alarm display, the line timing signal is forcibly fixed to a high level or a low level. For example, if the signal disconnection detection signal is fixed at high level, the line alarm display detection signal is fixed at low level. Therefore, the timing control unit 8 receives the line timing signal in the normal state and detects the signal disconnection when the line timing signal is fixed to the high level, and detects the line alarm display when the line timing signal is fixed to the low level. Then, the line timing signal is immediately switched to the internal timing signal or the external reference timing signal. And at the time of failure recovery, based on the regulations,
In the case of alarm display detection, it is possible to switch back immediately, and in the case of signal disconnection detection, it is possible to switch back after 10 to 20 seconds. That is, the line timing signal, the signal disconnection detection signal, and the alarm display detection signal can be transferred between the receiving unit 4 and the timing control unit 8 by one signal line.

[0014]

EXAMPLE FIG. 2 is an explanatory view of an example of the present invention.
Is a receiving unit, 12 is a transmitting unit, 13 is a timing control unit, 1
4 is a photoelectric conversion unit, 15 is a descrambler, 16 is a synchronization unit, 17 is a section overhead dropper, and 18
Is a line overhead dropper, 19 is a byte demultiplexer, 20 is an alarm detector, 21 is a memory,
22 is a pointer processing unit, 23 is a line overhead
An inserter, 24 is a section overhead inserter, 25 is a scrambler, 26 is an electro-optical conversion unit, 27 is a phase comparator, 28 is a voltage controlled crystal oscillator, 29 is a selector control unit, 30 is a selector, 31 is an internal clock generation unit, 32 is an AND circuit, 33 is an abnormality detection unit, 34 is a line timing transmission unit, 35 is an inhibit gate circuit,
Reference numeral 36 is an OR circuit, and 37 is a medium speed channel section.

The photoelectric conversion unit 14 of the reception unit 11 corresponds to the timing extraction unit 1 of FIG. 1, and the portions having the same names as those of FIG. 1 correspond to the same portions. Further, the photoelectric conversion unit 1 of the receiving unit 11
4, each of the descrambler 15, the synchronization unit 16, the section overhead dropper 17, the line overhead dropper 18, and the byte demultiplexer 19 has the same configuration and operation as the above-mentioned conventional receiving unit. Similarly to the conventional example, the alarm detection unit 20 is also connected to the photoelectric conversion unit 14 via a signal (not shown) and detects a reception signal disconnection or a line alarm display signal, and S1 is a signal disconnection detection. OR output signal of the signal and the line alarm display detection signal, S2 is the line alarm display detection signal, and S3 is the timing sending unit 34 of the receiving unit 11.
From FIG. Therefore, when the signals S1 and S2 are “0”, that is, in the normal state, the line timing signal extracted by the photoelectric conversion unit 14 is timing controlled via the inhibit gate circuit 35 and the AND circuit 36 of the line timing transmission unit 34. It is transferred to the section 13.

When the alarm detector 20 detects a signal disconnection, the signal S1 becomes "1", so that the inhibit gate circuit 35 inhibits the line timing signal and the line alarm display is not detected at that time. , The signal S2 is "0", and the output signal S3 of the OR circuit 36 is fixed to the low level ("0"). When the alarm detector 20 detects the line alarm display, the signal S1 becomes "1" and the signal S2 also becomes "1".
Becomes Therefore, the output signal S3 of the OR circuit 36 is fixed at the high level (“1”).

When the signal S3 alternately repeats the high level and the low level at a predetermined timing, the detecting section 33 of the timing control section 13 determines that the line timing signal is normally transferred, and outputs the line timing signal. The signal is set to "0". When the signal S3 is fixed at low level or fixed at high level, it is determined that the signal disconnection detection signal or the line alarm display detection signal is output, and the output signal is set to "1".

When the output signal of the detector 33 is "0",
The selector control unit 32 determines that it is normal and selects the selector 3
The line timing signal is controlled to be selectively output from 0, and the selected output signal is added to the transmission unit 12 as the master clock signal MCLK. When the output signal of the detection unit 33 is "1", the selector control unit 32 determines that there is an abnormality and performs switching control so that the selector 30 selectively outputs the internal timing signal or the external reference timing signal. The selected output signal is applied to the transmitter 12 as the master clock signal MCLK. At that time, the output signal of the AND circuit 32 becomes "0" for the signal disconnection detection signal and becomes "1" for the line alarm display detection signal. Therefore, the selector control unit 29 selects the selector 30 according to which detection signal.
Can be controlled.

When the fault is recovered and the signal S3 is restored to the original line timing signal, the detecting section 33 detects it and sets the output signal to "0". When the signal disconnection detection signal is restored, the selector control unit 29 immediately selects the selector 30.
Control to switch back so as to selectively output the line timing signal. When the line alarm display detection signal is restored, start the timer etc. according to the above-mentioned rules and
After 0 to 20 seconds have passed, the line timing signal is switched back so as to be selectively output.

The configuration of the memory 21, pointer processing unit 22, line overhead inserter 23, section overhead inserter 24, scrambler 25, electro-optical conversion unit 26, phase comparator 27, voltage controlled crystal oscillator 28 of the transmission unit 12 and The operation is the same as the above-mentioned conventional example, and each unit is operated by the clock signal phase-synchronized with the master clock signal MCLK from the timing control unit 13.

The above-described embodiment shows a case where the signal S3 applied from the line timing transmission section 34 to the timing control section 13 is fixed at a low level when a signal break is detected, and is fixed at a high level when a line alarm display signal is detected. However, by changing the logical configuration of the alarm detection unit 20 or the line timing transmission unit 34, it is possible to fix the high level when the signal disconnection is detected and fix the low level when the line alarm display signal is detected. Also in the medium speed channel unit 37, the line timing signal extracted from the received signal is transferred to the timing control unit 13, and the line timing signal is fixed to a low level or high when the signal disconnection is detected or the line alarm display signal is detected. It is transferred as a fixed level.

[0022]

As described above, according to the present invention, the line timing signal extracted by the timing extracting unit 1 of the receiving unit 4 is transferred to the timing control unit 9, and the line timing signal from the timing control unit 8 is normally transmitted. A signal is selected to be the master clock signal MCLK of the transmission unit 9, the line timing signal is fixed to high level or low level for the signal detection signal by the alarm detection unit 2, and the line timing signal is set to low for the line alarm display detection signal. Since the level or the high level is fixed, the number of signal lines between the receiver 4 and the timing controller 8 can be one. That is, even in a device having a plurality of high-speed channel units and medium-speed channel units, transfer of line timing signals between respective receiving units and the timing control unit 8, transfer of signal loss detection signals, and line Since the transfer of the alarm display detection signal can be performed by one signal line, there is an advantage that the installation space of the signal line can be reduced and the device can be downsized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of the present invention.

FIG. 3 is an explanatory diagram of an optical transmission system.

FIG. 4 is an explanatory diagram of an insertion / removal unit.

FIG. 5 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Timing Extraction Section 2 Alarm Detection Section 3 Line Timing Transmission Section 4 Reception Section 5 Detection Section 6 Selector 7 Selector Control Section 8 Timing Control Section 9 Transmission Section

Claims (1)

[Claims] 1. A receiver (4) having a timing extractor (1), an alarm detector (2), and a line timing transmitter (3), and a line timing from the line timing transmitter (3). A detection unit (5) that performs abnormality detection based on a signal, a selector (6) that selects the line timing signal and an internal timing signal or an external reference timing signal, and a selector control unit that controls the selector (6) ( A timing control unit (8) having a timing control unit (7) and a transmission unit (9) for performing a transmission process using the timing signal from the timing control unit (8) as a master clock signal, and the timing transmission unit (3) , The line timing signal is fixed to a high level (or low level) for the signal disconnection detection signal by the alarm detection unit (2),
The line alarm display detection signal from the alarm detection unit (2) is sent as a fixed low level (or high level), and the timing control unit (8) outputs the line timing signal from the timing sending unit (3). The detection unit (5) detects whether the signal is a signal disconnection detection signal or a line alarm display detection signal depending on whether the high level is fixed or the low level is fixed, and the selector (6) is selected by the selector control unit (7) based on the detection result. ) Is controlled to switch between the line timing signal and the internal timing signal or the external reference timing signal, and the line timing signal is added to the transmitting unit (9).