JPH05243789A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPH05243789A
JPH05243789A JP4078989A JP7898992A JPH05243789A JP H05243789 A JPH05243789 A JP H05243789A JP 4078989 A JP4078989 A JP 4078989A JP 7898992 A JP7898992 A JP 7898992A JP H05243789 A JPH05243789 A JP H05243789A
Authority
JP
Japan
Prior art keywords
substrate
substrates
wiring
function trimming
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4078989A
Other languages
Japanese (ja)
Inventor
Kunio Kumagai
邦生 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP4078989A priority Critical patent/JPH05243789A/en
Publication of JPH05243789A publication Critical patent/JPH05243789A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To perform function trimming efficiently under a condition that a plurality of substrates are integrally connected to form a substrate assembly. CONSTITUTION:A terminal part and a wiring part 4 are formed on the surface of substrates 1-18 in a substrate assembly 1 where a plurality of substrates 11-18 and a disposal substrate 19 are connected in one piece and at the same time the wiring part 4 or terminal parts which need to be connected at the time of later function trimming are connected mutually through the wiring parts 4 and 10 on the surface adjacent other substrates 11-18 or the disposal substrate 19 which is devided later over the substrates 11-18. Then, function trimming is performed on the substrates 11-18 in the state of the assembly substrate 1 and then the substrate assembly 1 is mounted to a lead frame after it is divided into the substrates 11-18 and the disposal substrate 19 after function trimming is completed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、機能検査を行ないつつ
抵抗を所定の値に設定するファンクショントリミング工
程を有する混成集積回路の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a hybrid integrated circuit having a function trimming step of setting a resistance to a predetermined value while performing a function test.

【0002】[0002]

【従来の技術】近年、混成集積回路では、ある回路ブロ
ックの機能を所定値に入れるため、電源電圧を印加し回
路ブロックを動作状態にしながら、ファンクショントリ
ミングを実施し調整を行うことが多くなっている。この
混成集積回路の製造方法としては、図3に示す如くセラ
ミック基板等の集合基板1の上に印刷抵抗及び導体の回
路パターンを形成し、表面又は裏面にトランジスタ,コ
ンデンサ等の各種電子部品(図示せず)を搭載し、分割
した基板にリードフレームを半田付けした後、印刷抵抗
のファンクショントリミングを実施し、次に樹脂モール
ド等で外装し、製品化することが一般的である。
2. Description of the Related Art In recent years, in a hybrid integrated circuit, in order to put a function of a certain circuit block into a predetermined value, function trimming is often performed while performing a function trimming while applying a power supply voltage to bring the circuit block into an operating state. There is. As a method of manufacturing this hybrid integrated circuit, as shown in FIG. 3, a circuit pattern of printed resistors and conductors is formed on a collective substrate 1 such as a ceramic substrate, and various electronic components such as transistors and capacitors are formed on the front or back surface (see FIG. (Not shown) is mounted, the lead frame is soldered to the divided substrates, the function trimming of the printing resistor is performed, and then the resin is externally packaged with a resin mold or the like for commercialization.

【0003】例えば、ファンクショントリミングに際
し、図4に示したように基板11の表面, 裏面で端子部
2,3のとを接続しておく必要がある場合には、配
線部5を介すると共に、分割された各個片の基板にリー
ドフレームを取付け、表,裏面の端子部2,3を接続し
ていた(以下、第1の従来方法と呼ぶ)。
For example, in the case of function trimming, when it is necessary to connect the terminals 2 and 3 on the front surface and the back surface of the substrate 11 as shown in FIG. A lead frame was attached to each of the individual substrates thus prepared, and the terminal portions 2 and 3 on the front and back surfaces were connected (hereinafter referred to as a first conventional method).

【0004】また、この第1の従来方法と異なり、集合
基板の状態でファンクショントリミングを行う別の態様
としては、スルーホールを使用する方法がある。図4の
場合では、端子部2,3のとの周辺導体部をスルー
ホールにて接続することにより、集合基板の状態で表面
側一方向からのファンクショントリミングが可能となる
(以下、第2の従来方法と呼ぶ)。
Further, unlike the first conventional method, there is a method of using a through hole as another mode for performing the function trimming in the state of the collective substrate. In the case of FIG. 4, by connecting the peripheral conductor portions of the terminal portions 2 and 3 with through holes, it is possible to perform function trimming from one direction on the front surface side in the state of the assembled substrate (hereinafter, referred to as the second embodiment). Called the conventional method).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、第1の
従来方法では集合基板1の状態でリードフレームを取り
付けることが出来ないため、各基板に分割した後リード
フレームを取り付ける必要があり、その後の製造工程に
おいて作業性及び歩留りが悪いという課題があった。
However, since the lead frame cannot be attached in the state of the collective substrate 1 in the first conventional method, it is necessary to attach the lead frame after dividing into the respective substrates, and the subsequent manufacturing. There is a problem that workability and yield are poor in the process.

【0006】また第2の従来方法では、集合基板1の状
態でファンクショントリミング等の処理が可能となり、
その面では効率的であるが回路が複雑な場合、セラミッ
ク等からなる基板11に多数のスルーホールを形成しなけ
ればならず、大幅なコストアップが避けられないという
課題があった。
In the second conventional method, function trimming or the like can be performed in the state of the collective substrate 1,
In that respect, it is efficient, but when the circuit is complicated, it is necessary to form a large number of through holes in the substrate 11 made of ceramic or the like, which causes a problem that a large increase in cost cannot be avoided.

【0007】本発明はかかる課題に鑑みなされたもので
あって、基板を個片に分割する前の状態、即ち集合基板
の状態で、しかもスルーホールの形成を必要とすること
なく、ファンクショントリミングの実施が可能な混成集
積回路の製造方法を提供することを目的とする。
The present invention has been made in view of the above problems, and it is possible to perform function trimming in the state before dividing the substrate into individual pieces, that is, in the state of the collective substrate, and without forming through holes. An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that can be implemented.

【0008】[0008]

【課題を解決するための手段】本発明に係る混成集積回
路の製造方法は、複数の基板を一体的に配列形成した集
合基板に抵抗及び導体の回路パターンを形成し、電子部
品を搭載した後、集合基板の状態で前記各基板の電気回
路のファンクショントリミングを行う工程を含む混成集
積回路の製造方法において、ファンクショントリミング
時に接続する必要のある回路パターンの配線部同士を、
一の基板を越えて、後に切り離されるべき相隣する他の
基板表面にわたって形成した配線部を介して接続してお
き、集合基板の状態でファンクショントリミングを行っ
た後、前記集合基板を前記配線部と共に各基板に切り離
すことを特徴とする。
According to the method of manufacturing a hybrid integrated circuit of the present invention, after a circuit pattern of resistors and conductors is formed on an aggregate substrate in which a plurality of substrates are integrally arranged and formed, an electronic component is mounted. In a method of manufacturing a hybrid integrated circuit including a step of performing function trimming of an electric circuit of each substrate in a state of a collective substrate, wiring parts of circuit patterns that need to be connected at the time of function trimming are
Connections are made via wiring parts formed over the surface of another substrate to be separated later, across one substrate, and after function trimming is performed in the state of the collective substrate, the collective substrate is connected to the wiring part. It is also characterized in that it is separated into each substrate.

【0009】[0009]

【作用】本発明にあってはファンクショントリミングを
実行するに際して、接続状態にあることが必要な各基板
における配線部を、一の基板を越えて後に切り離される
べき相隣する他の基板にわたって形成した配線部を介し
て接続しておくことにより、容易に接続状態に設定出
来、ファンクショントリミングを集合基板の状態で行う
ことが可能となり、しかも各個々の基板に分割したとき
は本来の機能上不必要な配線部同士の接続が自動的に遮
断されることとなる。
According to the present invention, when the function trimming is executed, the wiring portion in each substrate which needs to be in the connected state is formed over the other substrates adjacent to each other to be separated later beyond the one substrate. By connecting via the wiring part, it is possible to easily set the connection state, and it is possible to perform function trimming in the state of the collective board. Moreover, when divided into each individual board, it is unnecessary for the original function. The connection between the various wiring parts is automatically cut off.

【0010】[0010]

【実施例】以下本発明を図面に基づき具体的に説明す
る。図1は本発明に係る混成集積回路の製造方法におい
て用いる集合基板の平面図、図2は個々に分割した基板
の拡大図であり、図中1はセラミック等で構成された集
合基板、11〜18は集合基板を構成している個々の基板、
19は同じく捨て基板を示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. FIG. 1 is a plan view of a collective substrate used in the method of manufacturing a hybrid integrated circuit according to the present invention, FIG. 2 is an enlarged view of a substrate divided into individual parts, in which 1 is a collective substrate made of ceramic or the like. 18 is an individual board constituting the collective board,
Reference numeral 19 also indicates a discarded substrate.

【0011】集合基板1には個々の基板11〜18間及びこ
れらと捨て基板19との間を切り分けるための切目7が形
成されている。また各基板11〜18夫々にはその表,裏面
に図4(a) ,図4(b) に示す従来と同様の端子部2及び
配線部4が形成され、更に図には具体的に示していない
が、トランジスタ,コンデンサ等各種の電子部品が搭載
され、これらの電極,端子と配線部4等が半田付けされ
ている。
The collective substrate 1 is formed with cuts 7 for cutting between the individual substrates 11 to 18 and between these and the discarded substrate 19. Further, each of the substrates 11 to 18 is provided with the same terminal portion 2 and wiring portion 4 as shown in FIGS. 4 (a) and 4 (b) on the front and back surfaces thereof. However, various electronic parts such as transistors and capacitors are mounted, and these electrodes and terminals are soldered to the wiring portion 4 and the like.

【0012】そして本発明方法にあっては、特にファン
クショントリミングを実施するに際して接続を必要とす
る各基板11〜18における端子部2のうち、例えばと
とは当該基板11に相隣する他の基板12における配線部
4、並びに端子部2の,と配線部4とを結ぶ配線部
8,9により接続されている。
In the method of the present invention, among the terminal portions 2 on each of the substrates 11 to 18 that require connection especially when performing function trimming, for example, and is another substrate adjacent to the substrate 11. The wiring portion 4 in 12 and the wiring portions 8 and 9 connecting the wiring portion 4 of the terminal portion 2 and the wiring portion 4 are connected.

【0013】配線部8,9は配線部4を形成する工程で
これと同じ方法にて形成される。配線部8,9は一の基
板11に相隣する他の基板12との間に形成される切目7を
越えて形成されており、これによって端子部2の,
、これに連らなる配線部4が相互に接続された状態と
なっている。
The wiring portions 8 and 9 are formed in the same method as in the step of forming the wiring portion 4. The wiring portions 8 and 9 are formed over the cut 7 formed between the one substrate 11 and the other substrate 12 adjacent to each other.
The wiring portions 4 connected to this are connected to each other.

【0014】また集合基板1の周辺部に面して位置し、
利用すべき配線部4を持った相隣する他の基板が存在し
ない基板、例えば基板14,18 の場合には、図1に示す如
く当該基板14に面して位置する捨て基板19を利用して端
子部2のととを結ぶ配線部10を形成する。
Further, it is located facing the peripheral portion of the collective substrate 1,
In the case of a board having no other adjacent board having the wiring section 4 to be used, for example, the boards 14 and 18, the waste board 19 located facing the board 14 is used as shown in FIG. The wiring portion 10 connecting the terminal portion 2 and the terminal portion 2 is formed.

【0015】このように形成された集合基板1につい
て、その各基板11〜18に対する通電テスト,ファンクシ
ョントリミングを行って各定数を適正に設定する。テス
トが終了すると、集合基板1を夫々の切目7に沿って切
り分ける。集合基板1を各個片としての基板11〜18に分
割したときは配線部8,9も切断され、図2に示す如く
になる。
With respect to the collective substrate 1 thus formed, each of the substrates 11 to 18 is subjected to an energization test and function trimming to properly set each constant. When the test is completed, the collective substrate 1 is cut along each of the cuts 7. When the collective substrate 1 is divided into the individual substrates 11 to 18, the wiring portions 8 and 9 are also cut, as shown in FIG.

【0016】図2は基板12の拡大平面図であり、この状
態でリードフレームを取り付け、後の樹脂モールド工程
で全体を合成樹脂にて被覆される結果、配線部8,9の
存在が各基板11〜18それ自体の機能に悪影響を与えるこ
とはない。配線部10についても同様であり、各端子部2
の, から、捨て基板19との間の切目7を越えて捨て
基板19上に延在する配線を介して端子部2の,を接
続しているので、集合基板1を各個片としての基板11〜
18に分割したときは、前述した配線部8,9の場合と同
様に夫々途中の切目7にて切断され、基板11〜18それ自
体の機能に何ら悪影響を与えることもない。このように
して得た基板11〜18にはリードフレームを取り付け、各
端子部2とリード部とを半田付けした後、樹脂工程に送
り合成樹脂にてモールドする。
FIG. 2 is an enlarged plan view of the substrate 12. In this state, the lead frame is attached and the whole is covered with a synthetic resin in a later resin molding step. As a result, the wiring portions 8 and 9 are present on each substrate. 11-18 Does not adversely affect the functioning of itself. The same applies to the wiring portion 10, and each terminal portion 2
Since the terminals 2 of the terminal portion 2 are connected to each other through the wiring extending over the notch 7 from the notch substrate 19 to the notch substrate 19, the substrate 11 as an individual piece of the aggregate substrate 1 is connected. ~
When the wiring board is divided into 18, the wirings 8 and 9 are cut at the cuts 7 in the middle, respectively, as in the case of the wiring portions 8 and 9, and the functions of the substrates 11 to 18 themselves are not adversely affected. A lead frame is attached to the substrates 11 to 18 obtained in this way, and after soldering the respective terminal portions 2 and the lead portions, they are sent to a resin process and molded with a synthetic resin.

【0017】なお上述した実施例においては相隣する基
板11〜18夫々に、利用すべき配線部4が存在する場合に
ついて説明したが、このような配線部4が存在しない場
合には、スペースに余裕があれば相隣する他の基板11〜
18にテスト時にのみ用いる配線部を形成してもよい。ま
たこのような配線部を設けるスペース上の余裕もないと
きは、集合基板1の周辺部のみではなく各基板11〜18間
にも捨て基板19を設け、この捨て基板19の表面を利用し
てファンクショントリミング時に必要な端子部又は配線
部を接続するための配線部を形成することとしてもよ
い。
In the above-described embodiment, the case where the wiring portions 4 to be used are present in the adjacent substrates 11 to 18 has been described. However, when such wiring portions 4 are not present, the space is provided in the space. If there is a margin, another adjacent substrate 11 ~
A wiring portion used only at the time of testing may be formed on 18. In addition, when there is no room in the space for providing such a wiring portion, the discarding substrate 19 is provided not only in the peripheral portion of the collective substrate 1 but also between the substrates 11 to 18, and the surface of the discarding substrate 19 is used. It is also possible to form a wiring portion for connecting a terminal portion or a wiring portion necessary for function trimming.

【0018】[0018]

【発明の効果】以上の如く本発明方法にあっては、ファ
ンクショントリミング時に必要な配線同士の接続を、一
の基板を越えて後に切断されるべき相隣する他の基板表
面に形成した配線部を介して接続することとしたから、
このための配線部は回路パターン形成時に同時的に形成
しておくことが可能となり、スルーホールの形成等の特
別の工程を要さず、しかもファンクショントリミング等
の工程においては集合基板の状態で取り扱うことが出来
て作業能率が格段に向上する等、本発明は優れた効果を
奏するものである。
As described above, according to the method of the present invention, a wiring portion in which wirings required for function trimming are formed on the surface of another adjacent substrate to be cut later after passing over one substrate. I decided to connect via
The wiring portion for this purpose can be formed at the same time when the circuit pattern is formed, and no special process such as formation of a through hole is required, and the process such as function trimming is performed in the state of the collective substrate. Therefore, the present invention has excellent effects such that the working efficiency is remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明方法において用いる集合基板の平面図で
ある。
FIG. 1 is a plan view of a collective substrate used in the method of the present invention.

【図2】図1の集合基板を分割した基板の拡大平面図で
ある。
FIG. 2 is an enlarged plan view of a substrate obtained by dividing the collective substrate of FIG.

【図3】従来方法で用いられる集合基板の平面図であ
る。
FIG. 3 is a plan view of a collective substrate used in a conventional method.

【図4】図3の集合基板を分割した基板の表,裏面の拡
大図である。
FIG. 4 is an enlarged view of front and back surfaces of a substrate obtained by dividing the collective substrate of FIG.

【符号の説明】[Explanation of symbols]

1 集合基板 2,3 端子部 4,5 配線部 7 切目 8,9,10 配線部 11〜18 基板 19 捨て基板 20 印刷抵抗 1 Assembly board 2, 3 Terminal section 4, 5 Wiring section 7 Cut line 8, 9, 10 Wiring section 11-18 Board 19 Discarded board 20 Printing resistance

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数の基板を一体的に配列形成した集合
基板に抵抗及び導体の回路パターンを形成し、電子部品
を搭載した後、集合基板の状態で前記各基板の電気回路
のファンクショントリミングを行う工程を含む混成集積
回路の製造方法において、 ファンクショントリミング時に接続する必要のある回路
パターンの配線部同士を、一の基板を越えて、後に切り
離されるべき相隣する他の基板表面にわたって形成した
配線部を介して接続しておき、集合基板の状態でファン
クショントリミングを行った後、前記集合基板を前記配
線部と共に各基板に切り離すことを特徴とする混成集積
回路の製造方法。
1. A circuit pattern of resistors and conductors is formed on a collective substrate in which a plurality of substrates are integrally arranged and formed, and after electronic components are mounted, function trimming of an electric circuit of each substrate is performed in the state of the collective substrate. In the method for manufacturing a hybrid integrated circuit including the steps to be performed, the wiring parts of the circuit patterns that need to be connected at the time of function trimming are formed over one substrate and over the surface of another adjacent substrate to be separated later. A method of manufacturing a hybrid integrated circuit, wherein the integrated substrate is separated from each other together with the wiring portion after performing the function trimming in the state of the aggregated substrate after the connection is made through the parts.
JP4078989A 1992-02-29 1992-02-29 Manufacture of hybrid integrated circuit Pending JPH05243789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4078989A JPH05243789A (en) 1992-02-29 1992-02-29 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4078989A JPH05243789A (en) 1992-02-29 1992-02-29 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH05243789A true JPH05243789A (en) 1993-09-21

Family

ID=13677309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4078989A Pending JPH05243789A (en) 1992-02-29 1992-02-29 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH05243789A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103427786A (en) * 2012-05-16 2013-12-04 精工爱普生株式会社 Electronic component, manufacturing method and inspection method for electronic component, sheet substrate, and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103427786A (en) * 2012-05-16 2013-12-04 精工爱普生株式会社 Electronic component, manufacturing method and inspection method for electronic component, sheet substrate, and electronic apparatus

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