JPH05243568A - トランジスタ - Google Patents
トランジスタInfo
- Publication number
- JPH05243568A JPH05243568A JP4310285A JP31028592A JPH05243568A JP H05243568 A JPH05243568 A JP H05243568A JP 4310285 A JP4310285 A JP 4310285A JP 31028592 A JP31028592 A JP 31028592A JP H05243568 A JPH05243568 A JP H05243568A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- channel
- semiconductor layer
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US79541891A | 1991-11-19 | 1991-11-19 | |
| US795418 | 1991-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243568A true JPH05243568A (ja) | 1993-09-21 |
Family
ID=25165473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4310285A Pending JPH05243568A (ja) | 1991-11-19 | 1992-11-19 | トランジスタ |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0543268A3 (OSRAM) |
| JP (1) | JPH05243568A (OSRAM) |
| TW (1) | TW223702B (OSRAM) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI335464B (en) | 2005-12-21 | 2011-01-01 | Chimei Innolux Corp | Protruding mechanism and backlight module using the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4354309A (en) * | 1978-12-29 | 1982-10-19 | International Business Machines Corp. | Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon |
| US4479831A (en) * | 1980-09-15 | 1984-10-30 | Burroughs Corporation | Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment |
| JPS6473676A (en) * | 1987-09-16 | 1989-03-17 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1992
- 1992-11-11 EP EP19920119281 patent/EP0543268A3/en not_active Withdrawn
- 1992-11-19 JP JP4310285A patent/JPH05243568A/ja active Pending
-
1993
- 1993-04-14 TW TW082102817A patent/TW223702B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| EP0543268A2 (en) | 1993-05-26 |
| EP0543268A3 (en) | 1993-08-11 |
| TW223702B (OSRAM) | 1994-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100295727B1 (ko) | 전계효과트랜지스터및이를포함하는집적회로와그의제조방법 | |
| EP0495650B1 (en) | Method of fabricating field-effect transistor | |
| US5846857A (en) | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance | |
| US6916698B2 (en) | High performance CMOS device structure with mid-gap metal gate | |
| US20060014354A1 (en) | Method of making transistor with strained source/drain | |
| JPH08222645A (ja) | 軽くドープしたドレイン領域を形成する方法 | |
| JPS63255968A (ja) | 電界効果トランジスタの製造方法 | |
| EP0465045B1 (en) | Method of field effect transistor fabrication for integrated circuits | |
| US5468665A (en) | Process for making a semiconductor MOS transistor employing a temporary spacer | |
| US5460983A (en) | Method for forming isolated intra-polycrystalline silicon structures | |
| US6753229B1 (en) | Multiple-thickness gate oxide formed by oxygen implantation | |
| US20070114605A1 (en) | Ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation | |
| US6391728B1 (en) | Method of forming a highly localized halo profile to prevent punch-through | |
| US6747318B1 (en) | Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides | |
| US5604138A (en) | Process for making a semiconductor MOS transistor | |
| JPH09102550A (ja) | Ldd cmos形成方法 | |
| US6362062B1 (en) | Disposable sidewall spacer process for integrated circuits | |
| US5840611A (en) | Process for making a semiconductor MOS transistor | |
| US8269276B2 (en) | Method for the production of MOS transistors | |
| US5527719A (en) | Process for making a semiconductor MOS transistor using a fluid material | |
| JPH05243568A (ja) | トランジスタ | |
| US6875676B2 (en) | Methods for producing a highly doped electrode for a field effect transistor | |
| JP3262090B2 (ja) | 相補型mos半導体装置および製造方法 | |
| US12268025B1 (en) | ALEFT-ISD-LTSEE{Advanced Low Electrostatic Field Transistor using Implanted S/D and Low Temperature Selective Epitaxial Extension} | |
| US20050208726A1 (en) | Spacer approach for CMOS devices |