JPH05241959A - Cache memory built-in type microprocessor - Google Patents

Abstract

PURPOSE:To execute an address trap function in the case of hitting on built-in cache memory and also mishitting on it. CONSTITUTION:In a microprocessor incorporating cache memory to designate an address of block unit that becomes a purge target from the outside, an address designation means 20 designates a register to hold a specific address or an address inputted from the outside, and a connection means connects the address from the address designation means or the outside to the cache memory, and a comparison means 21 compares a part of the connection means with an associated address to the cache memory, and a gate means 22 connects the address designation means 20 to the cache memory by the connection means when an activation means performing a purge operation is disabled, and outputs a trap signal without performing the purge operation when the registration of the specific address held at the address designation means 20 on the cache memory is detected, and also, coincidence is detected by the comparison means 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor with a built-in cache memory, and more particularly to debugging of a microprocessor having a function of externally designating a block unit address to be purged.

[0002]

2. Description of the Related Art Conventionally, a microprocessor with a built-in cache memory having a function of externally designating an address of a block unit to be purged of this type has a configuration as shown in FIGS. .. Here, only a part of the built-in cache memory and the access control unit is shown and the other parts are omitted.

FIGS. 4A and 4B are block diagrams showing the structures of a part of the built-in cache memory and the access control unit.

Generally, the cache memory (31) is
To close the time gap between the microprocessor (32) operating at high speed and the access to the main memory (34) operating at low speed, a copy of the area of the content of the main memory which is expected to be frequently used have. If the data necessary for the microprocessor to access the main memory exists in the cache memory, the data is accessed faster than in the cache memory without accessing the main memory.

In the figure, at the time of read access, the tag selected by the decoder 4 from the tag memory unit 1 storing the address RAD to be accessed and the address indicating where in the main memory unit 34 the data is stored. , And is compared by the comparator 6. If they match and the valid flag of the valid flag unit 2 indicating whether this entry is valid (valid in this case), the data DO corresponding to the matched tag is output from the data memory unit 3. If there is no matching tag or the valid is invalid (this case is called a miss hit), the address is output from the address generation unit 20 to the address bus AB, the data is accessed from the main memory unit, and the main memory is stored in the internal cache. Register the tag and data of the contents of the section. At the time of write access, only the tag and data are registered in the internal cache.

The function of externally designating the address of the block unit to be purged is to maintain the consistency with the cache contents when the main memory is rewritten by a bus master such as another microprocessor in a multiprocessor environment. The function monitors the system address bus, and if the data registered in the internal cache memory contains data rewritten by another bus master, the entry containing this data is cleared ( Purge) (hereinafter referred to as the bus monitoring function).

In FIG. 4A, a block unit address (hereinafter referred to as a monitoring address) MAD to be purged and a tag selected by the decoder 5 from the tag memory unit 1 are compared by a comparator 7. If these match and the monitoring address strobe MASTB that activates the bus monitoring is active, the valid flag unit 2 corresponding to the matched tag.
Invalidate the barit of.

FIG. 5 shows an example of bus monitoring operation.

In FIG. 5A, the microprocessor 32 writes "A" in the contents of the main memory 34 at address 1000, and at the same time, registers it in the internal cache memory 31. In FIG. 5B, the bus master 35 is the main storage unit 3.
If the contents "A" at address 1000 of 4 is rewritten to "B", the address 1000 being rewritten
Via the bus (hereinafter referred to as a monitoring address bus) MAB to which the monitoring address of the microprocessor 32 is input to the MAD of FIG.
The write signal 5 is connected to the monitoring address strobe MASTB respectively, and the purging operation causes the microprocessor 32 to clear (invalid) the entry corresponding to the address 1000 of the main memory 34 registered in the internal cache memory 3. To The function that causes a trap when a specific address is accessed is called the address trap function.

In FIG. 4B, a specific address (hereinafter referred to as a trap address) T which is a target for causing a trap is shown.
The comparator 21 compares AD with the address output from the address generator 20 to the address bus. This 2
If the two match and the trap strobe TRSTB that activates the address trap function is active,
Activate the trap signal TRAP to notify other units that a particular address has been accessed,
Generate a trap.

In this conventional example, since the address appearing on the address bus is compared with the trap address, when the internal cache memory is hit, the address does not appear on the address bus and the address trap function is executed. Can not. On the other hand, in order to execute the address trap function, the method of not performing the internal cache memory operation, or the internal cache memory operation but the access to the main memory including the trap address is registered in the internal cache memory. There is a way not to do it.

[0012]

As described above, in the conventional microprocessor with a built-in cache memory for externally designating the address of the block unit to be purged, the internal cache
When the memory is hit, there is a problem that the address trap is not executed because the address does not appear on the address bus.

In the method in which the internal cache memory is not operated, all the accesses to the main memory appear on the address bus, so the address trap function can be executed, but the real-time property is lost and the internal cache memory is used. It has the drawback that it cannot operate at high speed.

In the method of operating the internal cache memory but not registering the access to the main memory portion including the trap address in the internal cache memory, the access to the main memory portion including the trap address is missed. Since it becomes a hit, the address trap function can be executed and operates in almost real time, but there is a drawback that it does not become a complete real time operation.

The object of the present invention is to solve these problems,
An object of the present invention is to provide a microprocessor with a built-in cache memory, which can perform an address trap function even when the built-in cache memory is hit when it operates in real time.

[0016]

The structure of the present invention has an external purging operation in a cache memory built-in microprocessor having a built-in cache memory having a function of externally specifying a block unit address to be purged. Purge notification means for notifying activation of the address, address register means for holding a specific address or external input, and address connection means for selectively connecting an address from this address specification means or external to the internal cache memory And a comparing means for comparing a part of the address connecting means with a part of the associative address to the built-in cache memory, and the purge notifying means does not activate the purge operation, the address connecting means determines the address. The address means is connected by connecting the specifying means and the cache memory. Gate means for detecting that a specific address held by the means is registered in the cache memory, and for outputting a trap signal without performing a purging operation when the comparing means detects a match. It is characterized by

[0017]

1 (a) and 1 (b) are block diagrams showing the configuration of a first embodiment of the present invention. In the present embodiment, the monitoring address strobe MAST that activates the bus monitoring is activated by the trap strobe TRSTB that activates the address trap function.
If B is inactive, the monitoring address
Connect the translated trap address from the generator 9 to the bus for comparison with the tag. Since this tag is stored as a logical address, the trap address, which is a physical address, must be translated for comparison with the tag. In the tag memory unit 1, a part of the trap address and a part of the associative address to the internal cache memory are compared by the comparators 6 and 7, and when they match, the cache trap signal CTRAP is activated. To do.

The trap strobe TRSTB is active and the monitoring address strobe MAST
If B is inactive, trap address TAD
Is converted so that it can be compared with the tag in generator 9,
It is connected to the monitoring address bus by a buffer 8 with a control signal. This address and the tag selected by the decoder 5 from the tag memory unit 11 are
The comparator 7 compares.

When these two match, and a part of the address trap input to the decoder 5 and a part of the address trap input to the decoder 4 are compared by the comparator 7 and they match, a cache trap It activates the signal CTRAP, which is input to the OR gate 23, which activates the trap signal TRAP. In the case of a miss hit, the comparator 21 compares the trap address TAD with the address output by the address generator 20 to the address bus. If the two match and the trap strobe TRSTB is active, it activates the trap signal TRAP.

In this embodiment, the monitoring address
If strobe MASTB is active, conventional bus monitoring is performed. Even if the monitoring address strobe MASTB is active and the bus monitoring is executed, if the internal cache memory is miss-hit, the address to be accessed appears on the address bus and the address trap function can be executed. However, the address trap function cannot be executed when the bus monitoring is executed and the internal cache memory is hit. This is avoided by prohibiting rewriting of the main memory of another bus master when the address trap function is executed.

2 and 3 are block diagrams of the second embodiment of the present invention. This embodiment is an improvement of the first embodiment so that the bus monitoring function and the address trap function can be executed at the same time when the internal cache memory is hit.

If the trap strobe TRSTB for activating the address trap function is active and the monitoring address strobe MASTB for activating the bus monitoring is active and the internal cache memory is hit, the address hit The trap address TAD is configured to be compared by the comparator 21 which originally compares the address bus with the trap address.

When the trap strobe TRSTB is active, the monitoring address strobe MAST
The operation when B is inactive is the same as in the first embodiment. If the trap strobe TRSTB is active, the monitoring address strobe MASTB is active, and the internal cache memory is hit, the cache trap busy signal CTR
Activate BSY and HAD the hit address
Output to. This address and the trap address TA converted so that it can be compared with the tag in the generator 25
The comparator 21 compares D with D. When these two match, the trap signal TRAP is activated.

Since the operation of the built-in cache memory is faster than that of the main memory unit, the address generation unit 20 is active while the cache trap busy signal CTRBSY is active.
Is much shorter than the time it is outputting the address to the address bus. Therefore, the address trap function with the address appearing on the address bus is not impaired. This allows the bus monitoring function and the address trap function to be executed at the same time when the internal cache memory is hit.

[0025]

As described above, according to the present invention, the address trap function can be executed both when the internal cache memory is hit and when it is missed, and the real-time property is maintained even when the cache operation is effective. There is an effect that a certain debugging can be performed and a conventional circuit can be used at a low cost without impairing the bus monitoring function.

[Brief description of drawings]

1A and 1B are block diagrams of a cache memory unit and an access control unit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a cache memory unit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an access control unit corresponding to FIG.

4A and 4B are block diagrams of a cache memory unit and an access control unit of a conventional example.

FIGS. 5A and 5B are schematic block diagrams for explaining registering in a cache memory and a bus monitoring operation in conventional bus monitoring.

[Explanation of symbols]

1 Tag memory unit 2 Valid / Flag unit 3 Data memory unit 4,5 Decoder 6,7,21 Comparator 8,25 Generator 9 Comparator for comparing inputs to the decoder 10,22 Two-input AND gate 11,12,13 One Input is negative input 2 input A
ND gate 14,153 3-input AND gate 16-19,24,27-29 Buffer with control signal 20 Address generator 23 2-input OR gate 26 Inverter 31 Internal cache memory 32 Microprocessor with cache memory 33 Micro Processor board 34 Main memory 35 Bus master 1 36 Bus master board 37 System bus

Claims (1)

[Claims] 1. A purge notification means for externally notifying activation of a purge operation in a cache memory built-in microprocessor having a built-in cache memory having a function of externally specifying an address of a block unit to be purged. A register for holding a specific address or an addressing means for inputting from the outside, an address connecting means for selectively connecting an address from the addressing means or the outside to the internal cache memory, and a part of the address connecting means The comparing means for comparing a part of the associative addresses to the internal cache memory and the address connecting means connect the address specifying means and the cache memory when the purge notifying means does not activate the purge operation. The specific address held by the addressing means Is registered in the cache memory, and gate means for outputting a trap signal without performing a purging operation when the comparison means detects a match.
Microprocessor with built-in memory.