JPH113246A - Microcomputer containing cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a system containing a microcomputer while keeping consistency between a cache and an external memory by preparing a monitoring means to monitor the accesses to an external shared memory of the microcomputer. SOLUTION: A monitor circuit 119 detects that an external bus master accesses an external shared memory and then permits the external writing to a data cache memory. In such cases, a write control circuit 117 can continuously store the data into the data cache. The circuit 117 also can output the execution address of the program stored in an instruction cache to the outside through a terminal MA3-MA2 based on the monitoring result, can invalidate the data stored in the cache via a comparator 106, a 3-input AND 107 and a timing generation circuit 112 and then can rewrite the data of the cache. As a result, the coincidence of contents is effectively secured between the cache and the external shared memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in cache memory, and more particularly, to a means for invalidating a part of the contents of a data cache memory, a means for writing to the built-in cache memory from outside the microcomputer, and a program. Related to the means for leaving the execution result.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a microcomputer with a built-in cache memory (hereinafter referred to as "cache") disclosed in Japanese Patent Application Laid-Open No. 5-250257.
In a microcomputer with a built-in cache, it is required that the value of the memory connected to the outside (hereinafter, referred to as “external memory”) and the value of the built-in cache match (hereinafter, “coherence”). This cache is composed of several blocks. The microcomputer, once fetching data from the external memory, uses the data in the cache when the data in the cache is valid (hereinafter, “cache hit”). Since the cache can be accessed at a high speed, the performance of the microcomputer is improved.
When there is no data in the cache (hereinafter, "miss hit"), one block of data is fetched from the external memory. 1
Since it takes time to capture blocks, there are microcomputers that continuously access and capture data.

A description will be given of a method of realizing the consistency employed in the microcomputer shown in FIG. 2 when the microcomputer writes to the cache
Two methods are used. One is a method of writing data to an external memory whenever a microcomputer performs a write operation, which is called a write-through method. The other is a method in which only the data in the cache is rewritten and written into an external memory when necessary.

Next, the problem of consistency in the read operation will be described. When there is only one bus master, the cache and the external memory are kept consistent by the above-mentioned writing method. However, if there is another microcomputer or DMA controller as the bus master, the data in the external memory will be rewritten by the other microcomputer or DMA controller, and the consistency between the cache and the external memory will not be maintained. Become.

There is another important problem with microcomputers having a cache. That is, when executing a program taken into the cache, information for tracing the execution result of the program does not come out of the microcomputer.

In the case of FIG. 4, the problem of coherence between the cache and the external memory and the problem of tracing the execution result of the program are solved by the following method. In other words, invalidate the cache for consistency (hereafter,
"Purge") method. When purged, data is always taken from the external memory, and consistency is maintained. That is, when data is fetched from the external memory, data of the cache block size is always fetched. The terminals MA31-MA2 in FIG.
Normally, the address at the time of access by the microcomputer is output, but when purging, it is input and the address to be purged is input. While the cache purge timing signal MASTB is active,
One block will be purged.

The operation of the execution trace will be described. The trace information selection signal MEAN in FIG.
1-A signal indicating that a valid address is output to MA2. Terminal M when the cache hits
Since the address is output to A31-MA2, the trace information selection signal MEAN becomes active. In the case of a mishit, it remains inactive.

As another conventional example, the operation of a microcomputer MC68040 manufactured by Motorola will be described. FIG.
Is a MC68040 block diagram of FIG. MC68040
Has an external bus monitoring function in the data cache, the instruction cache, and the data memory unit, and is configured to be able to rewrite the cache data from outside the microcomputer.

[0009] The snoop controller of MC68040 can recognize that there is an external write to the cache by the state of the bus control signal and the address output from the external bus master. When the external bus master tries to rewrite the data fetched into the cache with the data in the external memory when writing to the cache from the outside, the MC68040 prohibits the external bus master from accessing the external memory and releases the cache to the outside. Then, it operates to update the data in the cache.
Then, when it is necessary to write back to the external memory, the data in the cache is written back. This keeps the external memory and cache consistent. However, the MC68040 does not have a function of leaving the execution result of the program when the program in the cache is executed in the history.

[0010]

The problem of the prior art described above is that high performance cannot be obtained in an application system incorporating a microcomputer. That is, the external bus master is a microcomputer,
This is because, when synchronizing the two microcomputers with the 1-byte flag of the external memory, it is necessary to purge only by rewriting the 1-byte data, and when reading the flag, the data for one block is fetched. This is because the free time of the external bus decreases.

On the other hand, in a system having a DMA controller as an external bus master, when data fetched into a cache is rewritten in a burst mode,
At the time of transfer, the data access bus inside the microcomputer is released to the external bus master and cannot be used. When the microcomputer accesses the cache, execution of the program is waited until the DMA transfer is completed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microcomputer with a built-in cache memory having at least two caches for data and instructions, and to improve the performance of a system incorporating the microcomputer while maintaining consistency between the cache and the external memory. And to enable the execution result of the program taken into the cache to be recorded in the history.

[0013]

The object of the present invention is to provide a monitoring means for monitoring access to a shared memory external to a microcomputer, and a program executed upon execution of a program stored in an instruction cache based on an output state of the monitoring means. Output means for externally outputting the address of the data, an invalidating means for invalidating any data in the data cache based on an output state of the monitoring means, and an output state of the monitoring means.
Achieved by a microcomputer with a built-in cache, comprising: storage means for continuously storing data in a data cache; and means for writing arbitrary data to the data cache from outside the microcomputer based on the output state of the invalidation means can do.

In the microcomputer according to the present invention, when the external bus master accesses the external shared memory, the monitoring means detects the access to the external shared memory, and permits external writing to the data cache memory. In that case, data can be continuously stored in the data cache. Further, based on the monitoring result, the execution address of the program stored in the instruction cache can be output to the outside, the data in the cache can be invalidated, and the data in the cache can be rewritten. As a result, the contents of the cache and the external shared memory can be efficiently matched and the execution result of the program can be left in the external address memory, so that the performance of the system incorporating the microcomputer of the present invention can be improved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a preferred embodiment of the present invention,
The following (a) and (b) can be mentioned. (B) A selection means for selecting one of the invalidation means and the writing means.

(B) timing adjustment means for adjusting the timing of the invalidation processing by the invalidation means, the timing of the write processing by the writing means, and the timing of the program execution processing stored in the instruction cache memory; Timing output means for outputting the result of the timing adjustment by the means to the outside.

The embodiment (a) relates to selecting invalid means and writing means according to the situation. That is, when the external bus master is a microcomputer and synchronization is achieved with a 1-byte flag stored in the external memory, a method of rewriting cache data by selecting a writing means is selected. When a bus master other than the microcomputer is a DMA controller and data is continuously transferred in the burst mode, a method of purging a part of cache data from outside the microcomputer is selected. Thereby, rewriting and purging of cache data can be selected. In addition, since the purging can be used effectively, the performance of the system incorporating the microcomputer of the present invention can be improved.

The embodiment (b) relates to adjusting the timing of each processing. That is, when the cache is purged or accessed from the external bus master, the timing adjustment unit adjusts the timing for writing the address to the address memory, and outputs a control signal from the timing output unit to the outside. Also, at the time of normal program execution, the execution address is output to the outside. This allows
The execution result of the program can be reliably left in the address memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention and an application using the same will be described with reference to the accompanying drawings. FIG. 1 is a block diagram for explaining the embodiment, FIG. 2 is a timing chart of each part of the microcomputer shown in FIG. 1, and FIG.
FIG. 21 is a block diagram showing an application example of the microcomputer shown in FIG.

In FIG. 1, the monitoring means according to the present invention is a 4 NAND circuit as a circuit for monitoring external shared memory access.
(119). The execution address of the program whose timing has been adjusted by the timing generation circuit (105) is the terminal M
Output through A31-MA2. The invalidating means for invalidating any data in the data cache memory includes a comparator (106) and a three-input AND (10
7), comprising a timing generation circuit (112). C
LR is a signal indicating invalidity.

The storage means for continuously storing data in the data cache memory and the writing means for writing arbitrary data from the outside of the microcomputer to the data cache memory include a write control circuit (117).
1, a signal CEAN for inputting a timing at which the external bus master writes data into the cache, and an MWR * (* indicates an inverted signal as an external memory write strobe.
2, and an HLDAK signal indicating that the external master occupies the bus. The monitoring means (119) also has a function of selecting one of the invalidating means and the writing means by using each signal of CAEN, MWR *, and HLDAK.

The timing adjustment means for adjusting the timing of the invalidation processing by the invalidation means is the timing generation circuit (112). The timing adjusting means for adjusting the timing of writing arbitrary data from the outside of the microcomputer to the data cache memory by the writing means is CEAN. Execution processing of a program stored in the instruction cache memory and a timing generation circuit (1
The timing adjusting means for adjusting the timing of 12) and CEAN is a timing generation circuit (116). The timing adjustment result generated by the timing generation circuit (116) is output via timing output means MAACK. MAACK is a signal for outputting a purge address input timing signal to the terminals MA31-MA2.

A circuit for generating a cache hit or a mishit includes a comparator (108) and a two-input AND (10
9), NOT circuit (110), 2-input AND (113)
And the mishit signal is output via the terminal MISS. The cache hit signal is represented by an internal signal HIT.

The cache memory is an MD which is a decoder.
It comprises an EC (101), an RDEC (102), a tag memory unit (103), a data memory unit (104), the invalidating means, the hit / miss hit signal generation circuit, and the write control circuit (117).

The terminals MA31-MA2 output a program execution address, and are also used for inputting a purge address when invalidating arbitrary data and for inputting a write address when writing data to a cache. Terminal R
A31-RA2 is an address bus terminal for external memory access. DB is a data bus terminal for external memory access. DO is a terminal for outputting hit data to leave a history of program execution results. DO is output via a 3-stator buffer (114). NWR * is an external memory write strobe,
MRD * is an external memory read strobe. MEA
N is a write information selection signal for tracing a program execution result. When a cache hit occurs, the output information of MA31-MA2 is output. When a mishit occurs, the information of RA31-RA2DB is output. Is a selection signal for writing to the.

The operation of this embodiment will be described with reference to the timing chart of FIG. First, the case where the external bus master writes data to the cache will be described. The hold acknowledges HLDAK and CAEN are at a high potential (hereinafter referred to as “H”).
i "), MWR * is low potential (hereinafter" Lo "), MAS
TB is in the Lo state. Write control circuit (117)
Activates and activates the write strobe to the cache. Since MASTB is Lo, the cache is not purged. As the MEAN signal, the HIT signal is input to the timing generation circuit (111), and is output after the timing is adjusted. Here, the HIT signal is a signal delayed by one clock. DO has a high impedance because the external bus master uses an external data bus when HLDAK is active.

Next, the DR which seems to use HLDAK
Consider AM refresh. MASTB is Lo,
CAEN is Lo, MWR * is Hi, and HLDAK is Hi. Since MWR * is Hi, writing to the cache is not performed. Also, since MASTB is Lo, the cache is not purged.

Next, a description will be given of a case where the microcomputer reads the cache. MASTB is Lo, CA
EN is Lo, HLDAK is Lo, MWR * is Hi, MR
D * is Hi. Since MASTB is Lo, the cache is not purged. CAEN is L
Since it is o, writing to the cache is not performed. H
Since the IT signal is Hi and HLDAK is Lo, hit data is output via DO.

Next, a description will be given of a case where the external bus master reads the same data as the data fetched into the cache from the external memory. MASTB is Lo, CAEN is H
i, HLDAK is Hi, MRD * is Lo, MWR * is H
This is the state of i. Since MASTB is Lo, the cache is not purged. Since MWR * is Hi, writing to the cache is not performed. Since the HIT signal is Hi and the HLDAK signal is Lo, hit data is output via DO.

Next, a description will be given of the case of purging the cache. Here, MASTB is Hi, CAEN is Lo, H
LDAK is Hi, MRD * is Lo, and MWR * is Hi. Since MASTB is Hi, the output signal CLR of the comparator (106) and the three-input AND (107) is output.
Becomes active and clears the information in the tag memory section.
Since CAEN is Lo, it is not written to the cache.

Next, a description will be given of a case where the microcomputer writes data to the cache. MASTB is Lo, CAEN is Lo, HLDAK is Lo, and MWR * is Lo. The quash is not purged because MASTB is Lo. CAEN is Lo, but the cache write strobe C inside the microcomputer is
Since MWR * becomes active, writing to the cache is performed. At the same time, since MWR * is Lo, the data output from DO is written to the external memory. In the case of a mishit, one block is read from the external memory.

Next, the address output of the program execution result will be described. In the timing diagram of FIG.
At the address and the address 0300H, a valid program execution address is output while MAACK is Hi. The timing generation circuit (105) holds the output address until the output timing. MA31-M
It is the timing generation circuit (116) that determines the input and output timings of A2. Here HLDAK, M
The address output timing is made using the ASTB and CAEN signals. This timing signal is output to the outside as a MAACK signal.

An application example of the microcomputer according to the present embodiment will be described with reference to FIG. In FIG.
The address memory (301) stores a history of addresses executed by the microcomputer (303). The multiplexer (305) is a circuit for selecting information to be written in the address memory. The program switching signal is based on the MEAN signal output from the microcomputer (303), and the write control circuit (30)
Generated in 4). The address written in the address memory is A31-A2 when the microcomputer (303) accesses the external memory, and MA31-MA2 when the microcomputer (303) accesses the cache. When the cache is externally accessed, the three-state buffer (30
By switching 2), an address can be input to MA31-MA2. By writing MA31-MA2 into the address memory, it is possible to leave it in the history.

[0034]

According to the present invention, the method of maintaining the consistency between the cache of the microcomputer and the data in the external memory can be switched at any time, and the frequency of use of the bus and the release time of the cache can be optimized as a system. Thus, the performance of an application system incorporating the microcomputer according to the present invention is improved.

Further, when the program loaded into the cache is executed, a function of outputting the program execution result to the outside is provided, so that the history of the execution result can be left in the development support apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a timing chart of each unit in the embodiment.

FIG. 3 is a block diagram illustrating an application example of the present invention.

FIG. 4 is a block diagram of a conventional example (published in JP-A-5-250257).

FIG. 5 is a block diagram of MC68040.

[Explanation of symbols]

101: MDEC address decoder 102: RDEC address decoder 103: tag memory unit 104: data memory unit 105: address output timing generation circuit 106: comparator for purging 107: 3-input AND 108: comparator for hit and mishit 109: 2-input AND 110 NOT circuit 111 MEAN signal timing generation circuit 112 MASTB signal timing generation circuit 113 2-input AND 114 Data output 3-state buffer 115 Address output 3-state buffer 116 Address output buffer control timing generation circuit 117 Write control circuit 118 ... 2-input AND 301 ... Execution address storage memory 302 ... 3-state buffer 302 ... CPU (microcomputer) 304 ... Address Memory write control circuit 305 MPX (multiplexer) 401 2-input AND 402 Address output delay circuit 501 Floating point unit 502 Integer unit 503 Instruction memory unit 504 Data memory unit 505 Data cache snoop controller 506 Data ATC 507 ... Data cache 508 ... Instruction cache 509 ... Instruction ATC 510 ... Instruction cache snoop controller MA31-MA2 ... Purge address, cache write address input and output of program execution address RA31-RA2 ... Address when accessing external memory DB ... Address DO: Cache hit data MWR *: External memory write strobe MRD *: External memory read strobe ISS ... miss-hit signal CAEN ... cache write timing signal MASTB ... cache purge timing signal MEAN ... trace information selection signal MAACK ... input timing signal CMWR * ... micro-computer inside of the cache write strobe HLDAK ... hold acknowledge signal of the purge address

Claims (3)

[Claims] 1. A microcomputer having at least two cache memories for data and instructions, the monitoring means monitoring access to a shared memory external to the microcomputer having the cache memory, and the monitoring means. Output means for externally outputting the address of the executed program when the microcomputer executes the program stored in the instruction cache memory based on the output state of the means; and the data cache memory based on the output state of the monitoring means. Invalidation means for invalidating any data of: a storage means for continuously storing data in the data cache memory based on an output state of the monitoring means; and arbitrary data based on an output state of the invalidation means. From outside the microcomputer Cache memory-based microcomputer and having a writing means for writing the serial data cache memory. 2. The apparatus according to claim 1, further comprising a selection unit for selecting one of the invalidation unit and the writing unit.
A microcomputer with a built-in cache memory according to claim 1. 3. The timing of invalid processing by said invalid means, the timing of write processing by said writing means,
And timing adjustment means for adjusting the timing of the program execution processing stored in the instruction cache memory, and timing output means for outputting the result of the timing adjustment by the timing adjustment means to the outside. 2. The microcomputer with a built-in cache memory according to 1.