JPH0523682U - Video signal processing circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain a video signal processing circuit which increases the level of a luminance signal and reduces noise in order to improve the sensitivity of a video camera used in a low illuminance or a dark place. [Structure] Control signal generating means for generating a switch control signal based on the level of an input luminance signal, and first to fourth switching operations in response to the switch control signal output from the control signal generating means. It is formed by including a signal selecting means including a switch unit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit that increases the level of a luminance signal and reduces noise in order to improve the sensitivity of a video camera used in a low illuminance or a dark place. Is.

[0002]

[Prior Art]

 The sensitivity of a video camera generally depends on the brightness of the object used in the process of picking up a video signal of a predetermined level from the object and the opening degree of the lens iris. A standard test pattern called "gray scale", in which the brightness from white to black is divided into 11 levels and arranged, is used for the measurement.

[0003]

[Problems to be solved by the device]

 However, when the video camera is used in a relatively dark place, the video camera becomes less sensitive, which adversely affects the final screen quality. Therefore, in this technical field, by adopting an automatic gain control circuit and increasing the amplification degree up to a certain low illuminance amount of light incident on the video camera, a luminance signal of a constant level is obtained. The technique for obtaining the information is widely known. However, since the above automatic gain control circuit has an inherent lower limit in its amplification factor that does not cause noise, it is not desirable when incident light with a certain light amount or less corresponding to this lower limit is incident on the video camera. Since noise appears in the video signal output from the video camera, it is practically difficult to obtain a good video signal from the incident light under low illuminance only with the automatic gain control circuit.

On the other hand, in order to improve the sharpness of an image in a video camera, a contour compensating device which will be described later in detail with reference to FIG. 3 is widely used. This contour compensator is basically composed of two delay lines and three adders, and is included in the normal operating range (for example, medium illuminance / high illuminance) of the automatic gain control circuit. The contour of a video input signal having a brightness level is emphasized or corrected. However, since such a conventional contour compensator still has a low S / N ratio with respect to incident light input under low illuminance, the sensitivity for incident light with low illuminance was naturally poor. ..

This will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing a contour correction circuit according to a conventional technique, and FIG. 4 is a waveform diagram for explaining the operation of each part of FIG. When the luminance signal input a passes sequentially through the first and second delay lines DL1 and DL2 having a delay time of one horizontal period (1H), the first delay line DL1 and the second delay line DL2 output their respective outputs. The signals shown in b and c of FIG. 4 are output to the terminals. Adder A1 adds the original luminance signal a and the luminance signal c delayed by 2H to provide a summed output of (a + c). Subsequently, the inverting amplification unit DO first reduces the amplitude of the output of the adder A1 to ½ to obtain a signal as shown in d of FIG. The signal of is output. The adder A2 adds the 1 H delayed signal b and the output "-d" of the inverting amplifier DO to output a contour correction signal as shown in e of FIG. The contour correction signal e is applied to one input terminal of the adder A3 after passing through the low-pass filter LP F. The adder A3 finally outputs the contour-corrected luminance signal as shown in f of FIG. 4 by adding the 1 H delay signal b and the contour correction signal e.

As described above, the contour correction circuit of FIG. 3 can perform a good contour correction function for a luminance signal under medium illuminance and high illuminance, but does not perform a contour correction function for a luminance signal under low illuminance. On the other hand, it also has a problem of showing a low S / N ratio.

Therefore, an object of the present invention is to use a delay line to perform a contour compensation operation for a video signal based on incident light of medium illuminance and high illuminance, while performing a contour compensation operation on an incident light of low illuminance. An object of the present invention is to provide a video signal processing circuit capable of selectively performing an operation of improving the S / N ratio and increasing the sensitivity of a video camera for a video signal based on the video signal.

Another object of the present invention is to provide a video signal processing circuit in which switching between contour compensation operation and sensitivity enhancement operation is automated.

[0009]

[Means for Solving the Problems]

 The video signal processing circuit according to the present invention for achieving the above object comprises a control signal generating means for generating a switch control signal based on a level of an input luminance signal, and the control signal. Signal selecting means formed by the first, second, third and fourth switch units that perform a switching operation in response to a switch control signal output from the generating means, an input luminance signal and the fourth switch. First computing means for adding unit output signals to generate first and second summed output signals, an input luminance signal applied to its first input terminal and said second input terminal applied thereto The first switch unit which selects one of the first addition outputs of the first calculation means by the control signal from the control signal generation means and supplies it to the output terminal, and the first switch unit. Delay unit for delaying the output signal of the first delay unit by 1H to output one delay signal, and a second delay unit for further delaying the output signal of the first delay unit for 1H to output the first and second delay signals. Means and one of the first and second delayed output signals of the second delay means applied to the first and second input terminals thereof, respectively, is selected by the control signal of the control signal generating means, and its output terminal is selected. To the fourth switch unit, a second addition output signal of the first delay means applied to its first input terminal, and a second delay output of the second delay means applied to its second input terminal. One of the signals is selected by the control signal of the control signal generating means and is supplied to its output terminal, and the second switch unit and the output signal of the second switch unit from the delayed output signal of the first delay means. To Second computing means for generating a subtraction output signal that is applied to one input terminal of the third switch unit and the second computing means applied to the one input terminal of the other two types The subtraction output signal is selectively supplied to the first or second output terminal by the control signal of the control signal generating means, and the first delay unit is based on the control signal of the control signal generating means. Operation of adding one delayed output signal of the stage and the output signal from the first output terminal of the third switch unit, or one delayed output signal of the first delay means, the third switch unit and the second output And a third operation means for selectively performing a subtraction operation with the output signal from the terminal.

In the video signal processing circuit according to claim 2, the control signal generating means includes a first clamp circuit for clamping the input luminance signal to a predetermined dc level, and the first clamp circuit. A first buffer for buffering the output of the non-inverting amplifier, a non-inverting amplifier for amplifying the output of the first buffer without changing the polarity, and a predetermined mode switching reference voltage of the non-inverting amplifier. It is characterized by comprising a comparator.

The video signal processing circuit according to a third aspect is characterized by being formed by a manual switch that can be manually operated.

A video signal processing circuit according to a fourth aspect of the present invention includes a second clamp circuit for clamping an output signal of the first switch unit in the signal selecting means to a predetermined dc level, and a second clamp circuit. A second buffer for buffering the output of the two-clamp circuit, a first delay line for delaying the output of the second buffer by 1H, and a first buffer for further buffering the output of the first delay line. It is characterized by consisting of 3 buffers.

A video signal processing circuit according to a fifth aspect of the present invention includes a third clamp circuit for clamping the output signal of the first delay means to a predetermined dc level, and an output of the third clamp circuit. Buffer for buffering the output of the fourth buffer, a second delay line for further delaying the output of the fourth buffer by 1H, and an output of the second delay line for further buffering the second delay means. A fifth buffer for supplying a 1-delay output signal and a voltage divider for dividing the first delay output from the fifth buffer into a voltage and supplying a second delay output signal of the second delay means. Characterize.

A video signal processing circuit according to a sixth aspect of the present invention is an addition circuit for adding the input luminance signal clamped to a predetermined dc level and the output signal of the fourth switch unit, and the addition circuit. Buffer for buffering the output of the first calculation means to supply the first addition output signal of the first calculation means, and the first addition output signal from the sixth buffer, And a voltage divider for supplying a 2-added output signal.

The video signal processing circuit according to claim 7 is formed by a subtraction circuit for subtracting one delayed output signal from the first delay means and an output signal from the output terminal of the second switch unit. Then, a contour correction signal is output when the luminance is equal to or higher than a predetermined reference illuminance, and a noise component corresponding to a difference between vertically adjacent luminance signals is detected and output when the luminance is equal to or lower than the predetermined reference illuminance. It is characterized by being formed like this.

The video signal processing circuit according to claim 8 is an addition operation of one delayed output signal of the first delay means and a contour correction signal from the first output terminal of the third switch unit, or An adder / subtractor circuit for performing a subtraction operation of one delayed output signal of the first delay means and a detection noise component from the second output terminal of the third switch unit, and an output of the adder / subtractor circuit It is formed by the 7th buffer for buffering, and the contour-corrected luminance signal is removed at a predetermined reference illuminance or higher, and the level is increased and noise is removed at a predetermined reference illuminance or lower. It is characterized in that it is formed so as to output the generated luminance signal.

[0017]

[Action]

 The video signal processing circuit of the present invention is as described in claims 1 to 8, and, if necessary, a control signal generating means for generating a switch control signal based on the level of an input luminance signal, and the control signal generating means. There is provided a signal selection means including first to fourth switch units that perform a switching operation in response to a switch control signal output from the control signal generating means.

The first to fourth switch units may be formed by analog switches, for example. The switch unit selectively forms two kinds of signal paths by the switch control signal from the control signal generating means, one of which is a signal path under medium illuminance or high illuminance, and the other one. The second is the signal path under low illumination.

If a brightness input signal is input under medium and high illuminance, the control signal generating means generates a switch control signal of, for example, a “low” logic level according to the level of the brightness signal, All switch units in the signal selection means are thereby switched to form a signal path for contour compensation of the luminance signal. That is, the first switch unit selects an input luminance signal and sequentially supplies it to the first delay means and the second delay means connected in series. Each of these delay means delays the signal applied to its input terminal by one horizontal period. The second delay means simultaneously generates the first and second delayed output signals, the second delayed output signal having a level equal to or less than the level of the first delayed output signal. At this time, the fourth switch unit selects the first delayed output signal of the second delay means and supplies it to the first calculation means. The first computing means adds the input luminance signal (hereinafter referred to as OH) and the first delayed output signal of the second delay means (that is, the luminance signal delayed by 2H: hereinafter referred to as 2H). Then, the first and second addition output signals are generated, but the level of the second addition output signal is set smaller than the level of the second addition output signal. Here, the second switch unit selects the second addition output signal of the first operation output means, for example {(OH + 2H) / 2}, and supplies it to one input terminal of the second operation means. The second calculation means outputs the second addition output signal of the first calculation means from the delayed output signal of the first delay means (that is, the luminance signal delayed by 1H: hereinafter referred to as 1H) applied to the other input terminal. Subtraction is performed to generate a contour correction signal, that is, 1H-{(OH + 2H) / 2}. This contour correction signal is applied to the second input terminal of the third calculating means via the third switch unit, while the delayed output signal 1H of the first delay means is applied to the first input terminal of the third calculating means. When applied, the third computing means combines the first and second input signals and outputs a contour-corrected luminance signal.

On the other hand, when a luminance input signal is input under low illuminance, the control signal generating means generates a switch control signal of, for example, a “high” logic level based on the level of the luminance signal, By this, all switch units in the signal selecting means are switched so as to select a signal path for improving the sensitivity of the low luminance signal. The improvement of the sensitivity of the low luminance signal in the present invention is generally formed by the process of multiplying the luminance signal level, the noise detection process and the process of removing noise from the increased luminance signal. First, the first switch unit operates so as to select the first addition output signal of the first calculating means, but the inputted luminance signal OH is applied to the first input terminal of the first calculating means, Since the second delayed output signal of the second delay means, for example 2H / 2, is applied to the second input terminal by the selection of the fourth switch unit, the first arithmetic means has at least OH + 2H / at its first addition output terminal. It becomes possible to provide an increased luminance signal corresponding to 2 (denoting this as OH '). The increased luminance signal is sequentially supplied from the first addition output terminal of the first calculation means to the first and second delay means via the first switch unit, and the first and second delay means are supplied to the first and second delay means. Each also produces an increased delayed output signal. At this time, assuming that the first delayed output signal and the first and second delayed output signals of the second computing means are 1H ', 2H' and 2H '/ 2, respectively, the second computing means moves in the vertical direction. Depending on the similarity between the delayed signals of adjacent 1H 'and 2H', the same subtraction operation as [1H'-2H '] is performed to detect noise. That is, the second switch unit selects the first delay signal 2H 'of the second delay means and supplies it to one input terminal of the second operation means, whereby the second operation means applies it to the other input terminals. The 2H 'delayed signal is subtracted from the delayed output signal 1H' of the first delay means to detect noise. At this time, the third switch unit switches the detection noise component output from the second computing means to the third input terminal side of the third computing means, whereby the third computing means has its first input terminal. By subtracting the above-mentioned detected noise component from the delayed output signal 1H 'from the first delay means applied to, the luminance signal whose level is increased and noise is removed is output. Therefore, according to the video signal processing circuit of the present invention, not only the S / N ratio for the low illuminance signal can be improved, but also the contour compensation function can be performed in parallel for the medium or high illuminance signal. Therefore, the used value of the circuit configuration can be raised. In addition, since the selection of the S / N ratio improving function and the contour compensating function is automatically performed according to the level of the input luminance signal, there is an advantage that convenience in use is provided.

[0021]

【Example】

 The above-mentioned advantages and features of the present invention and its advantages will be clearly understood from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of a video signal processing circuit according to the present invention, and FIG. 2 is a schematic circuit diagram of the video signal processing circuit shown in FIG.

In FIG. 1, reference numeral 10 indicates a control signal generating means for generating a switch control signal Sc based on the level of an input luminance signal Yi. According to an embodiment of the present invention, the control signal generating means 10 buffers an output of the first clamp circuit and a first clamp circuit for clamping the input luminance signal to a predetermined dc level. A first buffer for ringing, a non-inverting amplifier for amplifying the output of the first buffer without changing the polarity, and a comparator for comparing the output of the non-inverting amplifier with a predetermined mode switching reference voltage. Is formed by.

The first clamp circuit is formed of a clamping capacitor C3, a switching transistor Q1 and clamping voltage generators Vcc, R9, C4, R10 and R11 in FIG. That is, the input luminance signal Yi is applied to the collector of the switching transistor Q1 via the clamping capacitor C3, and the clamping pulse Cp is applied to the base of the transistor Q1. The clamping pulse Cp is generated in a blank period from a clamping pulse generating circuit (not shown) in response to the horizontal synchronizing pulse in the video signal to turn on or off the transistor Q1. Further, the resistor R9 and the capacitor C4 are connected in parallel to the emitter of the transistor Q1, and the connection point between the resistors R10 and R11 supplied with the voltage from the power supply Vcc is also connected to the emitter of the transistor Q1. To supply the emitter clamping voltage of the transistor Q1. In the first clamp circuit configured as described above, while the clamping pulse Cp is applied to the base of the transistor Q1, the clamping voltage is applied to the output side of the capacitor C3 through the turned-on transistor Q1. While being supplied, the capacitor C3 is charged, while the capacitor C3 is charged while the clamping pulse Cp is not applied to the base of Q1 by the transistor, that is, while the transistor Q1 is turned off. The generated DC voltage is held at a constant level while being discharged by the time constant determined by the capacitor C3 and the emitter resistance R12 of the first buffer which will be described later. In this way, the horizontal sync tip level in the input luminance signal Yi is fixed to the output level of the clamp voltage generating section, so that a DC reproduced luminance signal is obtained at the collector terminal of the transistor Q1.

The first buffer is formed by a transistor Q4 forming an emitter follower and an emitter resistor R12. The base of the transistor Q4 is connected to the collector of the transistor Q1 so that the output of the first buffer is drawn from the emitter of the transistor Q4. The first buffer has a high input impedance and converts the signal applied to its input terminal into a low impedance without changing the clamp level and outputs it.

The non-inverting amplifier connected to the output terminal of the first buffer amplifies and outputs the output of the first buffer without a change in polarity, and includes an OP amplifier OP1, resistors R1 and R2, It is formed by the capacitor C1.

The output of the non-inverting amplifier is applied to one end of a comparator via a low pass filter formed by a resistor R4 and a capacitor C2.

The comparator is formed by an OP amplifier OP2, reference voltage setting resistors R5 and R6, a feedback resistor R7 and an output resistor R8. The reference voltage applied to the non-inverting terminal of the OP amplifier OP2 is a reference voltage for switching the operation mode of the video signal processing circuit according to the present invention, which is an arbitrary boundary value between low illuminance and medium illuminance. (This is referred to as a predetermined reference illuminance).

Therefore, when the level of the input luminance signal applied to the inverting terminal of the OP amplifier OP2 is higher than the reference voltage, that is, when the luminance signal under medium illuminance or high illuminance is applied to the input terminal Yi, While the comparator generates the low level switch control signal Sc, when the input luminance signal level to the inverting terminal of the OP amplifier OP2 is lower than the previous reference voltage, that is, the luminance signal under low illuminance is input luminance terminal Y i. When applied to the comparator, the comparator generates a high level switch control signal Sc.

The control signal generating means according to another embodiment of the present invention is formed of a manually operable manual switch, so that the switch control signal can be arbitrarily operated according to the user's judgment regarding the illuminance state of the subject. It can also occur.

The signal selecting means 20 has four switch units SW1, SW2, SW3 and SW4, and each switch unit can be composed of, for example, an analog switch. Each switch unit can be formed by, for example, an analog switch. Each switch unit selects the signal path under the middle illuminance and the high illuminance indicated by the solid line or the signal path under the low illuminance indicated by the dotted line by the low or high level of the switch control signal.

The first delay means indicated by reference numeral 30 delays the output signal of the first switch unit SW 1 by 1H and supplies one delayed output signal to its output terminal N2. The indicated second delay means further delays the output signal of the first delay means 10 by 1H and supplies the first and second delayed output signals to its first and second output terminals N3 and N4, respectively. The configuration of the first delay means 30 according to an embodiment of the present invention comprises a second clamp circuit for clamping the output signal of the first switch unit SW1 in the signal selection means 20 to a predetermined dc level. , A second buffer for buffering the output of the second clamp circuit, a first delay line DL1 for delaying the output of the second buffer by 1H, and a buffering of the output of the first delay line. And a third buffer for

As shown in FIG. 2, the second clamp circuit has a clamping capacitor C5, a switching transistor Q2, a clamping voltage generating capacitor C6, and a resistor R13. It is formed in the same manner as that of the first clamp circuit in the control signal generating means 10. However, the input terminal of the capacitor C5 is connected to the output terminal of the first switch unit SW1. The connection between the transistors Q5 and Q7 and the emitter resistors R14 and R15, which form the second and third buffers respectively installed at the input and output ends of the first delay line DL1, is the same as that of the first buffer described above. Is formed by.

The second delay means according to one embodiment of the present invention includes a third clamp circuit for clamping the output signal N2 of the first delay means 30 to a predetermined dc level, and a third clamp circuit. A fourth buffer for buffering the output of the 3 clamp circuit, a second delay line DL2 for further delaying the output of the fourth buffer by 1H, and a buffer of the output of the second delay line DL2. And a fifth buffer for supplying the first delayed output signal N3 of the second delay means, and the first delayed output signal from the fifth buffer is voltage-divided into the second delayed output signal N4 of the second delay means. And a voltage divider for supplying the voltage. Here, as the third clamp circuit, the clamping capacitor C7 that receives one delayed output signal N2 of the first delay means 30, the switching transistor Q3, the clamping voltage generating capacitor C8, and the resistor. The connection between R16 is formed in the same manner as that of the second clamp circuit described above. In addition, the transistor and emitter resistance pairs (Q6 and R17) and (combined resistance of Q8 and R18 and R19) provided at both ends of the second delay line DL2 are respectively the fourth and fifth by the above-mentioned method. Form a buffer. The singular point of the second delay means 40 shown in FIG. 2 is that the emitter of the transistor Q8 is set to the first delay output terminal N3 of the second delay means 40, while the voltage dividers R18 and R19 forming the emitter resistance are connected. The intermediate tap is used as the second delay output terminal N4 of the second delay means 40. When the resistors R18 and R19 are formed of variable resistors, the signal level of the second delay output terminal N4 can be made equal to or smaller than the signal level of the first delay output terminal N3. In the preferred embodiment of the present invention, the level of N4 is preferably 1/2 of the level of N3.

On the other hand, the above-mentioned clamping pulse input Cp is commonly applied to the bases of the transistors Q2 and Q3 in order to synchronize the above-mentioned first, second and third clamp circuits. Then, in order to simplify the configuration of the clamping voltage generator for supplying the clamping voltage to the emitters of the switching transistors Q2 and Q3, the emitters of the switching transistors Q2 and Q3 are the same as those in the first clamp circuit. Together with the emitter of the switching transistor Q1, it is commonly connected to an intermediate connection point between the resistors R10 and R11.

On the other hand, the first calculation means 50 adds the brightness signal input through the output terminal N1 of the first buffer and the output signal of the fourth switch unit SW4 to add the first and second addition output signals N5 and N6 is supplied. According to one embodiment of the present invention, the first calculating means includes an adder circuit for adding the input luminance signal N1 clamped to a predetermined dc level and the output signal of the fourth switch unit SW4. The output of the adder circuit is buffered to supply the first addition output signal N 5 of the first calculation means 50, and the first addition output signal N 5 from the sixth buffer is voltage-divided. It is composed of voltage dividers R25 and R26 for supplying the second addition output signal N6 of the first calculation means 50. In the example shown in FIG. 4, the adder circuit is formed by including an OP amplifier OP3 and resistors R20, R21, R22, R23 and R24. Here, the input luminance signal N1 that is the first input signal of the adder circuit is applied to the non-inverting terminal of the OP amplifier OP3 via the resistor R20, and the output signal of the fourth switch unit SW4 that is the second input signal is the resistance. Since it is commonly applied to the non-inverting terminal of the OP amplifier OP3 via R21, the OP amplifier OP3 outputs the addition signal of both input signals to its output terminal.

However, the fourth switch unit SW4 outputs the first delayed output signal N3 of the second delay means 40 to the high level when the low-level switch control signal S c is applied (that is, when the medium illuminance and the high illuminance are applied). When the level switch control signal Sc is applied (that is, when the illuminance is low), the second delay output signal N4 of the second delay means is selected and supplied to its output terminal, so that the addition output of the OP amplifier OP3 In the end, however, it varies depending on the level of the switch control signal S c.

Further, the transistor Q10 forming the sixth buffer in the first calculating means 50 outputs the first addition output signal N5 of the first calculating means 50 through its emitter, while the voltage dividers R25 and R26 are in between. At tab, the second addition output signal N6 of the first calculation means 50 is output. When this voltage divider is composed of a variable resistor, the level of N6 can be set equal to or smaller than the level of N5, but in the embodiment of the present invention, the level of N6 is set to 2/1 of the N5 level. ing.

The first switch unit SW1 in the signal selecting means 20 has a first input terminal for receiving an input luminance signal supplied through the output terminal N1 of the first buffer, and a first input terminal of the first calculating means 50. The first switch unit SW1 receives the signal of the first input terminal when the low-level switch control signal Sc is applied (that is, in the middle illuminance and the high illuminance). When the high level switch control signal Sc is applied (that is, when the illuminance is low), the signal from the second input terminal is selected and supplied to its output terminal.

The second switch unit SW2 has a first input terminal for receiving the second addition output signal N6 of the first calculation means 50 and a first input terminal for receiving the first delay output signal N 3 of the second delay means 40. Two input terminals are provided, and the second added output signal N6 is selected and output when the illuminance is medium and high, and the second delayed output signal is selected and output when the illuminance is low.

The second computing means indicated by reference numeral 60 is a subtraction circuit for subtracting the output signal from the output terminal of the second switch unit SW2 from one delayed output signal N2 from the first delay means 30. The contour correction signal is detected at a predetermined reference illuminance or higher, and a noise component corresponding to the difference between luminance signals vertically adjacent to each other is detected at a predetermined reference illuminance or lower. It is supposed to do. More specifically, the delay output signal N2 of the first delay means 30 is applied to the non-inverting terminal of the OP amplifier OP4 forming the subtraction circuit via the resistor R29, and the resistance is connected to the inverting terminal of the OP amplifier OP4. The output signal of the second switch unit SW2 is applied via R27, while a resistor R28 is provided between the inverting terminal of the OP amplifier OP4 and the ground, and a resistor R28 is provided between the inverting terminal of the OP amplifier OP4 and its output terminal. R30 is installed.

Here, if the N1, N2, and N3 signals under medium and high illuminance are described as OH, 1H, and 2H, respectively, the addition OP amplifier OP3 outputs the [OH + 2H] signal. Therefore, the second addition output N6 of the first calculation means 50 becomes [(OH + 2H) / 2] and is further supplied to the inverting terminal of the OP amplifier OP4 in the second calculation means 60 via the second switch unit SW2. .. Since the non-inverting terminal of the OP amplifier OP4 is supplied with one delayed output signal 1H from the first delay means 30, the OP amplifier OP4 eventually corresponds to [1H- (OH + 2H) / 2]. A contour correction signal such as 4e is output.

On the other hand, when the N1, N2, and N3 signals under low illuminance are displayed as OH ′, 1H ′, and 2H ′, respectively, the addition OP amplifier OP3 outputs a signal of [OH ′ + 2H / 2]. This output signal is adapted to be further input from the first addition output terminal N5 of the first calculation means 50 to the first delay means 30 and the second delay means 40 via the first switch unit SW1. The effect that the level of the luminance signal applied to the upper first and second delay means 30 and 40 is increased as compared with the original luminance signal OH 'is obtained. On the other hand, the delayed output signal 1H 'from the first inversion means 30 is applied to the non-inverting terminal of the subtraction OP amplifier OP4, and the first delay output of the second delay means 40 is applied to its inverting terminal. Since the signal 2H 'is applied through the second switch unit SW2, the OP amplifier OP4 generates a noise component corresponding to the difference [1H'-2H'] between the luminance signals vertically adjacent to each other at its output terminal. Detect and output.

In one embodiment of the present invention, the third switch unit SW3 in the signal selecting means 20 has one common input terminal for receiving the output signal of the OP amplifier OP4 for subtraction described above. And the contour correction signal output from the OP amplifier OP4 is switched to the first output terminal when the illuminance is high, and the detection noise component output from the OP amplifier OP4 is switched to the second output terminal when the illuminance is low. It is like this.

The third operation means 70 as the final stage is provided with one delayed output signal 1H of the first delay means 30 and the third switch based on the level of the switch control signal Sc of the control signal generation means 10. The addition operation with the contour correction signal from the first output terminal of the unit SW3, or one delayed output signal 1H 'of the first delay means 30 and the second output terminal of the third switch unit SW3 It is formed by an adder / subtractor circuit that performs a subtraction operation with the detected noise component, and a seventh buffer for buffering the output of this adder / subtractor circuit. In the embodiment of FIG. 2, one output terminal N2 of the first delay means 30 is connected to the non-inverting terminal of the OP amplifier OP5 which constitutes the adder / subtractor circuit via the resistor R32, and the third switch The first output terminal of the unit SW3 is commonly connected via the resistor R31. The second output terminal of the third switch unit SW3 is connected to the inverting terminal of the OP amplifier OP5 via the resistor 33, and the resistor R34 is connected between the inverting terminal of the OP amplifier OP5 and the ground. A resistor R35 is installed between the inverting terminal and the output terminal of the OP amplifier OP5. The output terminal of the OP amplifier OP5 is applied to the base of the transistor Q9 of the seventh buffer through the resistor R36, and the output of the third computing means 70 is adapted to be extracted from the emitter of the transistor Q9.

In the adder / subtractor circuit having the above-described configuration, when the illuminance is equal to or higher than the predetermined reference illuminance (that is, medium illuminance and high illuminance), only the non-inverting terminal of the OP amplifier OP 5 has the first illuminance. Since the delay output signal 1H from one output terminal N2 of the delay means 30 and the contour correction signal from the first output terminal of the third switch unit SW3 are simultaneously applied, the OP amplifier OP5 effectively outputs [1H + contour correction]. Signal is added to the output signal, and finally a contour-corrected luminance signal is provided to the output terminal Yo as shown in FIG.

On the contrary, under the predetermined reference illuminance (that is, low illuminance), only the delayed output signal 1H ′ from the output terminal N2 of the first delay means 30 is applied to the non-inverting terminal of the OP amplifier OP5. Then, the detection noise component from the second output terminal of the third switch unit SW3 is applied to the inverting terminal of the OP amplifier OP5. Therefore, the OP amplifier OP5 at this time has a [1H'-detection noise component] By performing the subtraction operation, a level-increased and noise-free luminance signal can be finally provided to the output terminal Yo.

It should be noted that the present invention is not limited to the above-mentioned embodiment, but can be modified as necessary.

[0049]

[Effect of the device]

 Since the video signal processing circuit of the present invention is constructed and operates in this way, the components of the contour compensator that have been used so far are included to the maximum extent, and contour compensation is performed under medium and high illuminance. With respect to the operation, the sensitivity improving operation can be automatically performed under low illuminance, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing circuit of the present invention.

FIG. 2 is a schematic circuit diagram of FIG.

FIG. 3 is a configuration diagram of a contour compensation device according to a conventional technique.

4 is a drawing showing signals of various parts of the apparatus of FIG.

[Explanation of symbols]

 10 control signal generating means 20 signal selecting means 30 first delay means 40 second delay means 50 first calculating means 60 second calculating means 70 third calculating means Q1, Q2, Q3 clamping transistors C3, C5, C7 clamping capacitors Q4 to Q10 buffer transistors DL1 and DL2 delay lines SW1 to SW4 first to fourth switch units OP1 non-inverting amplifier OP amplifier OP2 comparator OP amplifier OP3 addition circuit OP amplifier OP4 subtraction circuit OP amplifier OP5 addition / subtraction circuit OP amplifier

Claims (8)

[Scope of utility model registration request] 1. A control signal generating means for generating a switch control signal based on the level of an input luminance signal, and a switching operation in response to the switch control signal output from the control signal generating means. The signal selection means formed by the first, second, third and fourth switch units, and the input luminance signal and the output signal of the fourth switch unit are added to generate the first and second added output signals. A first calculation means, an input luminance signal applied to a first input terminal thereof and a second luminance signal thereof;
The first switch unit for selecting one of the first addition outputs of the first calculation means applied to the input terminal according to the control signal from the control signal generation means and supplying the selected one to the output terminal; First delay means for delaying the output signal of the switch unit by 1H to output one delay signal; and first delay means for further delaying the output signal of the first delay means by 1H.
And second delay means for outputting a second delay signal, and one of the first and second delay output signals of the second delay means applied to the first and second input terminals thereof, respectively.
The fourth switch unit for selecting one of them according to the control signal of the control signal generating means and supplying it to the output terminal thereof, and the second delay means of the first delay means applied to the first input terminal thereof.
The summed output signal and the second applied to its second input terminal
The second switch unit for selecting one of the second delay output signals of the delay means by the control signal of the control signal generating means and supplying it to its output terminal; and the second switch unit from the delay output signal of the first delay means. A second arithmetic means for subtracting an output signal of the two-switch unit to generate a subtraction output signal applied to one input terminal of the third switch unit; and a second arithmetic means of the second arithmetic means applied to the one input terminal. Based on the third switch unit for selectively supplying the other two types of subtraction output signals to the first or second output terminal thereof by the control signal of the control signal generating means, and the control signal of the control signal generating means. The first
Addition operation of one delayed output signal of the delay means and the output signal from the first output terminal of the third switch unit, or one delayed output signal of the first delay means and the third switch unit and the second output A video signal processing circuit having a third arithmetic means for selectively performing a subtraction operation with an output signal from a terminal. 2. The control signal generating means includes a first clamp circuit for clamping the input luminance signal to a predetermined dc level, and a first clamp circuit for buffering the output of the first clamp circuit. A buffer, a non-inverting amplifier for amplifying the output of the first buffer without a polarity change, and a comparator for comparing with a predetermined mode switching reference voltage of the non-inverting amplifier. The video signal processing circuit according to item 1. 3. The video signal processing circuit according to claim 1, wherein the control signal generating means is formed by a manual switch that can be manually operated. 4. The second delay means includes a second clamp circuit for clamping the output signal of the first switch unit in the signal selection means to a predetermined dc level, and the second clamp circuit. A second buffer for buffering the output of the circuit; a first delay line for delaying the output of the second buffer by 1H; and a third buffer for further buffering the output of the first delay line. The video signal processing circuit according to claim 1, comprising: 5. The third delay circuit includes a third clamp circuit for clamping the output signal of the first delay circuit to a predetermined dc level, and a buffer for outputting the output of the third clamp circuit. A fourth buffer for ringing, a second delay line for further delaying the output of the fourth buffer by 1H, and an output of the second delay line for further buffering to provide a first delay output of the second delay means. It is characterized by comprising a fifth buffer for supplying a signal and a voltage divider for voltage-dividing the first delay output from the fifth buffer and supplying a second delay output signal of the second delay means. The video signal processing circuit according to claim 1. 6. The adder circuit for adding the input luminance signal clamped to a predetermined dc level and the output signal of the fourth switch unit, and the output of the adder circuit. A sixth buffer for buffering and supplying a first addition output signal of the first calculation means, and a second addition output signal of the first calculation means by dividing the voltage of the first addition output signal from the sixth buffer. 2. The video signal processing circuit according to claim 1, further comprising a voltage divider for supplying the. 7. The second arithmetic means is formed by a subtraction circuit for subtracting one delayed output signal from the first delay means and an output signal from an output terminal of the second switch unit, Formed to detect and output a contour correction signal above a predetermined reference illuminance, and to detect and output a noise component corresponding to the difference between vertically adjacent luminance signals below a predetermined reference illuminance. The video signal processing circuit according to claim 1, which is provided. 8. The third arithmetic means adds the one delayed output signal of the first delay means and a contour correction signal from the first output terminal of the third switch unit, or An adder / subtractor circuit for performing a subtraction operation of one delayed output signal of the first delay means and a detection noise component from the second output terminal of the third switch unit, and an output of the adder / subtractor circuit is buffered. Output a contour-corrected luminance signal above a predetermined reference illuminance, and a luminance signal whose level is increased and noise is removed below a predetermined reference illuminance. The video signal processing circuit according to claim 1, wherein the video signal processing circuit is formed so that