JPH05235969A - Inter-processor communication test system - Google Patents

Abstract

PURPOSE:To realize the communication test in the congestion state with respect to the inter-processor communication test system being a multi-processor system provided with a master processor and plural slave processors. CONSTITUTION:The master processor 100 is provided with a test object designation means 101 selecting a test object slave processor 200 and a test result analysis means 102 analyzing the result of test by a report from the slave processor, and the slave processor is provided with a communication start multiple address means 201 sending a communication start command signal to all other slave processors in the case of a test object, a test signal transmission means 203 transferring a test signal to the test object slave processor upon the receipt of the communication start command signal, a test signal loopback means 202 returning the transferred test signal to the slave processor being a sender, and a loopback signal analysis means 204 analyzing the returned test signal and reporting it to the master processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication test system in a multiprocessor system having a main processor and a plurality of slave processors.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing an example of a conventional multiprocessor system. The multiprocessor system shown in FIG. 5 includes one monitoring processor (MPR) 1 for monitoring the operating states of all exchanges, and N call processing processors (CPR) for sharing and processing calls originating in the exchange.
2 (individual call processor (CPR) 2-1 to 2
-N, the same applies hereinafter), and the monitoring processor (MPR) 1 is connected to each call processing processor (CPR) 2 via an interprocessor communication path 3.

Within the supervisory processor (MPR) 1, one central control unit (CC) 11 and N inter-processor communication control units (CCA) 12 are provided, and the central control unit (CC) is provided. Reference numerals 11 are connected to the interprocessor communication paths 3 via interprocessor communication control units (CCA) 12, respectively.

Further, each call processor (CPR) 2 is provided with one central control unit (CC) 21 and one inter-processor communication control unit (CCA) 22,
Each central controller (CC) 21 is connected to the interprocessor communication path 3 via an interprocessor communication controller (CCA) 22.

The central control unit (CC) 11 in the supervisory processor (MPR) 1 is respectively a supervisory processor (MP).
R) 1 interprocessor communication controller (CCA) 12,
Interprocessor communication path 3 and call processor (CP
Various data is transmitted / received to / from the central control unit (CC) 21 in each call processing processor (CPR) 2 via the inter-processor communication control unit (CCA) 22 in R) 2.

Therefore, the central processing unit (CC) 11 in the supervisory processor (MPR) 1 and each call processor (C)
Communication with the central controller (CC) 21 in the PR) 2 is executed via paths independent of each other and does not conflict with each other.

Therefore, even when the communication function between the supervisory processor (MPR) 1 and each call processor (CPR) 2 is tested, the supervisory processor (MPR) 1 and each call processor (CPR) 2 are to be tested. Only the communication function between them is tested individually, and the test is not required in the state where the call processors (CPR) 2 compete with each other and communicate with the monitoring processor (MPR) 1.

[0008]

As is apparent from the above description, in the conventional multiprocessor system, the supervisory processor (MPR) 1 and each call processing processor (CPR) 2 are independent interprocessor communication paths 3.
The call processors (CPR) 2 are connected to each other and communicate with each other independently of each other.
R) 1 and each call processing processor (CPR) 2 also when testing the communication function, the monitoring processor (MPR) 1
The communication function between the call processing processor (CPR) 2 and each call processing processor (CPR) 2 is only individually tested.
R) 2 competes with each other to monitor processor (MPR) 1
No tests have been performed in communication with.

Therefore, the monitoring processor (MPR) 1 and the plurality of call processing processors (CPR) 2 are connected via a ring bus capable of high speed communication, and the monitoring processor (M
In the case of a multiprocessor system in which the PR) 1 and each call processing processor (CPR) 2 compete with each other to communicate via a ring bus, there is no conventional interprocessor communication test. A communication test in a competitive state is required.

It is an object of the present invention to realize a communication test in a race condition, which is required when a main processor and a plurality of slave processors are connected by a ring transmission line.

[0011]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 100 is a main processor, 2
00 is a plurality of slave processors, 300 is the main processor 10
It is an annular transmission line that connects 0 and a plurality of slave processors 200.

Reference numeral 101 denotes a main processor 10 according to the present invention.
It is a test object designating means provided in 0. 102 is a test result analysis means provided in the main processor 100 according to the present invention.

201 is a slave processor 20 according to the present invention.
It is a communication start broadcasting means provided in 0. 202 is a test signal folding means provided in the slave processor 200 according to the present invention.

203 is a slave processor 20 according to the present invention.
0 is a test signal transmitting means. Reference numeral 204 is a folded signal analysis means provided in the slave processor 200 according to the present invention.

[0015]

The test target designating means 101 selects the slave processor 200 to be tested and notifies each slave processor 200 via the ring-shaped transmission path 300.

When the self-slave processor 200 is designated by the master processor 100 as a test target, the communication start broadcast means 201 sends a signal to all other slave processors 200 to start communication. It is transmitted in a broadcast format via the ring-shaped transmission path 300.

When the self-slave processor 200 is designated by the main processor 100 as other than the test target, the test signal transmitting means 203 receives a signal from the slave processor 200 designated as the test target to start communication. By doing so, a predetermined test signal is transmitted to the annular transmission line 3
00 to the slave processor 200 designated as the target of the test.

When the self-slave processor 200 is designated by the main processor 100 as a target of the competition test, the test signal folding means 202 sends a signal instructing the start of communication by the communication start broadcasting means 201, and then other The test signals transferred from all of the slave processors 200 via the ring-shaped transmission path 300 are returned back to the transmission-source slave processors 200 via the ring-shaped transmission path 300.

When the self-slave processor 200 is designated by the main processor 100 as a target other than the test target, the loopback signal analyzing unit 204 transfers the test signal by the test signal transmitting unit 203 and then designates it as the test target. The normality of the test signal returned from the slave processor 200 via the annular transmission line 300 is analyzed, and the analysis result is returned to the main processor 100 via the annular transmission line 300.

The test result analysis means 102 analyzes the test result based on the analysis result returned from the slave processor 200 other than the test target. The test signal transmitting means 203
Is considered to transfer a test signal containing different data for each slave processor 200.

Further, it is considered that the test signal transmitting means 203 repeatedly transfers the test signal a different number of times for each slave processor 200. Therefore, a test can be executed in the case where all slave processors communicate with each other by competing with each other via the circular transmission path, and the reliability of the multiprocessor system is improved.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the inter-processor communication test process in FIG. 2, and FIG. 4 is an example of the frame format in FIG. It is a figure. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, a monitoring processor (MPR) 1 is shown as the main processor 100 in FIG.
A call processor (CPR) 2 is shown as the slave processor 200 in FIG. 1, a ring bus 4 is shown as the ring transmission line 300 in FIG. 1, and the test target designating means 101 and the test result analyzing means 10 in FIG.
2, a test target designating unit (TST) 111 and a test result analyzing unit (TAN) 112 are provided in the central controller (CC) 11 in the monitoring processor (MPR) 1, and the communication start broadcasting means in FIG. A communication start broadcast unit (BRC) 211, an echo frame transmission unit (ECS) 212, and a response frame analysis unit (RPT) 213 as 201, a test signal transmission unit 203, and a return signal analysis unit 204, respectively, are included in each call processor (CPR). ) 2
A central processing unit (CC) 21 provided therein, and a response frame return unit (ECH) 231 as the test signal return unit 202 in FIG. 1 includes a call processing processor (CPR).
It is provided in the protocol controller (PRC) 23 in the No. 2 network.

In FIG. 2, the communication start broadcasting unit (B
RC) 211 and response frame return unit (ECH) 23
1 is shown only in the call processor (CPR) 2-1
The echo frame transmitter (ECS) 212 and the response frame analyzer (RPT) 213 are shown only in the call processors (CPR) 2-2 to 2-N.

Further, the central control unit (CC) 21 in each call processor (CPR) 2 has a test data TD and a test instruction data TC necessary for an inter-processor communication test.
D is set in advance.

The test data TD is data (one word) used when each call processor (CPR) 2 creates an echo frame d to be transferred in a test process described later.
And each call processor (CPR) 2-1 to 2-
It is also possible to set different data for each N.

Further, the test instruction data TCD is used when each call processor (CPR) 2 transfers the echo frame d transferred in a test process to be described later and the number of transfer times indicating the number of repeated transfer frames and each echo frame d. The number of transfer words indicating the number of test data TD (one word) to be used is specified, and each call processor (CPR) is also specified.
It is also possible to set different data for each of 2-1 to 2-N.

In FIG. 2, the test data TD and the test instruction data TCD are the call processor (CPR).
2-2 to 2-N, the call processor (C
PR) 2-1 is omitted.

2 to 4, when the monitoring processor (MPR) 1 starts the inter-processor communication test in the multiprocessor system, the test target designating unit (TST) 111 in the central control unit (CC) 11 is Select the call processor (CPR) 2 to be tested,
For example, the call processor (CPR) 2-1 is determined.

Next, the test target designating unit (TST) 111 in the monitoring processor (MPR) 1 has all the call processors (CPR) 2-except the call processor (CPR) 2-1 which is determined to be the test target. 2 to 2-N, echo frame transmitters (ECS) 212-2 to 21 provided in the respective central control units (CC) 21-2 to 21-N
Frame reception instruction frame a for activating 2-N
Are transferred via the ring bus 4.

The various frames transferred by the supervisory processor (MPR) 1 and each call processor (CPR) 2 via the ring bus 4 have the structure shown in FIG. A header portion H composed of a long DL, a destination address DA and a source address SA;
It is composed of a data section DATA.

Call Processor (CPR) 2-2 through 2
-N, each protocol controller (PRC) 23
-2 to 23-N are call processing processors (CP
R) Frame reception instruction frame a addressed to 2-2 to 2-N
Each corresponding central control unit (CC)
21-2 to 21-N.

The central control units (CC) 21-2 to 21-N to which the frame reception instruction frame a is transmitted are respectively incorporated in the echo frame transmitter (ECS) 212-.
2 to 212-N are activated to prepare to receive the communication start broadcast frame c scheduled to be transferred from the call processor under test (CPR) 2-1.

Next, the test target designating unit (TST) 111 in the monitoring processor (MPR) 1 sends the test target call processing processor (CPR) 2-1 to the central controller (CC) 2
Communication start broadcasting unit (BRC) 2 provided in 1-1
Test start instruction frame b for activating 11-1
Transfer via the circular bus 4.

In the call processor (CPR) 2-1, when the protocol controller (PRC) 23-1 receives the test start instruction frame b addressed to the own call processor (CPR) 2-1, the corresponding central control unit Device (CC) 21
To -1.

The central control unit (CC) 21-1 to which the test start instruction frame b is transmitted activates the built-in communication start broadcast unit (BRC) 211-1. The activated communication start broadcast unit (BRC) 211-1 creates a communication start broadcast frame c having a communication start instruction field in the data part DATA, and the protocol control device (PRC) 23-1 and the ring bus 4 are used. Each call processor (CP
R) Transfer to 2-2 to 2-N.

Call Processor (CPR) 2-2 to 2
-N, each protocol controller (PRC) 23
-2 to 23-N are call processing processors (CP
R) When receiving the communication start broadcast frame c addressed to 2-2 to 2-N, the corresponding central control units (CC) 21
-2 to 21-N.

The echo frame transmitters (ECS) 212-2 to 212-N in the central control units (CC) 21-2 to 21-N, to which the communication start broadcast frame c is transmitted,
Based on the set test instruction data TCD, the test data TD is also used by the number of words to be transferred, the destination address DA is used as the address of the test target call processor (CPR) 2-1, and the source address SA is set to each own call processor ( CP
R) An echo frame d having addresses of 2-2 to 2-N is created, and the call processor under test (CPR) 2 under test is passed through the protocol control devices (PRC) 23-2 to 23-N and the ring bus 4. Transfer to -1.

In FIG. 3, the echo frame created by the call processor (CPR) 2-2 is referred to as d _2, and the call processor (CPR) 2-2 repeatedly transfers the echo frame d ₂ for n ₂ frames. The echo frame created by the call processor (CPR) 2-N is referred to as d _N, and the call processor (CPR) 2-
N indicates that the echo frame d _N is repeatedly transmitted by n _N frames.

In the call processor (CPR) 2-1, the echo control frames (PRC) 23-1 are transferred from the call processors (CPR) 2-2 to 2-N and echo frames d _{2 to} d _N are transferred. Upon receiving a response frame back portion (ECH) 231-1 start, interchanged with the destination address DA of each echo frame d ₂ to d _N received the source address SA response frame e ₂ to e
_N is created and returned to each call processor (CPR) 2-2 to 2-N via the ring bus 4.

In the above process, each call processor (CP
R) 2-1 to 2-N compete with each other and each echo frame d _{2 to} d _N and each response frame e _{2 to} e
_N is transferred via the ring bus 4.

In each call processor (CPR) 2-2 to 2-N, the protocol controller (PRC) 23
-2 to 23-N are call processing processors (CP
Upon receiving the response frame e ₂ through e _N destined R) 2-2 through 2-N, respectively corresponding central controller (CC) 2
1-2 to 21-N.

The central control units (CC) 21-2 to 21-N to which the response frames e _{2 to} e _N are transmitted activate the response frame analysis units (RPT) 213-2 to 213-N incorporated therein. ..

Each response frame analysis unit (RP
T) 213-2 to 213-N are data portions DATA of the echo frames d _{2 to} d _N transferred by the corresponding echo frame transmitting units (ECS) 212-2 to 212-N.
And the data portion DATA of the corresponding response frame e _{2 to} e _N returned from the call processor (CPR) 2-1.
Analysis result notification frames f _{2 to} f _N in which the verification results (match / mismatch) are used as the data part DATA.
And the corresponding protocol control device (PR
C) Transfer to the monitoring processor (MPR) 1 via 23-2 to 23-N and the ring bus 4.

In the monitoring processor (MPR) 1,
When the protocol control unit (PRC) 13 receives the analysis result notification frames f _{2 to} f _N transferred from the respective call processors (CPR) 2-2 to 2-N, the protocol control unit (PRC) 13 transfers them to the corresponding central control unit (CC) 11. To do.

The central control unit (CC) 11 to which the analysis result notification frames f _{2 to} f _N are transmitted activates the test result analysis unit (TAN) 112. The activated test result analysis unit (TAN) 112 is connected to each call processor (CPR).
By analyzing the data part DATA of the analysis result notification frames f _{2 to} f _N transferred from 2-2 to 2-N, the multiprocessor system in the case where the call processor (CPR) 2-1 is set as a test target The inter-processor communication test result of is determined.

As is apparent from the above description, according to this embodiment, the supervisory processor (MPR) 1 is each call processing processor (CPR) 2 which constitutes a multiprocessor system.
-1 is sequentially selected as the test target call processor (CPR) 2, and a call processor (CPR) other than the test target is selected.
2-2 to 2-N to the call processor under test (CP
The echo frame d is transferred to the R) 2-1 and the response frame e is returned from the call processor under test (CPR) 2-1 so that the monitoring processor (MP
R) The test of inter-processor communication in the multiprocessor system except 1 can be executed.

It is to be noted that FIGS. 2 to 4 are merely examples of the present invention until now, for example, a call processor to be tested (CP).
R) is not limited to 2-1 and any call processor (CPR) 2-1 to 2-N may be considered as a test target, but in any case, the effect of the present invention Does not change. Also, a communication start broadcast unit (BRC) 211, a response frame return unit (ECH) 231, an echo frame transmission unit (ECS) 212, and a response frame analysis unit (RP).
By providing T) 213 also in the monitoring processor (MPR) 1, an inter-processor communication test including the monitoring processor (MPR) 1 is possible, but the effect of the present invention does not change in such a case. Further, the frame format to be the subject of the present invention is not limited to the one shown in the figure, and many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the main processor 10 to which the present invention is applied
0 and slave processor 200 are illustrated monitor processor (MPR) 1 and call processor (CPR) 2
It goes without saying that it is not limited to.

[0049]

As described above, according to the present invention, in the multiprocessor system, a test can be executed in the case where all slave processors communicate with each other by competing with each other via the ring transmission line. , The reliability of the multiprocessor system is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of the inter-processor communication test process in FIG.

FIG. 4 is a diagram showing an example of a frame format in FIG.

FIG. 5 is a diagram showing an example of a conventional multiprocessor system.

[Explanation of symbols]

 1 Monitoring Processor (MPR) 2 Call Processor (CPR) 3 Interprocessor Communication Path 4 Ring Bus 11, 21 Central Control Unit (CC) 12, 22 Interprocessor Communication Control Unit (CCA) 13, 23 Protocol Control Unit (PRC) 100 Main Processor 101 Test Target Designating Means 102 Test Result Analyzing Means 111 Test Target Designating Unit (TST) 112 Test Result Analyzing Unit (TAN) 200 Slave Processor 201 Communication Start Broadcasting Means 202 Test Signal Returning Means 203 Test Signal Sending Means 204 Returning Signal analysis means 211 Communication start broadcast unit (BRC) 212 Echo frame transmission unit (ECS) 213 Response frame analysis unit (RPT) 231 Response frame return unit (ECH) 300 Circular transmission line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 15/16 450 Z 9190-5L

Claims (3)

[Claims] 1. A multiprocessor system in which a main processor (100) and a plurality of slave processors (200) are connected by an annular transmission path (300), wherein the main processor (100) is a slave processor to be tested. 200) and select the ring transmission line (30
0) A test for analyzing the test result based on the analysis result returned from the test target designating means (101) notifying each slave processor (200) and the slave processor (200) other than the test target. A result analysis means (102), and the sub processor (200) is connected to the main processor (1).
00) when specified as a test target, a signal for instructing the start of communication to all other slave processors (200) is sent in a broadcast format via the ring transmission path (300). When the communication start broadcast means (201) to be transmitted and the main processor (100) designate as a test target, the communication start broadcast means (201) transmits a signal instructing to start the communication. After that, from all the other slave processors (200) to the ring transmission line (3
00) for transmitting the test signal via the ring-shaped transmission line (300) to the slave processor (2) which is the transmission source.
(00) for returning the test signal back to (00)
And when it is designated by the main processor (100) as a target other than the test target, by receiving a signal instructing to start the communication from the slave processor (200) designated as the test target, From the main processor (100), a test signal transmitting means (203) for transferring the obtained test signal to the slave processor (200) designated as the target of the test via the ring transmission path (300). When the test signal is transmitted by the test signal transmitting means (203) when the test signal is designated as a target other than the test target, the slave processor (200) designated as the test target transfers the ring transmission path (300). The normality of the test signal returned via the circuit is analyzed, and the analysis result is passed through the ring transmission line (300) to the main processor (100). Inter-processor communication test system, characterized by providing a folding reply No. analyzing means (204) to be returned. 2. The inter-processor communication test method according to claim 1, wherein the test signal transmitting means (203) transfers the test signal containing different data for each slave processor (200). 3. The inter-processor communication test method according to claim 1, wherein the test signal transmitting means (203) repeatedly transfers the test signal a number of times different for each slave processor (200). ..