JPH0728763A - Broadcast communication method and broadcast routing device - Google Patents

Abstract

PURPOSE:To easily avoid the dead lock even at the time of random occurrence of broadcast requests in parallel computers by determining a specific routing chip as the broadcast routing chip for actual broadcast and transferring a message to this broadcast routing chip at the time of broadcast. CONSTITUTION:One specific broad, cast routing chip 10b for broadcast of 1:N (N>=2) communication is determined among routing chips 10a,... constituting a network. For example, a processor 20c requires broadcast communication, the processor 20c sends a broadcast message to the broadcast routing chip 10b through a routing chip 10c by 1:1 communication to request the broadcast communication. The broadcast routing chip 10b receives the broadcast message to transfer it to the other processors 10a to 10d, thus broadcasting it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadcast communication method and a broadcast routing device capable of avoiding a deadlock even when a plurality of broadcast communication requests are simultaneously generated in a parallel computer.

Broadcast communication in a parallel computer is a communication for sending a message of the same content from one processor to a plurality of other processors, and is one of important communication patterns in a parallel computer.

[0003]

2. Description of the Related Art As a communication control system of a parallel computer for efficiently performing broadcast communication with respect to a certain range of nodes, there is a system disclosed in Japanese Patent Laid-Open No. 3-102455. In this method, the data sent from another node is received by the reception processing unit for each direction. Next, the destination detection unit detects the destination information that specifies the range of the destination node in the data, and based on the detected destination information, the inter-node distance processing unit obtains the inter-node distance between that node and the destination node. Subsequently, the destination determination unit determines whether or not the data should be taken into the own node, determines whether or not the data needs to be transmitted and the transmission direction based on the distance information, and when the data needs to be transmitted. The data is transferred to the transmission processing unit for each direction, and the data is transferred.

Wormhole routing is adopted as a routing method for interconnection networks (networks) of many parallel computers. As a method for performing broadcast communication by wormhole routing quickly and efficiently, for example, Japanese Unexamined Patent Application Publication No. There is a broadcast communication system disclosed in Japanese Patent Publication No. 3-140035. In this method, a flit obtained by dividing a message into transfer units is provided with a header flit having broadcast communication range information at the beginning and a final flit at the end, and one node sequentially transmits to another node on the network, and the receiving node receives it. The range information is updated when referring to the header flit to indicate that the range information is to be transmitted to another node, the header flit is transmitted to the node in the transmission direction, and the flit that is subsequently transmitted. About the last flit, it is transmitted sequentially.

[0005]

Wormhole routing, while achieving low latency, occupies a channel, so deadlock may occur if broadcast communication is implemented by a mesh or torus. There are two causes of deadlock: channel occupancy and port occupancy. Here, the port means an interface of a communication path between the processor and the network.

FIG. 10 shows an example of deadlock due to port occupation in the prior art. Now, it is assumed that the processors 20a and 20d start broadcasting communication by wormhole routing almost at the same time. In wormhole routing, messages are sent from a routing chip connected to a transmission processor to the adjacent routing chips sequentially while securing paths.

It is assumed that the broadcast message sent by the processor 20a reaches the routing chip 100b from the routing chip 100a, the port of the processor 20b is secured, and the broadcast message is sent to the routing chip 100c. At this time, if the port of the processor 20c cannot be acquired due to the broadcast communication of the processor 20d, the port waits for an available port. On the other hand, the port of the processor 20c is assigned to the broadcast message of the processor 20d, and then the processor 20b is assigned.
When trying to acquire a port of
If the port cannot be acquired due to the broadcast of 0a and the port also waits for a free port, the ports will wait for a free port and deadlock will occur.

When a deadlock occurs, there is a method of eliminating the deadlock by detecting the occurrence of the deadlock by time monitoring, for example, and then releasing the port once by one or both and retrying again. However, this method has a problem that it takes time to detect a deadlock and it is inefficient because a retry must be performed.

To occupy the channel, the cause of the deadlock can be eliminated by virtualizing the channel and using a virtual channel system that makes it appear as if there are multiple channels. For example, a method known as structured channel routing may be adopted.

Similarly, it is conceivable that the port occupation can be solved by making the ports multi-ported. Multi-porting means that multiple messages can be simultaneously transferred from the network to the memory at the interface between the network and the memory. To this end, it is necessary to multiplex the number of interfaces to the processors in the routing chip to the extent that there is a possibility of competing broadcast communications, and the hardware cost thereof is considerably large.

It is an object of the present invention to solve the above problems and to easily avoid deadlock even if a broadcast communication request randomly occurs in a parallel computer.

[0012]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 10a, 10b, ... Represent a routing chip for transmitting / receiving and relaying messages in a network, and 20a, 20b ,.

According to the broadcast communication method of claim 1,
As shown in (A), in the routing chips 10a, ... Which constitute the network, 1 to N (where N ≧
2) Define one specific broadcast routing chip 10b for broadcasting communication.

For example, when the processor 20c requires broadcast communication, the processor 20c sends a 1 to the broadcast routing chip 10b via the routing chip 10c.
A broadcast message is sent by a one-to-one communication and a broadcast communication is requested (Fig. 1).

Upon receiving the broadcast message, the broadcast routing chip 10b transfers the broadcast message to the other processors 10a to 10d and broadcasts it (in FIG. 1). Figure 1
As shown in (B), each routing chip 10e, ...
When there are a plurality of ports (M) for sending a message from the respective processors 20e, ... Corresponding to each other, in the broadcast communication method according to claim 2, in the routing chips 10e ,. However, N ≧ 2) M specific broadcast routing chips 1 for broadcasting communication
Set 0e and 10g.

For example, when the processor 20f requires broadcast communication, the processor 20f sends a broadcast message via the routing chip 10f to the broadcast routing chip 10e or the broadcast routing chip 10g by one-to-one communication, Request broadcast communication.

The broadcast routing chip 10e or the broadcast routing chip 10g that has received the broadcast message
Transmits the broadcast message to the other processors 20e to 20h and broadcasts it.

According to the third aspect of the present invention, each broadcast routing chip has a FIFO (Fi
rstIn First Out) Transfers to another processor in a wormhole route using a buffer.

According to another aspect of the present invention, the processor requesting broadcast communication adds a message header for broadcast communication after the message header for one-to-one communication in the broadcast message to be sent to the broadcast routing chip, so that each broadcast The routing chip has a one-to-one correspondence with the received message.
The message header for communication is stripped, it is determined whether the next is a message header for broadcast communication, and if it is a message header for broadcast communication, the broadcast message is transferred to another processor.

According to the fifth aspect of the present invention, the identifier of the transmitting processor is added to the broadcast message, and the identifier of the transmitting processor in the broadcast message is compared with the identifier of its own processor in each routing chip.
If the identifiers match, then the broadcast message is filtered so that it is not received by the sending processor.

In the invention described in claim 6, as shown in FIG.
Routing chip 10 ₁₁, 10₁₂, ... two
Network by connecting in a two-dimensional torus or two-dimensional grid
A parallel computer consisting of multiple processors
And broadcast one-to-N (however, N ≧ 2) communication
A specific broadcast routing chip 10₁₁, 10_{twenty two}, 1
0₃₃, 10₄₄And arrange them diagonally. That
The processor requesting broadcast communication is a broadcast routine.
Send broadcast message to each of Guchip by one-to-one communication
And each broadcast route that received the broadcast message.
Swinging tip 10₁₁, 10_{twenty two}, 10₃₃, 10₄₄Is that
Broadcast messages to other processors in the column or row direction
Messages to be broadcast.

According to another aspect of the broadcast routing chip of the present invention, a transmission buffer for storing a message to be transmitted to another processor, a reception buffer for storing a message addressed to the own processor and received from another processor,
A receiving unit for receiving a message from another processor via the network, a transmitting unit for transmitting a message to the other processor via the network, and when the received message is not addressed to its own processor, the entire message is transmitted by the transmitting unit. To the destination determination unit to be transferred to, and when the received message is addressed to its own processor, receives the message from the destination determination unit, strips the message header, and if there is a further message header, sends the message to the buffer for transmission. To the buffer for receiving and if there is no message header, read the message stored in the buffer for transmitting, and analyze the message header to determine the direction to transmit. Select and send a message to the transmitter And a header analysis unit for feeding.

[0023]

A simple method for realizing random broadcasting without deadlock is to serialize a broadcasting processor by arbitration or the like so that a plurality of broadcasting communications are not performed at the same time. In architectures in which multiple processors are connected to the bus, the processor that acquires the bus is determined by arbitration. Therefore, in order to realize broadcasting on a network such as a torus, if a broadcast message from any processor is collected in a routing chip attached to one processor and broadcast from there, the message is serialized by the routing chip. (This becomes arbitration), the deadlock problem is solved. At this time, one store-and-forward (one reception and one transmission) is required.

Focusing on this point, the present invention realizes low-delay communication in which store-and-forward overhead is eliminated, and realizes broadcast communication in which deadlock does not occur. The basic principle is that the routing chip to be actually broadcast is determined to be a specific one, and when broadcasting, the message is transferred to the broadcast routing chip, and the broadcast routing chip does not receive the broadcast message in the memory and the wormhole Broadcast messages by routing.

In the case of the invention according to claim 1, for example, FIG.
In (A), since only the routing chip 10b actually broadcasts, the broadcast message is serialized by this, and deadlock due to contention is avoided.

In the case of the invention according to claim 2, for example, FIG.
In (B), if there are two ports between each routing chip 10e, ... And each processor 20e, ..., Two routing chips to be broadcast are determined in advance. In this example, the broadcast routing chips 10e, 10
It is g. Only these two routing chips 10e and 10g are actually broadcast, and even if the port is occupied by the broadcast communication, deadlock does not occur due to the lack of the port. Occupation of channels can be dealt with by using virtual channels.

By transmitting the broadcast message by the wormhole routing method as in the third aspect of the invention, low delay communication can be realized without copying the message to the memory of the processor.

According to the invention described in claim 4, by adding the message header for broadcast communication after the message header for one-to-one communication, the broadcast routing chip simply strips the message header. ，
Broadcast messages can be transferred with simple control.

As in the fifth aspect of the present invention, by providing the filter for discarding the broadcast message transmitted by the self processor in the routing chip, it is possible to prevent the broadcast message issued by the self processor from being received. .

According to the sixth aspect of the invention, the broadcast routing chips are arranged diagonally and broadcast in the column direction or the row direction, whereby distributed processing of broadcast communication is possible and dead of broadcast communication is possible. Locks can also be avoided.

By configuring the broadcast routing chip as in the invention described in claim 7, it is possible to easily construct a system for realizing the above broadcast communication method. This broadcast routing chip can be used as a normal routing chip without changing the hardware.

[0032]

FIG. 2 is a diagram showing a configuration example of a routing chip according to an embodiment of the present invention, FIG. 3 is an explanatory view of a message header used in the embodiment of the present invention, and FIG. 4 is an operation explanation of a destination determination unit shown in FIG. 5 and 5 are operation explanatory diagrams of the header strip section shown in FIG. 2, and FIG. 6 is an operation explanatory diagram of the header analysis section shown in FIG.

The routing chip 10 constituting the one-dimensional torus network is constructed as shown in FIG. 2, for example. In FIG. 2, 11 is a routing block for controlling transmission / reception of messages to / from the network, 12 is a transmission FIFO buffer, 13 is a reception FIFO buffer,
14 is a selector, 15 is a header analysis unit, 16L, 16R
Is a receiving unit, 17L and 17R are destination determining units, 18L and 18
R represents a transmitter, and 19 represents a header strip section.

When broadcasting, a broadcast message is transmitted to a predetermined routing chip 10 (this is called a broadcast routing chip). It should be noted that the broadcast routing chip and the normal routing chip that is not the same have the same hardware configuration in this embodiment. Whether each routing chip operates as a broadcast routing chip or a normal routing chip is determined by the header information of the message created by each processor. The broadcast routing chip also transfers messages in the one-to-one communication as in the conventional case.

As shown in FIG. 3A, the message is provided with a one-to-one communication header 30a at the beginning, and in the case of a broadcast message, a broadcast communication header 30b is further provided.
Is provided. Data 31 which is the content of the message follows.

The structures of the one-to-one communication header 30a and the broadcast communication header 30b are as shown in FIG. 3 (B). The header flag 32 indicates that it is the data 31 when it is "0", and indicates that this header is the one-to-one communication header 30a or the broadcast communication header 30b when it is "1". When the direction flag 33 is "0", it indicates that the message should be transmitted to the left, and when it is "1", the message is to be transmitted to the right. The destination field 34 represents the inter-node distance to the transfer destination. For example, when a message is sent up to three routing chips, the value of the destination field 34 is "3". The broadcast flag 35 is
"0" indicates a one-to-one communication, and "1" indicates a broadcast communication header.

The header of the broadcast message transferred to the broadcast routing chip is stripped by the header strip section 19. If the next header is a header for broadcast communication, it is transferred again to the transmission FIFO buffer 12, and if not, it is transferred to the reception FIFO buffer 13 and passed to the processor 20. The broadcast message is
By the analysis of the header analysis unit 15, it is broadcast to all the processors or the processors in the range designated by the transmission source.
This 1-to-N communication broadcast is disclosed in, for example, Japanese Patent Laid-Open No. 10245/1993.
It can be implemented using the method disclosed in Japanese Patent Laid-Open No.

The operation of each part of the routing block 11 shown in FIG. 2 will be described in more detail. Address determination unit 17
Upon receiving the message from the receiving units 16L and 16R, the L and 17R control as shown in FIG. First, in step 41, the value of the destination field 34 is subtracted by 1 from the message header. Then, in step 42, it is judged whether or not the value of the destination field 34 becomes 0, and if it becomes 0, the process proceeds to step 44. If it is not 0, in step 43, whether the broadcast flag 35 is 0, that is, a normal message (broadcast flag = 0)
Or a broadcast message (broadcast flag == 1). If it is a broadcast message, the process proceeds to step 44, and if it is a normal message, the process proceeds to step 45.

In the case of a message addressed to its own processor or a broadcast message, the entire message is transferred to the header strip section 19 in step 44. If it is neither a broadcast message nor a message addressed to its own processor, in step 45, the entire message is transferred to the transmission units 18R and 18L on the opposite side.

The header strip section 19 is the destination determination section 1
When the message is received from the 7L, 17R or the header analysis unit 15, the control is performed as shown in FIG. First, in step 51, the top message header is stripped.
Then, in step 52, it is determined whether or not the next header flag is 0. If the header flag is 0,
Since this is data indicating the content of the message, step 5
Go to 4. If the header flag is 1, it means that the header continues, so the routine proceeds to step 53.

In step 53, the entire message is transferred to the transmission FIFO buffer 12 for header analysis. In step 54, the data of the entire message after the header strip is transferred to the reception FIFO buffer 13.

The header analysis section 15 reads out the messages from the transmission FIFO buffer 12 one by one and controls them as shown in FIG. First, with respect to the message header, it is determined in step 61 whether or not the value of the destination field 34 is 0. If it is 0, the process proceeds to step 62, and if it is not 0, the process proceeds to step 63. The value of the destination field 34 is 0
If so, the entire message including the header is transferred to the header strip section 19 in step 62. If the value of the destination field 34 is not 0, it is determined in step 63 whether the broadcast flag 35 is 0, that is, whether it is a normal message (broadcast flag = 0) or a broadcast message (broadcast flag = 1). judge. If it is a broadcast message, the process proceeds to step 64, and if it is a normal message, the process proceeds to step 65.

In the case of a broadcast message, in step 64, the entire message including the header is transferred to the left and right transmitters 18L and 18R and broadcast. If it is not a broadcast message, the direction flag 33 is determined in step 65. If the direction flag 33 is 1, the entire message including the header is transferred to the right transmitter 18R in step 66, and the direction flag 33 is 0. Transfers the entire message including the header to the left transmitter 18L in step 67.

In the system of this embodiment, when the processor to be broadcast at a certain timing is predetermined, that is, when it is known that there is no possibility that deadlock will occur, broadcasting is performed. The processor may send the broadcast message directly to its routing chip without sending it to the broadcast routing chip. This is because the routing chip has the same structure as the broadcast routing chip and the one that does not. This corresponds to the case where there is no one-to-one communication header 30a in the message shown in FIG.

FIG. 7 shows an example of the structure when a two-dimensional torus is used. As shown in FIG. 7A, even when the routing chip 10 has a two-dimensional torus network configuration, the present invention can be similarly implemented. The same applies to the case of mesh instead of torus. The routing chip 10 at this time is configured as shown in FIG.

In the case of a two-dimensional torus, communication in the left-right direction (X direction) and communication in the up-down direction (Y direction) are required, so the X routing block 11X and the Y routing block 11Y are provided as routing blocks. Each of the X routing block 11X and the Y routing block 11Y has the same structure as the routing block 11 shown in FIG. X routing block 11 X or Y routing block 11
A selection switch S for switching the input source when writing a message from Y to the transmission FIFO buffer 12
There is W.

The header of the broadcast message in the two-dimensional torus or mesh is, for example, as shown in FIG. 7C, a header for X-direction one-to-one communication, a header for Y-direction one-to-one communication, and a header for X-direction broadcast communication. , Y direction broadcast communication header.

The entire system is shown in FIG. 8 (A), for example.
The configurations shown in (C) to (C) can be adopted. In FIG. 8, hatched routing chips are broadcast routing chips set for broadcasting. Figure 8
The example of (A) is an example when there is one routing chip that performs broadcasting. If there is a problem that access to the broadcast routing chips is concentrated, multiple broadcast routing chips can be used. At this time, it is necessary to make multiports for the number of broadcast routing chips.

In FIG. 8B, there are two broadcast routing chips for broadcasting to the entire processor. In this case, port duplication is necessary to prevent deadlock due to port occupation.

FIG. 8C shows an example of a system in which four broadcast routing chips are provided without being multiported. The broadcast routing chips are arranged diagonally as shown in the drawing, and each broadcast routing chip only performs broadcasting within the range shown by the dotted line, that is, broadcast communication in the row direction (X direction). Alternatively, only broadcast communication in the column direction (Y direction) may be performed.

FIG. 9 shows an example in which a filter is provided in the routing chip. In this method, since the message to be broadcast is broadcast from other than the transmitting processor that issued the broadcast communication request, the transmitting processor also receives the broadcast message issued by itself. It is possible to handle this broadcast message by the software in the processor so that the processor does not receive it and operate.
As shown in FIG. 9, the load of software can be reduced by providing the filter 90 in the routing chip 10.

In this embodiment, the identifier of the transmitting processor (processor ID) is inserted at the beginning of the header of the broadcast message or the data following the header. When the message is received, the filter 90 looks at the processor ID in the message and determines whether the transmission processor ID is the same as its own processor ID. If they are the same, discard the message and not receive it. That is, the filter 90 compares the processor ID in the message with its own processor ID, and when they are the same, does not transfer the message to the reception FIFO buffer 13.

[0053]

As described above, according to the present invention,
Deadlock due to broadcast communication can be avoided without increasing the number of ports between the network and the processor more than necessary. Also, it is possible to realize broadcast communication with little transfer overhead. The hardware for avoiding the deadlock can be easily realized only by providing a route from the routing block directly to the transmission buffer in the routing chip.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a configuration example of a routing chip according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a message header used in the embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of a destination determination unit shown in FIG.

5 is an operation explanatory view of the header strip section shown in FIG. 2. FIG.

FIG. 6 is an operation explanatory diagram of the header analysis unit shown in FIG. 2.

FIG. 7 is a diagram showing a configuration example of a two-dimensional torus.

FIG. 8 is a diagram showing an example of a system configuration according to an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration example in which a filter is provided.

FIG. 10 is a diagram illustrating a problem of the conventional technique.

[Explanation of symbols]

 10a, 10b, ... Routing chips 20a, 20b, ... Processor

Claims (7)

[Claims] 1. A broadcast communication method in a parallel computer comprising a plurality of processors (20) constituting a network by a routing device (10), wherein one to N (where N ≧ N) among the routing devices constituting the network.
2) A broadcast routing device (10b) for broadcasting communication is provided in one place, and a processor requesting broadcast communication sends a broadcast message to the broadcast routing device by one-to-one communication and receives the broadcast message. Is a broadcasting communication method characterized in that a broadcasting message is transferred to another processor for broadcasting. 2. A broadcast communication method in a parallel computer comprising a plurality of processors forming a network by a routing device (10), wherein the processor has M ports (where M ≧ 2) for receiving a message from the routing device. At this time, among the routing devices constituting the network, 1 to N (where N ≧ 2)
A processor that predetermines M broadcast routing devices (10e, 10g) for broadcasting communication and requests broadcast communication is
A broadcast communication method, wherein a broadcast message is sent to one of the broadcast routing devices by one-to-one communication, and the broadcast routing device receiving the broadcast message transfers the broadcast message to another processor for broadcasting. 3. The broadcast communication method according to claim 1 or 2, wherein the broadcast routing device transfers the received broadcast message to another processor by wormhole routing. 4. The broadcast communication method according to claim 1 or 2, wherein the processor requesting broadcast communication sets 1 in a broadcast message to be sent to the broadcast routing device.
A message header for broadcast communication is added after the message header for one-to-one communication, the broadcast routing device strips the message header for one-to-one communication of the received message, and next is a message header for broadcast communication. And a message header for broadcast communication, the broadcast message is transferred to another processor. 5. The broadcast communication method according to claim 1 or 2, wherein an identifier of a transmission processor is added to the broadcast message, and an identifier of the transmission processor in the broadcast message and an identifier of its own processor are added in each of the routing devices. A broadcast communication method characterized by filtering the broadcast message so that it is not received by the transmitting processor when the identifiers match by comparing with. 6. A broadcast communication method in a parallel computer comprising a plurality of processors forming a network by connecting a routing device (10) in a two-dimensional torus or a two-dimensional lattice form, in the routing device forming the network. , A plurality of broadcast routing devices for broadcasting 1 to N (where N ≧ 2) communication are diagonally arranged,
A processor requesting broadcast communication sends a broadcast message to each of the broadcast routing devices by one-to-one communication, and each broadcast routing device receiving the broadcast message sends the broadcast message to another processor in the column direction or the row direction. A broadcast communication method characterized by transmitting and broadcasting. 7. A broadcast routing device used in the broadcast communication method according to any one of claims 1 to 6.
0), which is a transmission buffer for storing messages to be transmitted to other processors, a reception buffer for storing messages addressed to the own processor received from other processors, and from other processors via the network. A receiving unit for receiving the message, a transmitting unit for transmitting the message to another processor via the network, and a destination determining unit for transferring the entire message to the transmitting unit when the received message is not addressed to the own processor, When the received message is addressed to its own processor, the message is received from the destination determination unit, the message header is stripped, and if there is another message header, the message is transferred to the buffer for transmission, and the message header is removed. If the message is transferred to the receiving buffer That a header strip section reads the stored in the buffer for outgoing messages, select the direction to be transmitted by analyzing the message header,
A broadcast routing device comprising: a header analysis unit that transfers a message to the transmission unit.