JPS6297444A - Data transmission equipment - Google Patents

Data transmission equipment

Info

Publication number
JPS6297444A
JPS6297444A JP60236870A JP23687085A JPS6297444A JP S6297444 A JPS6297444 A JP S6297444A JP 60236870 A JP60236870 A JP 60236870A JP 23687085 A JP23687085 A JP 23687085A JP S6297444 A JPS6297444 A JP S6297444A
Authority
JP
Japan
Prior art keywords
data transmission
command
device address
address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60236870A
Other languages
Japanese (ja)
Inventor
Takao Kato
孝雄 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60236870A priority Critical patent/JPS6297444A/en
Publication of JPS6297444A publication Critical patent/JPS6297444A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent crosstalk by allowing a data transmission equipment inserted between each processor and a data transmission line while being added with an equipment address to generate an equipment address check command and comparing the command with a received equipment address command. CONSTITUTION:Processors 1-4 are connected to a data transmission line 9 via data transmission equipments 5-8. The data transmission equipments 5-8 receive a signal from the processors 1-4 to analyze a command and to produce an equipment address check command, which is sent to the transmission line 9 together with an equipment address. Further, the data transmission equipments 5-8 receive a signal from the data transmission line 9 to analyze the command and when the address addressed to the own station is included, the message is sent to the processors 1-4 of the own station and when the address addressed to other station is included, an equipment address is added and the result is sent to the data transmission line 9. Thus, the presence of a data transmission equipment having the same equipment address as the own station equipment address is confirmed to prevent communication with an erroneous destination.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプロセッサ間ネソI・ワークシステムに用いら
れるデータ伝送装置の管理手段に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a management means for a data transmission device used in an inter-processor network I/work system.

〔概要〕〔overview〕

本発明は、プロセッサをデータ伝送路に結合し、自装置
に付された装置アドレスに基づいて他装置に接続される
データ伝送装置において、試験時に、他装置の装置アド
レスが(=J加される装置アドレスチェックコマンドを
送出し、このコマンドの内容と自装置の装置アドレスと
を比較することにより、 装置アドレスが他装置の装置アドレスと誤って同一アド
レスに付されることを防止することができるようにした
ものである。
The present invention provides a data transmission device in which a processor is coupled to a data transmission path and is connected to another device based on a device address assigned to the device itself.During a test, the device address of the other device is added (=J By sending a device address check command and comparing the contents of this command with the device address of the own device, it is possible to prevent the device address from being mistakenly assigned to the same address as the device address of another device. This is what I did.

〔従来の技術〕[Conventional technology]

従来例データ伝送装置には、プロセッサ間ネットワーク
システムのデータ伝送路上に同一の装置アドレスの付さ
れているデータ伝送が1台以上接続されていたときに、
これを判別する手段がない。
When one or more data transmission devices with the same device address are connected to the conventional data transmission device on the data transmission path of the inter-processor network system,
There is no way to determine this.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このようなデータ伝送装置では、データ伝送路」二に誤
って同一装置アドレスを持つデータ伝送装置が存在する
ときに、本来自局宛でない送信データであっても装置ア
ドレスが一致するという理由で自局宛データと判断し、
受信した旨の応答を送信元へ誤返送する欠点があった。
In such a data transmission device, when there is a data transmission device with the same device address on the data transmission path 2, even if the data transmission is not originally addressed to the local station, the data transmission device automatically sends data because the device addresses match. It is determined that the data is addressed to the station,
There was a drawback that a response indicating that it had been received was sent back to the sender by mistake.

本発明は、このような欠点を除去するもので、同一の装
置アドレスを持つデータ伝送装置を検知できる手段を有
するデータ伝送装置を捉供することを目的とする。
SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a data transmission device having means for detecting data transmission devices having the same device address.

c問題点を解決するための手段〕 本発明は、複数のプロセッサのそれぞれとデータ伝送路
とを接続する経路上に挿入され、装置アドレスが付され
たデータ伝送装置において、装置アドレスチェックコマ
ンドを生成するコマンド生成手段(503)と、受信し
た装置アドレスコマンドが他装置のすべてを一巡してい
ないときに、この装置アドレスコマンドに自装置の装置
アドレスを付加するアドレス付加手段(509)と、受
信した装置アドレスコマンドが他装置のすべてを一巡し
ているときに、この装置アドレスコマンドに付加されて
いる装置アドレスと自装置の装置アドレスとを比較判定
する判定手段(507)とを備えたごとを特徴とする。
Means for Solving Problem c] The present invention generates a device address check command in a data transmission device inserted on a path connecting each of a plurality of processors and a data transmission path and assigned a device address. an address adding means (509) for adding the device address of the own device to the received device address command when the received device address command has not circulated through all the other devices; The apparatus is characterized by comprising a determining means (507) for comparing and determining the apparatus address added to the apparatus address command and the apparatus address of the own apparatus when the apparatus address command is making a round of all other apparatuses. shall be.

〔作用〕[Effect]

試験時、コマンド生成手段から装置アドレスチェックコ
マンドが伝送路に送出される。これを受信した他装置で
は、この装置に付された装置アドレスを装置アドレスチ
ェックコマンドに付加して伝送路に送出する。すべての
他装置を一巡して受信された装置アドレスチェックコマ
ンドに付加されている他装置の装置コマンドと自装置の
装置コマンドとが比較される。一致する装置コマンドが
あさば、例えば、自装置の装置コマンドを変更すること
により通信の混乱を防止することができる。
During testing, a device address check command is sent to the transmission path from the command generation means. The other device that receives this adds the device address assigned to this device to the device address check command and sends it to the transmission path. The device command of the other device added to the device address check command received after visiting all other devices is compared with the device command of the own device. If the device commands match, for example, by changing the device command of the own device, communication confusion can be prevented.

〔実施例〕〔Example〕

以下、本発明実施例装置を図面に基づいて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be explained below based on the drawings.

第2図は本発明実施例装置が用いられているデータ伝送
系統の構成を示すブロック構成図で、この図の符号1〜
4はそれぞれプロセッサを、符号5〜8はそれぞれデー
タ伝送装置を、符号9はデータ伝送路を示す。
FIG. 2 is a block configuration diagram showing the configuration of a data transmission system in which the device according to the embodiment of the present invention is used.
Reference numeral 4 indicates a processor, reference numerals 5 to 8 indicate data transmission devices, and reference numeral 9 indicates a data transmission path.

まず、本発明実施例装置の構成を第1図に基づいて説明
する。この実施例装置5は、プロセッサ1からきデータ
が出力される信号線51と、信号線51上のデータを入
力するためのプロセッサ受信回路501 と、プロセッ
サ受信回路501がら入力した入力データが装置アドレ
スチェックコマンド生成指示か否かを解析するコマンド
解析回路502と、コマンド解析回路502のコマンド
解析が装置アドレスチェックコマンド生成指示であれば
装置アドレスチェックコマンドの生成を指示する信号線
53と、装置アドレスチェックコマンドの生成を指示す
る信号線53の状態が11」であれば装置アドレスチェ
ックコマンドを生成する装置アドレスチェックコマンド
生成回路503と、コマンド解析回路502、装置アド
レスチェックコマンド生成回路503、または装置アド
レス付加回路509の出力データをデータ伝送路9へ送
信するデータ伝送路送信回路504と、データ伝送路送
信回路504の出力データを乗せる信号線91と、デー
タ伝送路9からの入力データを乗せる信号線92と、信
号線92のデータを入力するデータ伝送路受信回路50
5と、データ伝送路受信回路505からの入力データが
装置アドレスチェックコマンドか否かを解析するコマン
ド解析回路506と、コマンド解析結果が装置アドレス
チェックコマンドでかつ自回路が装置アドレスヂエック
コマンド応答待ちでなければコマンド解析回路506の
出力を乗せる信号線54と、コマンド解析結果が装置ア
ドレスチェックコマンドでかつ自回路が装置アドレスチ
ェックコマンド応答待ちであればコマンド解析回路50
6の出力を乗せる信号線55と、コマン解析結果が装置
アドレスヂエックコマンド以外のときにコマンド解析回
路506の出力を乗せる信号線56と、信号綿54から
の入力データに自局アドレスを付加してデータ伝送路送
信回路504ヘデータを送出する装置アドレス付加回路
509と、信号線55および自局装置アドレス510か
らの入力データの装置アドレス情報中に自局装置アドレ
スと一致するものがあるか否かを判定する装置アドレス
情報判定回路507と、信号線56または装置アドレス
情報判定回路507から入力したデータをプロセッサ1
に送出するプロセッサ送信回路508と、プロセッサ送
信回路508の出力データを乗せる信号線52とを備え
る。
First, the configuration of an apparatus according to an embodiment of the present invention will be explained based on FIG. This embodiment device 5 has a signal line 51 for outputting data from the processor 1, a processor receiving circuit 501 for inputting data on the signal line 51, and a device address check for input data input from the processor receiving circuit 501. A command analysis circuit 502 that analyzes whether or not it is a command generation instruction; a signal line 53 that instructs generation of a device address check command if the command analysis of the command analysis circuit 502 indicates an instruction to generate a device address check command; and a signal line 53 that instructs generation of a device address check command; A device address check command generation circuit 503 that generates a device address check command if the state of the signal line 53 instructing the generation of is 11'', a command analysis circuit 502, a device address check command generation circuit 503, or a device address addition circuit. 509 to the data transmission path 9, a signal line 91 for carrying the output data of the data transmission line transmission circuit 504, and a signal line 92 for carrying the input data from the data transmission line 9. , a data transmission path receiving circuit 50 that inputs data on the signal line 92.
5, a command analysis circuit 506 that analyzes whether the input data from the data transmission line receiving circuit 505 is a device address check command, and a command analysis circuit 506 that analyzes whether the input data from the data transmission line receiving circuit 505 is a device address check command, and a command analysis circuit 506 that analyzes whether the command analysis result is a device address check command and its own circuit waits for a response to the device address check command. Otherwise, the signal line 54 carries the output of the command analysis circuit 506, and the command analysis circuit 50 if the command analysis result is a device address check command and the own circuit is waiting for a response to the device address check command.
6, a signal line 56 that carries the output of the command analysis circuit 506 when the command analysis result is other than a device address check command, and a signal line 56 that carries the output of the command analysis circuit 506, and the own station address is added to the input data from the signal line 54. The device address adding circuit 509 that sends data to the data transmission path transmitting circuit 504, the signal line 55, and the device address information of the input data from the local device address 510 match the local device address. A device address information determination circuit 507 that determines the
The processor transmission circuit 508 is provided with a processor transmission circuit 508 for transmitting data to the processor transmission circuit 508, and a signal line 52 for carrying output data of the processor transmission circuit 508.

次に、本発明実施例装置の動作を第1図に基づいて説明
する。
Next, the operation of the apparatus according to the embodiment of the present invention will be explained based on FIG.

はじめに、装置アドレスチェックコマンド発信動作を説
明する。プロセッサ1からの装置アドレスチェックコマ
ンド指示は信号線51を介してプロセッサ受信回路50
1に受信され、プロセッサ受信回路501からこの指令
がコマンド解析回路502へ出力され、コマンド解析回
路502で入力データが装置アドレスチェックコマンド
指示であることが解析されると、信号線53が「1」の
状態にされ、一方、装置アドレスチェックコマンド指示
でなければ信号線53は「0」の状態にされる。装置ア
ドレスチェックコマンド生成回路503で信号線53が
「1」であれば第3図に示す信月デーク形式の装置アド
レスチェックコマンドのデータが生成される。装置アド
レスチェックコマンド生成回路503からデータ伝送路
送信回路504へ装置アドレスチヱソクコマンドデータ
の送信要求が出力されると、データ伝送路送信回路50
4から装置アドレスチェックコマンドが信号線91に送
出される。このような一連の発信動作が終了し、他局か
らの応答待ち状態になる。
First, the operation of issuing a device address check command will be explained. The device address check command instruction from the processor 1 is sent to the processor receiving circuit 50 via the signal line 51.
1, this command is output from the processor reception circuit 501 to the command analysis circuit 502, and when the command analysis circuit 502 analyzes that the input data is a device address check command instruction, the signal line 53 becomes "1". On the other hand, if the device address check command is not specified, the signal line 53 is set to "0". If the signal line 53 is "1" in the device address check command generation circuit 503, data of the device address check command in Shingetsu Dake format shown in FIG. 3 is generated. When a request to send device address check command data is output from the device address check command generation circuit 503 to the data transmission path transmission circuit 504, the data transmission path transmission circuit 50
4, a device address check command is sent to the signal line 91. After this series of transmission operations is completed, the station enters a state of waiting for a response from another station.

ひきつづき、受信動作を説明する。データ伝送路9から
の入力データが信号線92を介してデータ伝送路受信回
路505で受信されると、データ伝送路受信回路505
からこの入力データがコマンド解析回路506に送出さ
れる。コマンド解析回路506でこの入力データのコマ
ンドが装置アドレスチェックコマンドでかつ装置アドレ
スチェックコマンドの応答待ちであることが解析されれ
ば、信号線55上の信号が「1」状態にされる。装置ア
ドレスチェックコマンドの応答待ちでなければ、信号線
54上の信号が「1」状態にされる。また、入力データ
コマンドが装置アドレスチェックコマンドでなければ、
プロセッサ送信回路508に出力される。
Next, the reception operation will be explained. When input data from the data transmission line 9 is received by the data transmission line receiving circuit 505 via the signal line 92, the data transmission line receiving circuit 505
This input data is sent to the command analysis circuit 506. If the command analysis circuit 506 analyzes that the command of this input data is a device address check command and that a response to the device address check command is awaited, the signal on the signal line 55 is set to the "1" state. If the device is not waiting for a response to the device address check command, the signal on the signal line 54 is set to the "1" state. Also, if the input data command is not a device address check command,
The signal is output to processor transmission circuit 508.

信号線54がrlJであれば、装置アドレス付加回路5
09から入力データの装置アドレス情報部に自局装置ア
ドレス510の出力が付加されたデータがデータ伝送路
送信回路504へ出力される。この人力したデータがデ
ータ伝送路送信回路504から信号線91に送出される
。一方、装置アドレス情報判定回路507では、信号線
55が「1」状態であれば、入力データの装置アドレス
情報部中に自局装置アドレス510 と同一の装置アド
レスがあるか否かが比較され、一致した装置アドレスが
不正アドレスコードに置換されるとともに、判定結果が
入力データのステータス情報部に反映される。判定が終
了した入力データはプロセッサ送信回路508へ出力さ
れ、プロセッサ送信回路508から入力データが信号線
52へ送出される。この一連の動作で受信が終了する。
If the signal line 54 is rlJ, the device address addition circuit 5
From 09, data in which the output of the local device address 510 is added to the device address information part of the input data is output to the data transmission path transmitting circuit 504. This manually generated data is sent from the data transmission line transmission circuit 504 to the signal line 91. On the other hand, in the device address information determination circuit 507, if the signal line 55 is in the "1" state, it is compared to see if there is a device address that is the same as the local device address 510 in the device address information section of the input data. The matched device address is replaced with an invalid address code, and the determination result is reflected in the status information section of the input data. The input data for which the determination has been completed is output to the processor transmission circuit 508, and the input data is sent from the processor transmission circuit 508 to the signal line 52. Reception is completed with this series of operations.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、データ伝送装置で自局装
置アドレスと同し装置アドレスを有するデータ伝送装置
の有無が確認できるので、各データ伝送装置はデータ伝
送路−にで1111−の装置アドレスを持つことが保証
され、したがって宛先の異なる通信を防止することがで
きる効果がある。
As explained above, the present invention allows a data transmission device to check whether there is a data transmission device having the same device address as its own device address. This has the effect of preventing communications with different destinations.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例装置の構成を示すブロック構成図
。 第2図は本発明実施例装置が用いられた複数プロセッサ
間ネットワークシステムの構成を示すブロック構成図。 第3図は本発明実施例装置が送受信動作に使用するデー
タの形式を示すフレーム構成図。 1〜4・・・プロセッサ、5〜8・・・データ伝送装置
、9・・・データ伝送路、51〜56.91.92・・
・信号線、501・・・プロセッサ受信回路、502.
506・・・コマンド解析回路、503・・・装置アド
レスヂエソクコマンド生成回路、504・・・データ伝
送路送信回路、505・・・データ伝送路受信回路、5
07・・・装置アドレス情報判定回路、508・・・プ
ロセソザ送信回路、509・・・装置アドレス付加回路
、510・・・自局装置アドレス。
FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of a network system between multiple processors in which a device according to an embodiment of the present invention is used. FIG. 3 is a frame configuration diagram showing the format of data used for transmission and reception operations by the device according to the embodiment of the present invention. 1-4... Processor, 5-8... Data transmission device, 9... Data transmission path, 51-56.91.92...
- Signal line, 501... Processor receiving circuit, 502.
506... Command analysis circuit, 503... Device address processing command generation circuit, 504... Data transmission line transmitting circuit, 505... Data transmission line receiving circuit, 5
07... Device address information determination circuit, 508... Processor transmission circuit, 509... Device address addition circuit, 510... Local device address.

Claims (1)

【特許請求の範囲】 1)複数のプロセッサのそれぞれとデータ伝送路とを接
続する経路上に挿入され、装置アドレスが付されたデー
タ伝送装置において、 装置アドレスチェックコマンドを生成するコマンド生成
手段(503)と、 受信した装置アドレスコマンドが他装置のすべてを一巡
していないときに、この装置アドレスコマンドに自装置
の装置アドレスを付加するアドレス付加手段(509)
と、 受信した装置アドレスコマンドが他装置のすべてを一巡
しているときに、この装置アドレスコマンドに付加され
ている装置アドレスと自装置の装置アドレスとを比較判
定する判定手段(507)とを備えたことを特徴とする
データ伝送装置。
[Scope of Claims] 1) In a data transmission device inserted on a path connecting each of a plurality of processors and a data transmission path and assigned a device address, a command generation means (503) for generating a device address check command. ), and address addition means (509) for adding the device address of the own device to the received device address command when the device address command has not circulated through all other devices.
and determining means (507) for comparing and determining the device address added to the received device address command with the device address of the own device while the received device address command is making a round of all other devices. A data transmission device characterized by:
JP60236870A 1985-10-22 1985-10-22 Data transmission equipment Pending JPS6297444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60236870A JPS6297444A (en) 1985-10-22 1985-10-22 Data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60236870A JPS6297444A (en) 1985-10-22 1985-10-22 Data transmission equipment

Publications (1)

Publication Number Publication Date
JPS6297444A true JPS6297444A (en) 1987-05-06

Family

ID=17007012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60236870A Pending JPS6297444A (en) 1985-10-22 1985-10-22 Data transmission equipment

Country Status (1)

Country Link
JP (1) JPS6297444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01171343A (en) * 1987-12-25 1989-07-06 Shikoku Nippon Denki Software Kk Connection order check system in loop type network system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01171343A (en) * 1987-12-25 1989-07-06 Shikoku Nippon Denki Software Kk Connection order check system in loop type network system

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