JPH05235786A - Transmission level control circuit - Google Patents

Transmission level control circuit

Info

Publication number
JPH05235786A
JPH05235786A JP3669292A JP3669292A JPH05235786A JP H05235786 A JPH05235786 A JP H05235786A JP 3669292 A JP3669292 A JP 3669292A JP 3669292 A JP3669292 A JP 3669292A JP H05235786 A JPH05235786 A JP H05235786A
Authority
JP
Japan
Prior art keywords
level
value
transmission level
converter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3669292A
Other languages
Japanese (ja)
Other versions
JP2745937B2 (en
Inventor
Hideo Omura
英雄 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3669292A priority Critical patent/JP2745937B2/en
Publication of JPH05235786A publication Critical patent/JPH05235786A/en
Application granted granted Critical
Publication of JP2745937B2 publication Critical patent/JP2745937B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To automatically correct an error due to a temperature characteristic or an error or the like due to dispersion in components by automatically correcting a control variable so that an output of a transmission level detector reaches an expected value. CONSTITUTION:An output of a variable resistor 8 used to generate a very small address level is given to an A/D converter 7, in which the level is A/D- converted and an output of the A/D converter 7 is inputted to a sub CPU 1 through a bug. A transmission level detector 6 detects a current transmission level and an output of the transmission level detector 6 is inputted to an A/D converter 5, in which the signal is A/D-converted and the output of the A/D converter 5 is inputted to the sub CPU 1 through a bus. The sub CPU 1 subtracts the current transmission level detection value being an output of the A/D converter 5 from the sum of the a digital level corresponding to a level of a transmission analog signal from a main CPU 2 and the transmission level fine-adjusted value being an output of the A/D converter 7 and adds the result to the current input of a D/A converter 3 as a new input of the D/A converter 3. A transmission level controller 4 changes the transmission level based on the output of the D/A converter 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は移動無線通信装置その他
アナログ信号送信装置に利用する。特に、送信レベル制
御回路での温度特性等による誤差を自動的に補正する手
段に関する。
BACKGROUND OF THE INVENTION The present invention is used in mobile radio communication devices and other analog signal transmitting devices. In particular, it relates to a means for automatically correcting an error due to temperature characteristics or the like in the transmission level control circuit.

【0002】[0002]

【従来の技術】従来の送信レベル制御回路は、温度特性
による誤差や素子のばらつきによる誤差等の補正は行っ
ていなかった。
2. Description of the Related Art A conventional transmission level control circuit does not correct an error due to a temperature characteristic or an element variation.

【0003】[0003]

【発明が解決しようとする課題】このような従来の送信
レベル制御回路は、温度特性による誤差や素子のばらつ
きによる誤差等で送信レベルに誤差が生ずる欠点があっ
た。
The conventional transmission level control circuit as described above has a drawback that an error occurs in the transmission level due to an error due to a temperature characteristic, an error due to element variation, and the like.

【0004】本発明は、このような欠点を除去するもの
で、温度特性による誤差、素子のばらつきによる誤差な
どの補正を自動的に行う手段をもつ送信レベル制御回路
を提供することを目的とする。
The present invention eliminates such drawbacks, and an object of the present invention is to provide a transmission level control circuit having means for automatically correcting an error due to temperature characteristics, an error due to element variation, and the like. .

【0005】[0005]

【課題を解決するための手段】本発明は、送信中のアナ
ログ信号のレベル値を与えられたアナログ信号に応じて
調整する送信レベル制御器に接続された送信レベル制御
回路において、送信するアナログ信号のレベル値に相当
のディジタルレベル値を設定するレベル値設定手段と、
送信中のアナログ信号のレベルの現在値を検出する送信
レベル検出器と、この送信レベル検出器で検出されたア
ナログ信号のレベル値をディジタルレベル値に変換する
第一変換手段と、微小なアナログレベル値を発生する調
整値発生手段と、この調整値発生手段で発生された微小
なアナログレベル値をディジタルレベル微調整値に変換
する第二変換手段と、与えられたディジタル信号をアナ
ログ信号に変換して上記送信レベル制御器に与える第三
変換手段と、上記レベル値設定手段で設定されたディジ
タルレベル値と上記第二変換手段で変換されたディジタ
ルレベル微調整値との和を演算し、この演算値と上記第
一変換手段で変換されたディジタルレベル値との差を演
算し、この演算値と上記第三変換手段で現時点で変換さ
れているディジタル信号との和を演算し、この演算値を
上記第三変換手段に新たなディジタル信号として与える
演算手段とを備えことを特徴とする。
SUMMARY OF THE INVENTION The present invention is a transmission level control circuit connected to a transmission level controller for adjusting the level value of an analog signal being transmitted according to a given analog signal. Level value setting means for setting a digital level value corresponding to the level value of
A transmission level detector that detects the current value of the level of the analog signal being transmitted, a first conversion means that converts the level value of the analog signal detected by this transmission level detector into a digital level value, and a minute analog level Adjusting value generating means for generating a value, second converting means for converting the minute analog level value generated by the adjusting value generating means into a digital level finely adjusting value, and a given digital signal for converting into an analog signal. Calculating the sum of the digital level value set by the level value setting means and the digital level fine adjustment value converted by the second converting means. The difference between the value and the digital level value converted by the first converting means is calculated, and the calculated value and the digital value currently converted by the third converting means. It calculates the sum of the signal, the calculated value, characterized in that a calculation means for providing a new digital signal to said third conversion means.

【0006】ここで、上記レベル値設定手段および上記
演算手段がCPUであっても良い。
Here, the level value setting means and the arithmetic means may be CPUs.

【0007】[0007]

【作用】送信レベル検出器の出力の値が期待する値にな
るように送信レベル制御器の制御量を自動的に補正し、
温度特性による誤差や素子のばらつきによる誤差等によ
る送信レベルの誤差を自動的に補正する。
[Operation] The control amount of the transmission level controller is automatically corrected so that the output value of the transmission level detector becomes the expected value,
Automatically corrects transmission level errors due to errors due to temperature characteristics and due to element variations.

【0008】[0008]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1はこの実施例の構成を示すブロック
構成図である。この実施例は、図1に示すように、送信
中のアナログ信号のレベル値を与えられたアナログ信号
に応じて調整する送信レベル制御器4を備え、さらに、
本発明の特徴とする手段として、送信するアナログ信号
のレベル値に相当のディジタルレベル値を設定するレベ
ル値設定手段であるメインCPU2と、送信中のアナロ
グ信号のレベルの現在値を検出する送信レベル検出器6
と、この送信レベル検出器6で検出されたアナログ信号
のレベル値をディジタルレベル値に変換する第一変換手
段であるAD変換器5と、微小なアナログレベル値を発
生する調整値発生手段である可変抵抗器8と、この調整
値発生手段で発生された微小なアナログレベル値をディ
ジタルレベル微調整値に変換する第二変換手段であるA
D変換器7と、与えられたディジタル信号をアナログ信
号に変換して送信レベル制御器4に与える第三変換手段
であるDA変換器3と、上記レベル値設定手段で設定さ
れたディジタルレベル値と上記第二変換手段で変換され
たディジタルレベル微調整値との和を演算し、この演算
値と上記第一変換手段で変換されたディジタルレベル値
との差を演算し、この演算値と上記第三変換手段で現時
点で変換されているディジタル信号との和を演算し、こ
の演算値を上記第三変換手段に新たなディジタル信号と
して与える演算手段であるサブCPU1とを備える。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. As shown in FIG. 1, this embodiment includes a transmission level controller 4 that adjusts the level value of the analog signal being transmitted according to a given analog signal, and further,
As a feature of the present invention, a main CPU 2 which is a level value setting means for setting a digital level value corresponding to the level value of the analog signal to be transmitted, and a transmission level for detecting the current value of the level of the analog signal being transmitted. Detector 6
An AD converter 5 which is a first converting means for converting the level value of the analog signal detected by the transmission level detector 6 into a digital level value, and an adjustment value generating means for generating a minute analog level value. The variable resistor 8 and the second converting means A for converting the minute analog level value generated by the adjusting value generating means into the digital level fine adjusting value.
A D converter 7, a DA converter 3 which is a third converting means for converting a given digital signal into an analog signal and giving it to the transmission level controller 4, and a digital level value set by the level value setting means. The sum of the digital level fine adjustment value converted by the second converting means is calculated, and the difference between the calculated value and the digital level value converted by the first converting means is calculated. The sub-CPU 1 is a computing means for computing the sum of the digital signal currently converted by the three converting means and giving the calculated value as a new digital signal to the third converting means.

【0009】次に、この実施例の動作を説明する。メイ
ンCPU2からサブCPU1に対して送信レベルが指定
される。可変抵抗器8はメインCPU2による送信レベ
ル値を微調整するものであり、可変抵抗器8の出力はA
D変換器7に入力されてAD変換され、AD変換器7の
出力はバスを通じてサブCPU1に入力される。送信レ
ベル検出器6は現在の送信レベル値を検出し、送信レベ
ル検出器6の出力はAD変換器5に入力されてAD変換
され、AD変換器5の出力はバスを通じてサブCPU1
に入力される。サブCPU1はメインCPU2による送
信レベル値とAD変換器7の出力である送信レベル微調
整の和とAD変換器5の出力である現在の送信レベル検
出値との差を現在のDA変換器3の入力に加えたものを
新たなDA変換器3の入力とする。送信レベル制御器4
はDA変換器3の出力により送信レベル値を変化させ
る。
Next, the operation of this embodiment will be described. The transmission level is designated from the main CPU 2 to the sub CPU 1. The variable resistor 8 is for finely adjusting the transmission level value by the main CPU 2, and the output of the variable resistor 8 is A
It is input to the D converter 7 and AD-converted, and the output of the AD converter 7 is input to the sub CPU 1 through the bus. The transmission level detector 6 detects the current transmission level value, the output of the transmission level detector 6 is input to the AD converter 5 and AD-converted, and the output of the AD converter 5 is output to the sub CPU 1 through the bus.
Entered in. The sub CPU 1 calculates the difference between the sum of the transmission level value by the main CPU 2 and the transmission level fine adjustment output from the AD converter 7 and the current transmission level detection value output from the AD converter 5 in the current DA converter 3. The input to the new DA converter 3 is added to the input. Transmission level controller 4
Changes the transmission level value according to the output of the DA converter 3.

【0010】[0010]

【発明の効果】本発明は、以上説明したように、AD変
換器5の出力である送信レベル検出値がメインCPU2
からの送信レベル指定値とAD変換器5の出力である送
信レベル微調整値の和と等しくなるように送信レベル制
御器4の制御量であるDA変換器3の入力を調整するこ
とができるので、温度特性による誤差・素子のばらつき
による誤差等による送信レベルの誤差を自動的に補正す
ることができる効果がある。
As described above, according to the present invention, the transmission level detection value output from the AD converter 5 is the main CPU 2
Since it is possible to adjust the input of the DA converter 3 which is the control amount of the transmission level controller 4 so as to be equal to the sum of the transmission level designation value from the above and the transmission level fine adjustment value which is the output of the AD converter 5. In addition, it is possible to automatically correct an error in the transmission level due to an error due to temperature characteristics, an error due to element variation, and the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の構成を示すブロック構成図。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 サブCPU 2 メインCPU 3 DA変換器 4 送信レベル制御器 5 AD変換器 6 送信レベル検出器 7 AD変換器 8 可変抵抗器 1 Sub CPU 2 Main CPU 3 DA Converter 4 Transmission Level Controller 5 AD Converter 6 Transmission Level Detector 7 AD Converter 8 Variable Resistor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 送信中のアナログ信号のレベル値を与え
られたアナログ信号に応じて調整する送信レベル制御器
に接続された送信レベル制御回路において、 送信するアナログ信号のレベル値に相当のディジタルレ
ベル値を設定するレベル値設定手段と、 送信中のアナログ信号のレベルの現在値を検出する送信
レベル検出器と、 この送信レベル検出器で検出されたアナログ信号のレベ
ル値をディジタルレベル値に変換する第一変換手段と、 微小なアナログレベル値を発生する調整値発生手段と、 この調整値発生手段で発生された微小なアナログレベル
値をディジタルレベル微調整値に変換する第二変換手段
と、 与えられたディジタル信号をアナログ信号に変換して上
記送信レベル制御器に与える第三変換手段と、 上記レベル値設定手段で設定されたディジタルレベル値
と上記第二変換手段で変換されたディジタルレベル微調
整値との和を演算し、この演算値と上記第一変換手段で
変換されたディジタルレベル値との差を演算し、この演
算値と上記第三変換手段で現時点で変換されているディ
ジタル信号との和を演算し、この演算値を上記第三変換
手段に新たなディジタル信号として与える演算手段とを
備えたことを特徴とする送信レベル制御回路。
1. A transmission level control circuit connected to a transmission level controller for adjusting the level value of an analog signal being transmitted according to a given analog signal, wherein a digital level corresponding to the level value of the analog signal to be transmitted. Level value setting means for setting a value, a transmission level detector for detecting the current value of the level of the analog signal being transmitted, and a level value of the analog signal detected by this transmission level detector is converted into a digital level value. First conversion means, adjustment value generation means for generating a minute analog level value, second conversion means for converting the minute analog level value generated by the adjustment value generation means into a digital level fine adjustment value, The conversion means converts the digital signal into an analog signal and gives it to the transmission level controller, and third level conversion means and the level value setting means. The sum of the digital level value thus converted and the digital level fine adjustment value converted by the second converting means, and the difference between the calculated value and the digital level value converted by the first converting means, And a calculating means for calculating the sum of the calculated value and the digital signal currently converted by the third converting means, and giving the calculated value to the third converting means as a new digital signal. And a transmission level control circuit.
【請求項2】 上記レベル値設定手段および上記演算手
段がCPUである請求項1記載の送信レベル制御回路。
2. The transmission level control circuit according to claim 1, wherein the level value setting means and the computing means are CPUs.
JP3669292A 1992-02-24 1992-02-24 Transmission level control circuit Expired - Fee Related JP2745937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3669292A JP2745937B2 (en) 1992-02-24 1992-02-24 Transmission level control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3669292A JP2745937B2 (en) 1992-02-24 1992-02-24 Transmission level control circuit

Publications (2)

Publication Number Publication Date
JPH05235786A true JPH05235786A (en) 1993-09-10
JP2745937B2 JP2745937B2 (en) 1998-04-28

Family

ID=12476862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3669292A Expired - Fee Related JP2745937B2 (en) 1992-02-24 1992-02-24 Transmission level control circuit

Country Status (1)

Country Link
JP (1) JP2745937B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010514282A (en) * 2006-12-21 2010-04-30 イセラ・カナダ・ユーエルシー Closed-loop digital power control for wireless transmitters

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010514282A (en) * 2006-12-21 2010-04-30 イセラ・カナダ・ユーエルシー Closed-loop digital power control for wireless transmitters
US8509290B2 (en) 2006-12-21 2013-08-13 Icera Canada ULC Closed-loop digital power control for a wireless transmitter

Also Published As

Publication number Publication date
JP2745937B2 (en) 1998-04-28

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