JPH05235773A - Delta sigma d/a converter - Google Patents

Abstract

PURPOSE:To revise the conversion characteristic of the delta sigma D/A converter with a command from the outside of the converter. CONSTITUTION:Output data of a quantization circuit 4 are subtracted from input data of an adder circuit 5 and the result is inputted to a delay circuit 6. An output of the delay circuit 6 is inputted to a delay circuit 7 and a multiplier circuit 8 and inputted to an adder circuit 9 from the delay circuit 7 and subtracted from digital data DG1 and added to an output of the adder circuit 9 while being inputted to an adder circuit 10 from the multiplier circuit 8. Furthermore, the output of the delay circuit 6 is inputted to an integral circuit 20 and integration data are inputted selectively to an adder circuit 23 and added to the output of the adder circuit 10. When the integration data are added by the addition of the adder circuit 23, a ternary noise shaping group is obtained and when '0' data are added, a secondary noise shaping group is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma type D / A converter which realizes high conversion accuracy by oversampling and which is suitable for use in audio equipment and the like.

[0002]

2. Description of the Related Art In a digital audio device such as a compact disc player, analog audio is sampled at a predetermined frequency and recorded as digital data of an appropriate number of bits. During reproduction, digital data read from a recording medium such as a compact disc is D /
It is restored to an analog signal by the A converter and reproduced as an audio signal through an amplifier and a speaker. At the time of reproducing the digital data, it is desired to minimize the conversion error of the D / A conversion to suppress the distortion of the reproduced signal, and various D / A conversion methods capable of obtaining a high conversion accuracy that can cope with this are desired. It is considered.

FIG. 3 is a block diagram showing an outline of a delta-sigma type D / A converter. The bit compression circuit 1 receives, for example, 16-bit digital data DG1 and converts the digital data DG1 into 3-bit digital data D.
Convert to G2 and output. In the conversion of data in the bit compression circuit 1, the digital data DG1 is oversampled at a frequency (48f _S ) that is 48 times the sampling frequency f _S , requantized in 7 steps of ± 3, and the 3-bit digital data DG2 is generated. Is configured to obtain. At this time, the quantization noise, that is, the error of the digital data DG2 with respect to the digital data DG1 is sequentially fed back at each conversion step, and the digital data D on the input side is fed back.
It is biased toward the high frequency region by a so-called noise shaping group that is added to G1. Therefore, the quantization noise in the low frequency region is greatly reduced, and most of the quantization noise is ignored by passing the low pass filter.

When the input digital data DG3 is 3 bits, the pulse width modulation circuit 2 sets 8 clocks in one data conversion period, and "8" is set in the clock period corresponding to the digital data DG2 in this 8 clock period. It is configured to output a "1" level signal and a "0" level signal during the remaining clock period. As a result, 1-bit digital data DG3 that repeats signals of "1" and "0" levels corresponding to the digital data DG2 is obtained. Then, this digital data DG3 is passed through an analog low-pass filter 3 composed of an RC circuit or the like, so that high-frequency components are removed and output as an analog signal AN to a circuit in the next stage.

FIG. 4 is a block diagram showing the configuration of the bit compression circuit 1 which employs a secondary noise shaping group. The quantizing circuit 4 uses the 16-bit digital data D
The signal level indicated by G1 is evaluated in 7 steps of ± 3, and 3-bit digital data DG2 corresponding to them is output. The data on the input side and the data on the output side of the quantization circuit 4 are input to the addition circuit 5, respectively, and the quantization circuit 4
The data output from the quantization circuit 4 is subtracted from the data input to the input terminal to calculate the data representing the quantization noise. The data representing the quantization noise is supplied to the delay circuit 6, delayed by one sampling period, and input to the second delay circuit 7 and the multiplication circuit 8. Then, the output of the delay circuit 7 is input to the adding circuit 9 and the digital data D
The output of the multiplication circuit 8 which is subtracted from G1 and whose multiplier is set to 2 is input to the addition circuit 10 and added.
The output of the adder circuit 10 is input to the quantization circuit 4.

Assuming that the digital data DG1 and DG2 are X and Y, the outputs of the adder circuits 10 and 9 are A and B, and the quantization noise in the quantizer circuit 4 is N, the output of the adder circuit 5 is −. Since N, the following three formulas are satisfied: Y = A + N B-2N · Z ⁻¹ = A X + N · Z ⁻² = B. Therefore, if A and B are deleted from these equations, the output Y for the input X becomes Y = X + N (1-Z ^-1 ) ² so that a secondary noise shaping operation is shown.

On the other hand, a bit compression circuit which adopts a third-order noise shaping group, as shown in FIG.
A delay circuit 11, a multiplication circuit 12, and an addition circuit 13 are added to the input side of the bit compression circuit that forms the secondary noise shaping group. That is, the output of the delay circuit 7 is input to the delay circuit 11 and the multiplication circuit 12, and the delay circuit 11
Is input to the adder circuit 13 to input digital data DG1.
And the output of the multiplication circuit 12 is input to the addition circuit 9 and subtracted from the output of the addition circuit 13. The multipliers of the multiplication circuits 8 and 12 are both set to 3.

Assuming that the output of the adder circuit 13 is C, Y = A + N B-3N.Z ^-1 = A C + 3N.Z ^-2 = B X-N.Z as in the case of FIG. ^-4 = 4 = ^-3 holds. By eliminating A, B, and C from these equations, Y = X + N · (1−Z ⁻¹ ) ³ is obtained, so that a third-order noise shaping operation is shown.

By the way, the characteristic of the nth-order noise shaping pin group represented by Y = X + N (1-Z ^-1 ) ⁿ is that since | Z ^-1 | is usually smaller than 1, the order of noise shaping is high. The noise component can be made smaller as this is done. However, in a high-order noise shaping group, the bias of noise components in the high-frequency region increases, so the low-pass filter 3 that removes noise in the high-frequency band is used.
Steep characteristics are required. Therefore, the order of the noise shaping group is set high for the purpose of suppressing the noise in the low frequency band, and conversely set low for the purpose of suppressing the noise in the high frequency band. ..

[0010]

In the delta-sigma type D / A converter in which the order of the noise shaping pin group is set at the time of circuit design, its conversion characteristic is fixed and its range of use is limited. Therefore, it lacks versatility,
It has a problem of high cost. Therefore, an object of the present invention is to change the conversion characteristic of a delta-sigma type D / A converter so that the order of the noise shaping group can be variably set.

[0011]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of first digital data of a plurality of bits input at a constant cycle are input. A quantizing circuit for sampling at a cycle shorter than the input cycle of 1 digital data and converting to second digital data in which the number of bits is reduced; and at the time of conversion from the first digital data to the second digital data. The generated quantization noise is delayed for each conversion in sampling period units, fed back to the input side, and the feedback data is sequentially added to the input side data. The n-th order noise shaping pin group and data conversion are performed separately from this noise shaping pin group. Time-quantized noise is fed back to the input side, and an integral-type auxiliary loop that adds the feedback data sequentially in the sampling period cycle and the above-mentioned quantization time Among the data conversion period, the second
A pulse width modulation circuit that outputs a signal of "1" level during a period specified by the digital data and a signal of a "0" level during the remaining period, and selectively outputs the data from the auxiliary loop. Is added to the signal on the input side of the quantization circuit to form an (n + 1) th order noise shaping pin group.

[0012]

According to the present invention, an auxiliary loop is added to an nth-order noise shaping group to make it an (n + 1) th order, and this auxiliary loop is selectively selected in accordance with a mode setting signal or the like given from outside the circuit. By operating it, the order of the noise shaping group can be changed without changing the circuit configuration. As a result, the conversion characteristic of the delta-sigma type D / A converter can be switched by an external instruction.

[0013]

1 is a circuit diagram of a main part of a delta-sigma type D / A converter of the present invention, showing a bit compression circuit adopting a (2 + 1) th order noise shaping pin group. In this figure, the adder circuits 5, 9 and 10, the delay circuits 6 and 7, and the multiplier circuit 8 are the same as those in FIG. 4, and are obtained by subtracting the output side data from the input side data of the quantization circuit 4. The data is input to the delay circuit 6, the output of the delay circuit 6 is subtracted from the digital data DG1 through the delay circuit 7, and the output of the addition circuit 9 is added through the multiplication circuit 8 to obtain 2
The following noise shaping groups are configured.

The feature of the present invention resides in that the delay circuit 6
There is provided an auxiliary loop for integrating the output of the above and feeding back to the input side of the quantizing circuit 4, and the data fed back from this auxiliary loop is selectively added to the input of the quantizing circuit 4. That is, the auxiliary loop is configured by the integrating circuit 20 including the adding circuit 21 and the delay circuit 22, and the output of the integrating circuit 20 is input to the adding circuit 23 provided on the input side of the quantizing circuit 4. Then, the integrating circuit 2
Either return data from 0 or "0" data is
The addition circuit 23 adds the output to the output of the addition circuit 10. The selection of the input data in the adder circuit 23 is easily realized by providing an input switching gate on the input side of the adder circuit, and the control signal for controlling the gate is for mode setting supplied from outside the circuit. Signal is used.

Assuming that the digital data DG1 and DG2 are X and Y, the outputs of the adder circuits 10 and 9 are A and B, and the output of the adder circuit 5 is K, K = A−Y (1) ) A = B + 2K · Z ⁻¹ ··· (2) B = X−K · Z ⁻¹ ··· (3) Formula 3 holds. Therefore, if A and B are deleted from the equations (2) and (3), the output Y with respect to the input X becomes Y = X−K · (1−Z ⁻¹ ) ² ··· (4). If the quantization noise in the quantization circuit 4 is N and the output of the integration circuit 20 is α, then Y = A + N + α (5) At this time, α = 0 (when the adding circuit 23 is “0”)
(When data is added), K = −N from the equations (1) and (5), and thus the equation (4) becomes Y = X + N · (1−Z ⁻¹ ) ² . On the other hand, if α ≠ 0 (when the adding circuit 23 adds the feedback data), the transfer function of the integrating circuit 23 is (1
Since −Z ⁻¹ ) ⁻¹ , α = K · Z ⁻¹ · (1−
Z ⁻¹ ) ⁻¹ , and from the formulas (1) and (5), K = −N
Since it becomes (1-Z ^-1 ), the formula (4) becomes Y = X + N · (1-Z ^-1 ) ³ .

Therefore, when the feedback data of the integrating circuit 20 is added to the output of the adding circuit 10 in the adding circuit 23 and is input to the quantizing circuit 4, a third-order noise shaping group is realized and "0" data is added. And input to the quantization circuit 4, a secondary noise shaping group is realized. As a result, the degree of the noise shaping group is changed according to the selection of the operation of the adder circuit 23.

FIG. 2 is a circuit diagram showing another embodiment, which is shown in FIG.
Similarly to, a bit compression circuit adopting a (2 + 1) th order noise shaping group is shown. The quantization circuit 30 is shown in FIG.
In the same manner as in the above case, the signal level indicated by the 16-bit digital data DG1 is evaluated in 7 steps of ± 3 to compress it into the 3-bit digital data DG2. On the input side of the quantizing circuit 30, three adder circuits 31 to 33 and integrating circuits 34 to 36 are alternately connected in series so as to correspond to a third-order noise shaping group. The signal on the output side of the quantization circuit 30 is input to the delay circuit 37, delayed by one sampling period, and added to each of the addition circuits 31 to 31.
Input to 3. As a result, the adder circuit 31 subtracts the output of the delay circuit 37 from the digital data DG1 and inputs it to the integrating circuit 34. Similarly, each adder circuit 32,
In 33, the delay circuit 3
The outputs of 7 are subtracted from each other, and the integration circuit 35 of the next stage,
36 is input. Then, the output of the integration circuit 36 is finally input to the quantization circuit 30.

Here, the digital data DG1 and DG2 are X and Y, and the outputs of the integrating circuits 36, 35 and 34 are A, B and C.
And the quantization noise in the quantum circuit 30 is N, Y = A + N ... (6) A = (BY−Z ⁻¹ ) · (1−Z ⁻¹ ) ^−1. (7) B = (C−Y · Z ⁻¹ ) · (1−Z ⁻¹ ) ⁻¹ ···· (8) C = (X−Y · Z ⁻¹ ) · (1−Z ⁻¹ ) ^-1 ... Four expressions of (9) are established. Therefore, when A is deleted from the equations (6) and (7), it becomes Y = B + N. (1-Z- ¹ ) ... (10). Then, if B is deleted from the equations (10) and (8), then Y = C + N · (1-Z ⁻¹ ) ² ··· (11), and C is obtained from the equations (11) and (9). , The output Y with respect to the input X becomes Y = X + N (1-Z ^-1 ) ³ ... (12), so that the third-order noise shaping operation is shown.

At this time, when the output of the delay circuit 37 input to the adder circuit 31 is replaced with "0" data and the integrating operation of the integrating circuit 34 is stopped, the equation (9) becomes C = X, and therefore the equation (9) 12) is not established, and the output Y for the input X becomes Y = X + N. (1-Z- ¹ ) ² ... (13) at the stage of the expression (11), and the secondary noise shaping operation is performed. .. Therefore, by selecting the operation of the adder circuit 31 and the integrating circuit 34, the order of the noise shaping pin group is set to the second order or the third order
You can set it next.

In such a noise shaping pin group, an addition circuit and an integration circuit are further added, and the operation of the addition circuit and the integration circuit of each stage is selectively stopped, thereby making it possible to select the degree of the noise shaping pin group. Can be expanded.

[0021]

According to the present invention, since the order of the noise shaping group can be set by an instruction from the outside of the circuit, the conversion characteristic of the D / A converter can be switched without changing the circuit configuration. . Therefore, the versatility of the device is expanded, and the D / A converter having the same structure can be adopted in a wide range, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a delta-sigma type D / A converter of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional delta-sigma type D / A converter.

FIG. 4 is a circuit diagram of a bit compression circuit that employs a secondary noise shaping pin group.

FIG. 5 is a circuit diagram of a bit compression circuit that adopts a third-order noise shaping group.

[Explanation of symbols]

1 bit compression circuit 2 pulse width modulation circuit 3 low pass filter 4 quantization circuit 5, 9, 10, 13, 21, 23, 31, 32, 33
Adder circuit 6, 7, 11, 22, 37 Delay circuit 8, 12 Multiplier circuit 20, 34, 35, 36 Integrator circuit

Claims (2)

[Claims] 1. A plurality of bits of first digital data input at a constant cycle are sampled at a cycle shorter than the input cycle of the first digital data, and converted into second digital data having a reduced number of bits. The quantizing circuit and the quantizing noise generated at the time of conversion from the first digital data to the second digital data are delayed by sampling period for each conversion and fed back to the input side, and the feedback data is fed back to the input side. An n-th order noise shaper group that is sequentially added to the data, and quantization noise at the time of data conversion is fed back to the input side separately from this noise shaper group, and the integral type auxiliary that adds the feedback data sequentially in the sampling period cycle Outputs a "1" level signal during the period specified by the second digital data in the data conversion period of the loop and the quantization circuit. A pulse width modulation circuit that outputs a signal of "0" level during the remaining period, and selectively adds the data from the auxiliary loop to the signal on the input side of the quantization circuit (n + 1). A delta-sigma type D / A converter characterized by comprising the following noise shaping group. 2. The delta converter according to claim 1, further comprising control means for specifying whether or not the data from the auxiliary loop is added to the signal on the input side of the quantizing circuit.
Sigma type D / A converter.