JPH05235389A - Photovoltaic device - Google Patents

Photovoltaic device

Info

Publication number
JPH05235389A
JPH05235389A JP4070190A JP7019092A JPH05235389A JP H05235389 A JPH05235389 A JP H05235389A JP 4070190 A JP4070190 A JP 4070190A JP 7019092 A JP7019092 A JP 7019092A JP H05235389 A JPH05235389 A JP H05235389A
Authority
JP
Japan
Prior art keywords
electrode
photovoltaic device
back electrode
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4070190A
Other languages
Japanese (ja)
Other versions
JP2771921B2 (en
Inventor
Yukio Nakajima
行雄 中嶋
Hisao Haku
久雄 白玖
Katsunobu Sayama
勝信 佐山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4070190A priority Critical patent/JP2771921B2/en
Publication of JPH05235389A publication Critical patent/JPH05235389A/en
Application granted granted Critical
Publication of JP2771921B2 publication Critical patent/JP2771921B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PURPOSE:To provide a high-performance photovoltaic device where the surface of a rear electrode is formed into a rugged face having ruggedness of spherical shape and optimum size. CONSTITUTION:On a photovoltaic device having an insulating substrate 1, a rear electrode 2, amorphous semiconductors 3-5, and a transparent electrode 6, which are piled up on the substrate 1 one after another, the rear electrode 2 comprises a polycrystalline germanium layer formed by etching treatment after amorphous germanium doped with an n-type dopant is grown in a solid phase.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、光起電力装置に関す
る。
FIELD OF THE INVENTION This invention relates to photovoltaic devices.

【0002】[0002]

【従来の技術】一般に、光起電力装置としては、例えば
ガラス等の絶縁性基板と、該基板上に順に積層された裏
面電極と、n−i−pの順に積層した非晶質半導体と、
透明電極とを有するものが知られている。
2. Description of the Related Art Generally, a photovoltaic device includes, for example, an insulating substrate such as glass, a back electrode laminated on the substrate in order, and an amorphous semiconductor laminated in the order nip.
Those having a transparent electrode are known.

【0003】裏面電極としては光反射率の高い銀等が主
流を占めており、n−i−p又はp−i−nの順に積層
した非晶質半導体としては、アモルファスシリコン、ア
モルファスシリコンカーバイド、アモルファスシリコン
ゲルマニウム等が用いられる。また、透明電極として
は、酸化錫(SnO3 )、酸化インジウム(In2
5)、イットリウムタングステンオキサイド(IT
O)、酸化亜鉛(ZnO)等が用いられる。
As the back electrode, silver or the like having a high light reflectance occupies the mainstream, and as the amorphous semiconductors laminated in the order of n-ip or p-i-n, amorphous silicon, amorphous silicon carbide, Amorphous silicon germanium or the like is used. Further, as the transparent electrode, tin oxide (SnO 3 ) and indium oxide (In 2
O 5 ), yttrium tungsten oxide (IT
O), zinc oxide (ZnO) and the like are used.

【0004】この従来の光起電力装置においては、変換
効率を高めるため、裏面電極を例えば、蒸着、スパッタ
リング等によって形成することにより、裏面電極の表面
を微細な凹凸を有する凹凸面、いわゆるテクスチャー構
造に形成して裏面電極の表面で光を散乱させ、非晶質半
導体を透過する裏面電極の反射光の光路長を長くするよ
うにして、いわゆる光閉じ込め効果を利用している。
In this conventional photovoltaic device, in order to improve the conversion efficiency, the back electrode is formed by, for example, vapor deposition, sputtering, etc., so that the surface of the back electrode has an uneven surface having fine unevenness, a so-called texture structure. In order to utilize the so-called light confinement effect, light is scattered on the surface of the back surface electrode and the optical path length of the reflected light of the back surface electrode that transmits the amorphous semiconductor is lengthened.

【0005】[0005]

【発明が解決しようとする課題】この裏面電極の凹凸の
大きさが小さすぎる場合には、裏面電極の表面での散乱
光が少なくなり、光閉じ込めの効果が低下し過ぎるので
好ましくない。逆に裏面電極の大きさが大きすぎる場合
には、裏面電極の全反射率が低くなり過ぎ、かえって出
力が低下するので好ましくない。
If the size of the unevenness of the back electrode is too small, the amount of scattered light on the surface of the back electrode is reduced, and the effect of light confinement becomes too low, which is not preferable. On the contrary, if the size of the back electrode is too large, the total reflectance of the back electrode becomes too low and the output is rather lowered, which is not preferable.

【0006】また、凹凸の形状としては、適度の全反射
率が得られるとともに、均等な散乱がえられる半球形が
最も好ましい。
Further, as the shape of the unevenness, a hemispherical shape is most preferable because an appropriate total reflectance can be obtained and uniform scattering can be obtained.

【0007】しかしながら、従来の裏面電極の形成方法
において、例えばスパッタリング温度等のパラメータを
制御することよって裏面電極の表面の凹凸の大きさを制
御したり、表面の凹凸の形状を半球形に形成したりする
ことは極めて困難である。本発明の目的は、裏面電極の
表面に最適の大きさの半球状の凹凸が形成された光起電
力装置を提供することを目的とするものである。
However, in the conventional method of forming the back electrode, the size of the unevenness on the surface of the back electrode is controlled by controlling the parameters such as the sputtering temperature, and the shape of the unevenness of the surface is formed in a hemispherical shape. It is extremely difficult to do so. It is an object of the present invention to provide a photovoltaic device in which hemispherical irregularities of optimal size are formed on the surface of a back electrode.

【0008】[0008]

【課題を解決するための手段】絶縁性基板と、該基板上
に積層された裏面電極と、n−i−p型の非晶質半導体
と、透明電極とを有する光起電力装置において、裏面電
極が、n型ドーパントが添加されたアモルファスゲルマ
ニウム(以下、a−Geと略記する。)を固相成長させ
た後、エッチング処理した多結晶ゲルマニウム層(以
下、poly−Ge層と略記する。)で形成されること
を特徴とする。
A photovoltaic device having an insulating substrate, a back electrode laminated on the substrate, an nip type amorphous semiconductor, and a transparent electrode. Polycrystalline germanium layer (hereinafter, abbreviated as poly-Ge layer), which is obtained by performing solid phase growth of amorphous germanium (hereinafter, abbreviated as a-Ge) to which an electrode is added with n-type dopant, is etched. It is characterized by being formed by.

【0009】[0009]

【作用】n型ドーパントが添加されたa−Geをアニー
リングして固相成長させると、poly−Ge層が得ら
れる。
When a-Ge doped with an n-type dopant is annealed and solid-phase grown, a poly-Ge layer is obtained.

【0010】このpoly−Ge層は酸性液を用いてエ
ッチング処理すると、表面に半球状の微細な凹凸が緻密
に形成される。
When this poly-Ge layer is subjected to an etching treatment using an acid solution, hemispherical fine irregularities are densely formed on the surface.

【0011】この凹凸の大きさは、a−Geを形成する
時の処理条件、例えば形成温度と、エッチング処理の条
件、例えば温度、時間等とに依存して任意の大きさに制
御できる。
The size of the irregularities can be controlled to any size depending on the processing conditions for forming a-Ge, for example, the forming temperature and the etching conditions, such as temperature and time.

【0012】[0012]

【実施例】本発明の実施例に係る光起電力装置を図面に
基づき具体的に説明すれば、以下の通りである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The photovoltaic device according to the embodiments of the present invention will be described below in detail with reference to the drawings.

【0013】図1の模式図に示すように、この光起電力
装置は、ガラス(商品名:コーニング7059)からな
る基板1、その上に順に積層された裏面電極2、n型非
晶質半導体層3、i型非晶質半導体層4、p型非晶質半
導体層5及び透明電極6及び集電用金属電極7を備えて
いる。
As shown in the schematic view of FIG. 1, this photovoltaic device comprises a substrate 1 made of glass (trade name: Corning 7059), a back electrode 2 laminated on the substrate 1, an n-type amorphous semiconductor. The layer 3, the i-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, the transparent electrode 6, and the metal electrode 7 for current collection are provided.

【0014】裏面電極2は、図2の模式図に示すよう
に、プラズマCVD法により、9倍程度の水素希釈条件
のもとで厚さ約5000Åのa−Ge層2oを形成した
後、アニーリングしてアモルファス層を多結晶化させる
いわゆる固相成長を行い、更にその後、酸性液中に浸漬
してエッチングすることにより形成される。
As shown in the schematic diagram of FIG. 2, the back surface electrode 2 is annealed after forming an a-Ge layer 2o having a thickness of about 5000Å by a plasma CVD method under a hydrogen dilution condition of about 9 times. Then, so-called solid phase growth for polycrystallizing the amorphous layer is performed, and thereafter, the film is formed by immersing in an acid solution and etching.

【0015】プラズマCVD法によるa−Ge層2oの
形成条件は表1の通りである。
Table 1 shows conditions for forming the a-Ge layer 2o by the plasma CVD method.

【0016】[0016]

【表1】 [Table 1]

【0017】基板温度は、実施例aでは290℃、実施
例bでは310℃、実施例cでは330℃、実施例dで
は350℃とした。
The substrate temperature was 290 ° C. in Example a, 310 ° C. in Example b, 330 ° C. in Example c, and 350 ° C. in Example d.

【0018】また、反応ガスにホスフィン(PH3 )を
添加するのは、固相成長を促進させる効果と、裏面電極
2の導電率を高めるためである。
The reason why phosphine (PH 3 ) is added to the reaction gas is to promote the solid phase growth and to increase the conductivity of the back electrode 2.

【0019】また、アニーリングの処理条件は表2に示
すように、アニール温度を350℃とし、アニール雰囲
気を窒素(N2 )雰囲気とし、アニール時間を2時間と
した。
As shown in Table 2, the annealing treatment conditions were an annealing temperature of 350 ° C., an annealing atmosphere of nitrogen (N 2 ) atmosphere, and an annealing time of 2 hours.

【0020】[0020]

【表2】 [Table 2]

【0021】エッチングは、0.15mol クロム酸カリ
水溶液(K2 Cr27 /H2 O)と49%フッ化水素
水溶液(HF/H2 O)との混合液を用いて行った。こ
のエッチングにより、poly−Ge層からなる裏面電
極2の表面に図3に示すような半球状の凹凸2aが緻密
に形成される。
The etching was performed using a mixed solution of 0.15 mol potassium chromate aqueous solution (K 2 Cr 2 O 7 / H 2 O) and 49% hydrogen fluoride aqueous solution (HF / H 2 O). By this etching, hemispherical unevenness 2a as shown in FIG. 3 is densely formed on the surface of the back electrode 2 made of the poly-Ge layer.

【0022】エッチングの処理時間は各実施例a〜dと
も0.5秒と1.0秒との2通りにした。
In each of Examples a to d, the etching treatment time was set to 0.5 seconds or 1.0 seconds.

【0023】図4の特性図に示すように、半球状凹凸2
aの直径はa−Geの形成温度を330℃にした時に最
大の約1000Åあるいは約3000Åとなり、それよ
りも低温ではa−Geの形成温度の増加に対応して増加
し、高温ではa−Geの形成温度の増加に対応して減少
する。また、エッチング処理時間が1秒以下では、エッ
チング処理時間の長い方が半球状凹凸2aの直径が大き
くなる。
As shown in the characteristic diagram of FIG. 4, hemispherical irregularities 2
The diameter of a reaches a maximum of about 1000Å or about 3000Å when the formation temperature of a-Ge is 330 ° C, and increases at a lower temperature corresponding to the increase of a-Ge formation temperature and at a higher temperature, a-Ge. Corresponding to an increase in the formation temperature of Further, when the etching treatment time is 1 second or less, the diameter of the hemispherical unevenness 2a becomes larger as the etching treatment time becomes longer.

【0024】なお、処理時間を1秒以上に増やしても全
体の厚膜が薄くなるだけで、その表面の凹凸2aの粒径
は1秒の場合とほとんど変わらなかった。
Even if the processing time was increased to 1 second or longer, the entire thick film was thinned, and the grain size of the irregularities 2a on the surface was almost the same as in the case of 1 second.

【0025】また、N型非晶質半導体層3、I型非晶質
半導体層4及びP型非晶質半導体層5は公知のプラズマ
CVD法により形成され、透明電極6はスパッタリング
法により形成され、集電用金属電極7は真空蒸着法によ
り形成される。
The N-type amorphous semiconductor layer 3, the I-type amorphous semiconductor layer 4, and the P-type amorphous semiconductor layer 5 are formed by a known plasma CVD method, and the transparent electrode 6 is formed by a sputtering method. The current collecting metal electrode 7 is formed by a vacuum deposition method.

【0026】上記の実施例a〜dについて太陽電池特性
を求めたところ、表3に示すような結果が得られた。
When the solar cell characteristics of the above Examples a to d were determined, the results shown in Table 3 were obtained.

【0027】[0027]

【表3】 [Table 3]

【0028】実施例aにおいてF.F.が著しく低いの
は、poly−Ge層の結晶性が不十分で裏面電極2と
して充分機能してないためである。
In Example a. F. Is extremely low because the crystallinity of the poly-Ge layer is insufficient and does not function sufficiently as the back electrode 2.

【0029】また、実施例a及び実施例bにおいて、I
scが低くなっているのは、凹凸が小さく、光閉じ込めが
十分にできていないためである。
In Examples a and b, I
The low sc is due to small irregularities and insufficient light confinement.

【0030】実施例dにおいては、a−Geの形成温度
が高いため、固相成長以前に微妙な結晶粒が生成された
おり、これが固相成長を阻害し、エッチング時に形成さ
れる凹凸の粒系径が小さくなる(図3参照)。このた
め、凹凸の粒径が最大となる実施例cに比べて実施例d
の出力電流が低くなっている。
In Example d, since the formation temperature of a-Ge was high, delicate crystal grains were generated before the solid phase growth, which hinders the solid phase growth and causes uneven grains formed during etching. The system diameter becomes smaller (see FIG. 3). Therefore, in comparison with Example c in which the grain size of the unevenness is maximum, Example d is used.
Output current is low.

【0031】実施例cは、poly−Ge層の結晶性が
十分であり、裏面電極として十分に機能している。ま
た、凹凸の大きさが最適になり、光閉じ込めが効果的に
行われているので、最大の出力が得られている。
In Example c, the crystallinity of the poly-Ge layer is sufficient and the poly-Ge layer functions sufficiently as the back electrode. Further, since the size of the unevenness is optimized and the light is confined effectively, the maximum output is obtained.

【0032】各実施例の電流の絶対値が低いのは、裏面
電極2の反射成分が利用できていなためである。
The absolute value of the current in each example is low because the reflection component of the back electrode 2 cannot be used.

【0033】本発明の他の実施例では、上記裏面電極2
が上記実施例cと同様にして形成されたpoly−Ge
層と、その上にスパッタリング法にて形成された厚さ約
500Åの銀(Ag)層とで構成される。この実施例の
その他の構成は、上記実施例cと同じである。
In another embodiment of the present invention, the back electrode 2
Of poly-Ge formed in the same manner as in Example c above.
It is composed of a layer and a silver (Ag) layer having a thickness of about 500Å formed thereon by a sputtering method. The other structure of this embodiment is the same as that of the above-mentioned embodiment c.

【0034】この実施例の太陽電池特性は表4のc/A
g欄に示す。
The solar cell characteristics of this example are shown in Table 4 as c / A.
It is shown in column g.

【0035】比較例として、ステンレス上に基板温度3
50℃で蒸着により形成された膜厚350Åの第1銀層
と、この後、基板温度を150℃に下げて蒸着により形
成された膜厚500Åの第2の銀層とで裏面電極が構成
され、その他の構成が実施例cと同じものを用いた。
As a comparative example, substrate temperature 3 on stainless steel
The back surface electrode is composed of a first silver layer having a film thickness of 350Å formed by vapor deposition at 50 ° C, and a second silver layer having a film thickness of 500Å formed by vapor deposition after lowering the substrate temperature to 150 ° C. The other configurations were the same as those in Example c.

【0036】この比較例の太陽電池特性は表4の凹凸A
g欄に示す。
The solar cell characteristics of this comparative example are as shown in Table 4
It is shown in column g.

【0037】[0037]

【表4】 [Table 4]

【0038】表4より、本発明の他の実施例にかかる光
起電力装置は、開放電圧Voc、出力電流Isc、F.
F.、効率Eff等何れの特性においても比較例よりも
高性能であることが分かる。
From Table 4, it can be seen that the photovoltaic device according to another embodiment of the present invention has an open circuit voltage Voc, an output current Isc, an F.V.
F. It can be seen that the performance is higher than that of the comparative example in any characteristics such as efficiency and efficiency Eff.

【0039】[0039]

【発明の効果】以上説明したように、本発明によれば、
裏面電極の表面を半球状の凹凸がある凹凸面に形成で
き、しかも、a−Geの形成条件、エッチング条件とう
を制御することによりその凹凸の大きさを精密に制御す
ることができる。
As described above, according to the present invention,
The surface of the back electrode can be formed into an uneven surface having hemispherical unevenness, and the size of the unevenness can be precisely controlled by controlling the a-Ge forming conditions and etching conditions.

【0040】これにより、最適の形状と大きさを有する
凹凸を形成して、従来よりも高性能の光起電力装置を得
ることができる。
As a result, it is possible to form the unevenness having the optimum shape and size and obtain a photovoltaic device having higher performance than the conventional one.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の模式図である。FIG. 1 is a schematic view of an embodiment of the present invention.

【図2】a−Geの形成状態を示す模式図である。FIG. 2 is a schematic view showing a formation state of a-Ge.

【図3】エッチング処理後のpoly−Ge層の状態を
示す模式図である。
FIG. 3 is a schematic view showing a state of a poly-Ge layer after etching treatment.

【図4】a−Ge形成温度と半球状凹凸の直径との関係
のエッチング処理時間依存性を示す特性図である。
FIG. 4 is a characteristic diagram showing the etching treatment time dependency of the relationship between the a-Ge formation temperature and the diameter of the hemispherical irregularities.

【符号の説明】[Explanation of symbols]

1 基板 2 裏面電極 3 n型非晶質半導体層 4 i型非晶質半導体層 5 p型非晶質半導体層 6 透明電極 1 substrate 2 back surface electrode 3 n-type amorphous semiconductor layer 4 i-type amorphous semiconductor layer 5 p-type amorphous semiconductor layer 6 transparent electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板と、該基板上に積層された裏
面電極と、n−i−pの順に積層した非晶質半導体と、
透明電極とを有する光起電力装置において、裏面電極
が、n型ドーパントが添加されたアモルファスゲルマニ
ウムを固相成長させた後、エッチング処理した多結晶ゲ
ルマニウム層を有することを特徴とする光起電力装置。
1. An insulating substrate, a back electrode laminated on the substrate, and an amorphous semiconductor laminated in the order of n-i-p,
A photovoltaic device having a transparent electrode, wherein the back electrode has a polycrystalline germanium layer which is etched after solid-phase growth of amorphous germanium doped with an n-type dopant. ..
JP4070190A 1992-02-19 1992-02-19 Photovoltaic device Expired - Fee Related JP2771921B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4070190A JP2771921B2 (en) 1992-02-19 1992-02-19 Photovoltaic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4070190A JP2771921B2 (en) 1992-02-19 1992-02-19 Photovoltaic device

Publications (2)

Publication Number Publication Date
JPH05235389A true JPH05235389A (en) 1993-09-10
JP2771921B2 JP2771921B2 (en) 1998-07-02

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Country Status (1)

Country Link
JP (1) JP2771921B2 (en)

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WO2011055600A1 (en) * 2009-11-05 2011-05-12 三菱電機株式会社 Photovoltaic device and method for manufacturing same
JP5143289B2 (en) * 2009-11-05 2013-02-13 三菱電機株式会社 Photovoltaic device and manufacturing method thereof

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