JP4152197B2 - Photovoltaic device - Google Patents

Photovoltaic device Download PDF

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JP4152197B2
JP4152197B2 JP2003007756A JP2003007756A JP4152197B2 JP 4152197 B2 JP4152197 B2 JP 4152197B2 JP 2003007756 A JP2003007756 A JP 2003007756A JP 2003007756 A JP2003007756 A JP 2003007756A JP 4152197 B2 JP4152197 B2 JP 4152197B2
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transparent conductive
film
conductive film
dopant
photovoltaic device
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JP2004221368A (en
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武志 山本
英治 丸山
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Description

【０００１】
【発明の属する技術分野】
この発明は、光起電力装置に関し、特に、結晶系半導体基板の表面側および裏面側に、それぞれ、透明導電膜が形成された光起電力装置に関する。
【０００２】
【従来の技術】
従来、表面側から光が入射される第１導電型の結晶系シリコン基板の表面上に、実質的に真性な非単結晶シリコン膜、第２導電型の非単結晶シリコン膜および透明導電膜が順次形成されたＨＩＴ（Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ ｗｉｔｈｉｎｔｒｉｎｓｉｃ ｔｈｉｎ‐ｌａｙｅｒ）構造の光起電力装置が知られている（たとえば、特許文献１参照）。
【０００３】
また、従来では、上記特許文献１に開示されたＨＩＴ構造の光起電力装置において、第１導電型の結晶系シリコン基板の裏面上に、実質的に真性な非単結晶シリコン膜、第１導電型の非単結晶シリコン膜および酸化物からなる透明導電膜が形成されたいわゆるＢＳＦ（Ｂａｃｋ Ｓｕｒｆａｃｅ Ｆｉｅｌｄ）構造を有する両面ＨＩＴ構造の光起電力装置も知られている。この従来の両面ＨＩＴ構造の光起電力装置では、通常、光が入射される結晶系シリコン基板の表面側の抵抗と光吸収とのバランスが最適になるように、表面側の透明導電膜に含有される金属ドーパントの量が制御されている。すなわち、酸化物からなる透明導電膜は、金属ドーパントの含有量が多くなれば、抵抗が低くなるとともに、光吸収が増加する。その一方、金属ドーパントの含有量が少なくなれば、抵抗が高くなるとともに、光吸収が低減する。したがって、表面側（光入射側）の透明導電膜の金属ドーパントの含有量を制御することによって、表面側の透明導電膜の抵抗と光吸収とのバランスを制御することが可能となる。また、従来の両面ＨＩＴ構造の光起電力装置では、表面側（光入射側）の透明導電膜と裏面側の透明導電膜とは同じ膜質設計にするのが一般的であるので、表面側の透明導電膜と裏面側の透明導電膜とには同じ量の金属ドーパントが含有されていた。
【０００４】
【特許文献１】
特開２００１−３４５４６３号公報
【発明が解決しようとする課題】
しかしながら、従来の両面ＨＩＴ構造の光起電力装置では、上記のように、表面側（光入射側）の透明導電膜の抵抗と光吸収とのバランスのみを考慮して、表面側および裏面側の透明導電膜に同じ量の金属ドーパントを含有していたので、結晶系シリコン基板の裏面側における光吸収の抑制が効率的に行われていなかった。このため、裏面側の透明導電膜の光吸収損失に起因して出力が低下するという不都合があった。その結果、高いセル特性を実現するのが困難であるという問題点があった。
【０００５】
この発明は、上記のような課題を解決するためになされたものであり、この発明の１つの目的は、高いセル特性を実現することが可能な光起電力装置を提供することである。
【０００６】
この発明のもう１つの目的は、上記の光起電力装置において、結晶系半導体基板の裏面側における光吸収損失に起因する出力の低下を抑制することである。
【０００７】
【課題を解決するための手段および発明の効果】
上記目的を達成するために、この発明の一の局面による光起電力装置は、表面および裏面を有し、表面側から光が入射される第１導電型の結晶系半導体基板と、結晶系半導体基板の表面上に形成された非晶質半導体膜と、非晶質半導体膜上に形成され、１．５質量％以上５質量％以下の金属ドーパントが含有されている第１透明導電膜と、結晶系半導体基板の裏面上に形成され、第１透明導電膜の金属ドーパントの含有量よりも少ない金属ドーパントが含有されている第２透明導電膜とを備えている。なお、本発明における非晶質半導体膜は、微結晶半導体膜も含む広い概念である。
【０００８】
この一の局面による光起電力装置では、上記のように、結晶系半導体基板の表面側（光入射側）に形成される第１透明導電膜の金属ドーパントの含有量を、１．５質量％以上５質量％以下にするとともに、結晶系半導体基板の裏面側に形成される第２透明導電膜の金属ドーパントの含有量を、第１透明導電膜の金属ドーパントの含有量よりも少なくすることによって、結晶系半導体基板の表面側の抵抗と光吸収とのバランスを最適化しながら、結晶系半導体基板の裏面側における光吸収の増加を抑制することができる。これにより、結晶系半導体基板の表面側における抵抗と光吸収とのバランスを最適化しながら、結晶系半導体基板の裏面側における光吸収損失に起因する出力の低下を抑制することができるので、高いセル特性を実現することができる。
【０００９】
上記一の局面による光起電力装置において、好ましくは、第２透明導電膜の金属ドーパントの含有量は、０．５質量％以上３質量％以下である。このように構成すれば、容易に、結晶系半導体基板の裏面側における光吸収損失に起因する出力の低下を抑制することができる。
【００１０】
上記一の局面による光起電力装置において、好ましくは、第１透明導電膜および第２透明導電膜は、ＩＴＯ膜を含み、金属ドーパントは、Ｓｎドーパントを含む。このように構成すれば、第１透明導電膜および第２透明導電膜を構成するＩＴＯ膜に対するＳｎドーパントの含有量を上記のように設定することにより、容易に、結晶系半導体基板の表面側（光入射側）における抵抗と光吸収とのバランスを最適化しながら、結晶系半導体基板の裏面側における光吸収損失に起因する出力の低下を抑制することができる。
【００１１】
上記一の局面による光起電力装置において、好ましくは、第１透明導電膜および第２透明導電膜は、ＺｎＯ膜を含み、金属ドーパントは、ＡｌドーパントおよびＧａドーパントのいずれか一方を含む。このように構成すれば、第１透明導電膜および第２透明導電膜を構成するＺｎＯ膜に対するＡｌドーパントおよびＧａドーパントのいずれか一方の含有量を上記のように設定することにより、容易に、結晶系半導体基板の表面側（光入射側）における抵抗と光吸収とのバランスを最適化しながら、結晶系半導体基板の裏面側における光吸収損失に起因する出力の低下を抑制することができる。
【００１２】
上記一の局面による光起電力装置において、好ましくは、非晶質半導体膜は、結晶系半導体基板上に形成された実質的に真性な第１非晶質半導体膜と、第１非晶質半導体膜上に形成された第２導電型の第２非晶質半導体膜とを含み、結晶系半導体基板の裏面と第２透明導電膜との間に形成された実質的に真性な第３非晶質半導体膜と、第３非晶質半導体膜の裏面上に形成された第１導電型の第４非晶質半導体膜とをさらに備える。このように構成すれば、高いセル特性を有する両面ＨＩＴ構造の光起電力装置を実現することができる。
【００１３】
【発明の実施の形態】
以下、本発明の実施形態を図面に基づいて説明する。
【００１４】
図１は、本発明の一実施形態による両面ＨＩＴ構造を有する光起電力装置の構造を示した断面図である。まず、図１を参照して、本実施形態による光起電力装置の構造について説明する。
【００１５】
本実施形態による光起電力装置では、図１に示すように、約１Ω・ｃｍの抵抗率および約３００μｍの厚みを有するとともに、（１００）面を表面とするｎ型単結晶シリコン基板１の表面上に、約５ｎｍの厚みを有する実質的に真性なノンドープ非晶質シリコン膜２、約５ｎｍの厚みを有するｐ型非晶質シリコン膜３、約１００ｎｍの厚みを有するＩＴＯ（酸化インジウム錫）膜からなる透明導電膜４、および、数十μｍの厚みを有する銀からなる金属電極５が順次形成されている。なお、ｎ型単結晶シリコン基板１は、本発明の「結晶系半導体基板」の一例である。また、ノンドープ非晶質シリコン膜２は、本発明の「非晶質半導体膜」および「第１非晶質半導体膜」の一例であり、ｐ型非晶質シリコン膜３は、本発明の「非晶質半導体膜」および「第２非晶質半導体膜」の一例である。また、透明導電膜４は、本発明の「第１透明導電膜」および「ＩＴＯ膜」の一例である。
【００１６】
また、ｎ型単結晶シリコン基板１の裏面上には、ｎ型単結晶シリコン基板１に近い方から順に、約５ｎｍの厚みを有する実質的に真性なノンドープ非晶質シリコン膜１２、約５ｎｍの厚みを有するｎ型非晶質シリコン膜１３、約１００ｎｍの厚みを有するＩＴＯ膜からなる透明導電膜１４、および、数十μｍの厚みを有する銀からなる金属電極１５が形成されている。そして、ノンドープ非晶質シリコン膜１２、ｎ型非晶質シリコン膜１３および透明導電膜１４によって、いわゆるＢＳＦ構造が構成される。なお、ノンドープ非晶質シリコン膜１２は、本発明の「第３非晶質半導体膜」の一例であり、ｎ型非晶質シリコン膜１３は、本発明の「第４非晶質半導体膜」の一例である。また、透明導電膜１４は、本発明の「第２透明導電膜」および「ＩＴＯ膜」の一例である。
【００１７】
ここで、本実施形態では、ｎ型単結晶シリコン基板１の表面側に形成された透明導電膜４のＳｎ（錫）ドーパントの含有量は、約１．５ｗｔ％（質量％）以上約５ｗｔ％以下（たとえば、約３ｗｔ％）に設定されているとともに、ｎ型単結晶シリコン基板１の裏面側に形成された透明導電膜１４のＳｎドーパントの含有量は、表面側の透明導電膜４のＳｎドーパントの含有量よりも少なく、かつ、約０．５ｗｔ％以上約３ｗｔ％以下（たとえば、約１ｗｔ％）に設定されている。なお、裏面側の透明導電膜１４のＳｎドーパントの含有量を少なくすることにより、裏面側の透明導電膜１４の抵抗が高くなる。しかし、ｎ型単結晶シリコン基板１の裏面側は、ｎ型単結晶シリコン基板１と同じｎ型領域であるため、ｎ型単結晶シリコン基板１の表面側と異なり、ｎ型単結晶シリコン基板１自体がキャリアを集電するための領域として機能する。このため、裏面側の透明導電膜１４のＳｎドーパントの含有量を少なくした場合に、裏面側の透明導電膜１４の抵抗が高くなることにより、裏面側の透明導電膜１４においてキャリアの移動度が低下したとしても、ｎ型単結晶シリコン基板１でキャリアが集電されるので、光起電力装置の集電特性の劣化が抑制される。したがって、裏面側の透明導電膜１４のＳｎドーパントの含有量を少なくしたとしても問題はない。
【００１８】
図２〜図４は、図１に示した一実施形態による光起電力装置の製造プロセスを説明するための断面図である。次に、図１〜図４を参照して、本実施形態による光起電力装置の製造プロセスについて説明する。
【００１９】
まず、図２に示すように、約１Ω・ｃｍの抵抗率および約３００μｍの厚みを有するとともに、（１００）面を表面とするｎ型単結晶シリコン基板１を洗浄することによって、ｎ型単結晶シリコン基板１の表面に付着した不純物を除去する。
【００２０】
次に、図３に示すように、高周波プラズマＣＶＤ法を用いて、ｎ型単結晶シリコン基板１の表面上に、約５ｎｍの厚みを有する実質的に真性なノンドープ非晶質シリコン膜２、および、約５ｎｍの厚みを有するｐ型非晶質シリコン膜３を順次形成する。このノンドープ非晶質シリコン膜２およびｐ型非晶質シリコン膜３の形成条件は、形成温度：約１００℃〜約２５０℃、反応圧力：約２６．６Ｐａ〜約７９．８Ｐａ、高周波電力：約１０Ｗ〜約１００Ｗ、および、周波数：約１３．５６ＭＨｚである。
【００２１】
この後、上記したノンドープ非晶質シリコン膜２およびｐ型非晶質シリコン膜３の形成プロセスと同様のプロセスを用いて、ｎ型単結晶シリコン基板１の裏面上に、ｎ型単結晶シリコン基板１に近い方から順に、約５ｎｍの厚みを有する実質的に真性なノンドープ非晶質シリコン膜１２、および、約５ｎｍの厚みを有するｎ型非晶質シリコン膜１３を形成する。
【００２２】
次に、図４に示すように、マグネトロンスパッタリング法を用いて、表面側のｐ型非晶質シリコン膜３上に、約１００ｎｍの厚みを有するＩＴＯ（酸化インジウム錫）膜からなる透明導電膜４を形成する。この表面側の透明導電膜４の形成条件は、形成温度：約２５０℃、Ａｒ（アルゴン）ガス流量：約２００ｓｃｃｍ、Ｏ2（酸素）ガス流量：約５０ｓｃｃｍ、電力：約０．５ｋＷ〜約３ｋＷである。また、ターゲット（図示せず）としては、表面側の透明導電膜４のＳｎ（錫）ドーパントの含有量が、約１．５ｗｔ％以上約５ｗｔ％以下（たとえば、約３ｗｔ％）になるようにＳｎドーパントの含有量が制御されたＩＴＯからなるターゲットを用いる。
【００２３】
この後、上記した表面側の透明導電膜４の形成プロセスと同様のプロセスを用いて、裏面側のｎ型非晶質シリコン膜１３上に、約１００ｎｍの厚みを有するＩＴＯ膜からなる透明導電膜１４を形成する。この際、本実施形態では、ターゲットとして、裏面側の透明導電膜１４のＳｎドーパントの含有量が、表面側の透明導電膜４のＳｎドーパントの含有量よりも少なく、かつ、約０．５ｗｔ％以上約３ｗｔ％以下（たとえば、約１ｗｔ％）になるようにＳｎドーパントの含有量が制御されたＩＴＯからなるターゲット（図示せず）を用いる。
【００２４】
最後に、図１に示したように、スクリーン印刷法を用いて、透明導電膜４および１４上の所定領域に、それぞれ、数十μｍの厚みを有する銀からなる金属電極５および１５を形成する。これにより、本実施形態による光起電力装置が形成される。
【００２５】
本実施形態では、上記のように、ｎ型単結晶シリコン基板１の表面側（光入射側）に形成される透明導電膜４のＳｎドーパントの含有量を、約１．５ｗｔ％以上約５ｗｔ％以下（たとえば、約３ｗｔ％）にするとともに、ｎ型単結晶シリコン基板１の裏面側に形成される透明導電膜１４のＳｎドーパントの含有量を、表面側の透明導電膜４のＳｎドーパントの含有量よりも少なく、かつ、約０．５ｗｔ％以上約３ｗｔ％以下（たとえば、約１ｗｔ％）にすることによって、ｎ型単結晶シリコン基板１の表面側の抵抗と光吸収とのバランスを最適化しながら、ｎ型単結晶シリコン基板１の裏面側における光吸収の増加を抑制することができる。これにより、ｎ型単結晶シリコン基板１の表面側における抵抗と光吸収とのバランスを最適化しながら、ｎ型単結晶シリコン基板１の裏面側における光吸収損失に起因する出力の低下を抑制することができるので、高いセル特性を実現することができる。
【００２６】
次に、上記した本実施形態による効果を確認するために、表面側の透明導電膜のＳｎドーパントの含有量および裏面側の透明導電膜のＳｎドーパントの含有量をそれぞれ変化させた場合の光起電力装置の出力改善率を測定した結果について説明する。ここで、出力改善率とは、表面側の透明導電膜のＳｎドーパントの含有量および裏面側の透明導電膜のＳｎドーパントの含有量がそれぞれ約１０ｗｔ％に設定された光起電力装置のセル出力との比率である。
【００２７】
図５は、表面側の透明導電膜のＳｎドーパントの含有量を変化させた場合の光起電力装置の出力改善率を示したグラフであり、図６は、裏面側の透明導電膜のＳｎドーパントの含有量を変化させた場合の光起電力装置の出力改善率を示したグラフである。なお、表面側の透明導電膜のＳｎドーパントの含有量を変化させた場合（図５）は、裏面側の透明導電膜のＳｎドーパントの含有量を約１０ｗｔ％に設定し、裏面側の透明導電膜のＳｎドーパントの含有量を変化させた場合（図６）は、表面側の透明導電膜のＳｎドーパントの含有量を約１０ｗｔ％に設定した。また、透明導電膜のＳｎドーパントの含有量は、上記した透明導電膜４および１４の形成プロセスにおいて、ターゲットとしてのＩＴＯのＳｎドーパントの含有量を制御することにより制御した。また、透明導電膜のＳｎドーパントの含有量は、ＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ Ｉｏｎ Ｍａｓｓ Ｓｐｅｃｔｒｏｍｅｔｅｒ：２次イオン質量分析法）を用いて測定した。
【００２８】
図５を参照して、表面側の透明導電膜のＳｎドーパントの含有量が約１．５ｗｔ％以上約５ｗｔ％以下の範囲では、出力改善率が約２％以上向上するとともに、最大で約２．５％向上する（Ｓｎドーパントの含有量が約３ｗｔ％の場合）ことが判明した。これは、表面側の透明導電膜のＳｎドーパントの含有量が約１．５ｗｔ％以上約５ｗｔ％以下の範囲では、ｎ型単結晶シリコン基板の表面側の抵抗と光吸収とのバランスが最適化されるためであると考えられる。また、図６を参照して、裏面側の透明導電膜のＳｎドーパントの含有量が約０．５ｗｔ％以上約３ｗｔ％以下の範囲では、出力改善率が約０．５％以上向上するとともに、最大で約１％向上する（Ｓｎドーパントの含有量が約１ｗｔ％の場合）ことが判明した。これは、裏面側の透明導電膜のＳｎドーパントの含有量が約０．５ｗｔ％以上約３ｗｔ％以下の範囲では、ｎ型単結晶シリコン基板の裏面側において、金属電極により反射された光の吸収が抑制されるためであると考えられる。
【００２９】
また、表面側の透明導電膜のＳｎドーパントの含有量および裏面側の透明導電膜のＳｎドーパントの含有量が、それぞれ、約３ｗｔ％および約１ｗｔ％に設定された光起電力装置の出力改善率を測定した結果、出力改善率が約３．５％向上することが判明した。これは、上記のＳｎドーパントの含有量の場合、ｎ型単結晶シリコン基板の表面側の抵抗と光吸収とのバランスが最適化され、かつ、ｎ型単結晶シリコン基板の裏面側において、金属電極により反射された光の吸収が抑制されるためであると考えられる。
【００３０】
上記した結果より、ｎ型単結晶シリコン基板の表面側に形成される透明導電膜のＳｎドーパントの含有量を、約３ｗｔ％（約１．５ｗｔ％以上約５ｗｔ％以下）にするとともに、ｎ型単結晶シリコン基板の裏面側に形成される透明導電膜のＳｎドーパントの含有量を、約１ｗｔ％（約０．５ｗｔ％以上約３ｗｔ％以下）にすることによって、ｎ型単結晶シリコン基板の表面側における抵抗と光吸収とのバランスを最適化しながら、ｎ型単結晶シリコン基板の裏面側における光吸収損失に起因する出力の低下を抑制することができることが確認された。
【００３１】
なお、今回開示された実施形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態の説明ではなく特許請求の範囲によって示され、さらに特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれる。
【００３２】
たとえば、上記実施形態では、ＩＴＯ膜からなる透明導電膜４および１４を用いた場合について説明したが、本発明はこれに限らず、ＺｎＯ膜からなる透明導電膜を用いるようにしてもよい。この場合、本願発明者が実験により確認したところ、ＺｎＯ膜からなる透明導電膜に対してＡｌをドーパントとして用いるとともに、表面側のＺｎＯ膜からなる透明導電膜のＡｌドーパントの含有量および裏面側のＺｎＯ膜からなる透明導電膜のＡｌドーパントの含有量を、それぞれ、約３ｗｔ％および約１ｗｔ％に設定することによって、光起電力装置の出力改善率を約２．５％向上させることができた。また、ＺｎＯ膜からなる透明導電膜を用いる場合、Ｇａをドーパントとして用いるとともに、表面側のＺｎＯ膜からなる透明導電膜のＧａドーパントの含有量および裏面側のＺｎＯ膜からなる透明導電膜のＧａドーパントの含有量を、それぞれ、約３ｗｔ％および約１ｗｔ％に設定することによっても、光起電力装置の出力改善率を約２．５％向上させることができた。なお、透明導電膜としてＺｎＯ膜を用いる場合のＡｌドーパントまたはＧａドーパントの含有量としては、表面側の透明導電膜については、約１．５ｗｔ％以上約５ｗｔ％以下の範囲であることが好ましく、裏面側の透明導電膜については、表面側の透明導電膜よりも含有量が少なく、かつ、約０．５ｗｔ％以上約３ｗｔ％以下の範囲であることが好ましい。
【００３３】
また、上記実施形態では、ｎ型単結晶シリコン基板１とｐ型非晶質シリコン膜３との間、および、ｎ型単結晶シリコン基板１とｎ型非晶質シリコン膜１３との間に、それぞれ、実質的に真性なノンドープ非晶質シリコン膜２および１２を形成したＨＩＴ構造に本発明を適用した場合について説明したが、本発明はこれに限らず、導電性を有する単結晶シリコン基板と導電性を有する非晶質シリコン膜との間に、実質的に真性なノンドープ非晶質シリコン膜を形成しない構造の光起電力装置にも適用可能である。
【００３４】
また、上記実施形態では、ｎ型単結晶シリコン基板１の裏面上に実質的に真性なノンドープ非晶質シリコン膜１２およびｎ型非晶質シリコン膜１３が形成されたＢＳＦ構造を有する光起電力装置の透明導電膜に本発明を適用する例を示したが、本発明はこれに限らず、ＢＳＦ構造を有しない光起電力装置の透明導電膜にも適用可能である。
【００３５】
また、上記実施形態では、結晶系半導体基板の表面上および裏面上に形成される非晶質半導体膜の一例として、非晶質シリコン膜を用いた場合について説明したが、本発明はこれに限らず、非晶質シリコン膜に代えて、非晶質ＳｉＣ膜、非晶質ＳｉＧｅ膜、非晶質ＳｉＯX膜および非晶質ＳｉＮ膜などのシリコン系半導体材料からなる非晶質半導体膜を用いてもよい。
【図面の簡単な説明】
【図１】本発明の一実施形態による両面ＨＩＴ構造を有する光起電力装置の構造を示した断面図である。
【図２】図１に示した一実施形態による光起電力装置の製造プロセスを説明するための断面図である。
【図３】図１に示した一実施形態による光起電力装置の製造プロセスを説明するための断面図である。
【図４】図１に示した一実施形態による光起電力装置の製造プロセスを説明するための断面図である。
【図５】表面側の透明導電膜のＳｎドーパントの含有量を変化させた場合の光起電力装置の出力改善率を示したグラフである。
【図６】裏面側の透明導電膜のＳｎドーパントの含有量を変化させた場合の光起電力装置の出力改善率を示したグラフである。
【符号の説明】
１ ｎ型単結晶シリコン基板（結晶系半導体基板）
２ ノンドープ非晶質シリコン膜（非晶質半導体膜、第１非晶質半導体膜）
３ ｐ型非晶質シリコン膜（非晶質半導体膜、第２非晶質半導体膜）
４ 透明導電膜（第１透明導電膜、ＩＴＯ膜）
１２ ノンドープ非晶質シリコン膜（第３非晶質半導体膜）
１３ ｎ型非晶質シリコン膜（第４非晶質半導体膜）
１４ 透明導電膜（第２透明導電膜、ＩＴＯ膜）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photovoltaic device, and more particularly to a photovoltaic device in which a transparent conductive film is formed on each of a front surface side and a back surface side of a crystalline semiconductor substrate.
[0002]
[Prior art]
Conventionally, a substantially intrinsic non-single crystal silicon film, a second conductivity type non-single crystal silicon film, and a transparent conductive film have been formed on the surface of a first conductivity type crystalline silicon substrate to which light is incident from the surface side. A photovoltaic device having a sequentially formed HIT (Heterojunction with thin thin layer) structure is known (for example, see Patent Document 1).
[0003]
Conventionally, in the photovoltaic device having the HIT structure disclosed in Patent Document 1, a substantially intrinsic non-single crystal silicon film, first conductive material is formed on the back surface of the first conductive type crystalline silicon substrate. A photovoltaic device having a double-sided HIT structure having a so-called BSF (Back Surface Field) structure in which a transparent conductive film made of a non-single crystal silicon film and an oxide is formed is also known. In this conventional photovoltaic device having a double-sided HIT structure, it is usually contained in the transparent conductive film on the surface side so that the balance between resistance and light absorption on the surface side of the crystalline silicon substrate on which light is incident is optimal. The amount of metal dopant to be controlled is controlled. That is, in the transparent conductive film made of an oxide, as the content of the metal dopant increases, the resistance decreases and the light absorption increases. On the other hand, if the content of the metal dopant decreases, the resistance increases and the light absorption decreases. Therefore, by controlling the content of the metal dopant in the transparent conductive film on the surface side (light incident side), it is possible to control the balance between the resistance and light absorption of the transparent conductive film on the surface side. Further, in a conventional photovoltaic device having a double-sided HIT structure, the surface side (light incident side) transparent conductive film and the back side transparent conductive film are generally designed to have the same film quality design. The same amount of metal dopant was contained in the transparent conductive film and the transparent conductive film on the back side.
[0004]
[Patent Document 1]
JP, 2001-345463, A [Problems to be solved by the invention]
However, in the conventional photovoltaic device with the double-sided HIT structure, as described above, only the balance between the resistance of the transparent conductive film on the front surface side (light incident side) and the light absorption is taken into consideration, so that Since the transparent conductive film contained the same amount of metal dopant, light absorption on the back side of the crystalline silicon substrate was not efficiently suppressed. For this reason, there was a disadvantage that the output was reduced due to the light absorption loss of the transparent conductive film on the back side. As a result, there is a problem that it is difficult to realize high cell characteristics.
[0005]
The present invention has been made to solve the above-described problems, and one object of the present invention is to provide a photovoltaic device capable of realizing high cell characteristics.
[0006]
Another object of the present invention is to suppress a decrease in output due to light absorption loss on the back side of the crystalline semiconductor substrate in the photovoltaic device.
[0007]
[Means for Solving the Problems and Effects of the Invention]
In order to achieve the above object, a photovoltaic device according to one aspect of the present invention includes a first conductive type crystalline semiconductor substrate having a front surface and a back surface and receiving light from the front surface side, and a crystalline semiconductor An amorphous semiconductor film formed on the surface of the substrate, a first transparent conductive film formed on the amorphous semiconductor film and containing a metal dopant of 1.5% by mass or more and 5% by mass or less, And a second transparent conductive film formed on the back surface of the crystalline semiconductor substrate and containing a metal dopant less than the metal dopant content of the first transparent conductive film. Note that the amorphous semiconductor film in the present invention is a broad concept including a microcrystalline semiconductor film.
[0008]
In the photovoltaic device according to this aspect, as described above, the content of the metal dopant in the first transparent conductive film formed on the surface side (light incident side) of the crystalline semiconductor substrate is 1.5% by mass. By making the content 5% by mass or less and reducing the content of the metal dopant in the second transparent conductive film formed on the back surface side of the crystalline semiconductor substrate to be lower than the content of the metal dopant in the first transparent conductive film. The increase in light absorption on the back side of the crystalline semiconductor substrate can be suppressed while optimizing the balance between the resistance and light absorption on the front side of the crystalline semiconductor substrate. As a result, it is possible to suppress a decrease in output caused by light absorption loss on the back side of the crystalline semiconductor substrate while optimizing the balance between resistance and light absorption on the front side of the crystalline semiconductor substrate. Characteristics can be realized.
[0009]
In the photovoltaic device according to the above aspect, the content of the metal dopant in the second transparent conductive film is preferably 0.5% by mass or more and 3% by mass or less. If comprised in this way, the fall of the output resulting from the light absorption loss in the back surface side of a crystalline semiconductor substrate can be suppressed easily.
[0010]
In the photovoltaic device according to the above aspect, the first transparent conductive film and the second transparent conductive film preferably include an ITO film, and the metal dopant includes an Sn dopant. If comprised in this way, by setting Sn dopant content with respect to the ITO film | membrane which comprises a 1st transparent conductive film and a 2nd transparent conductive film as mentioned above, the surface side of a crystalline semiconductor substrate ( While optimizing the balance between resistance and light absorption on the light incident side, it is possible to suppress a decrease in output due to light absorption loss on the back side of the crystalline semiconductor substrate.
[0011]
In the photovoltaic device according to the above aspect, the first transparent conductive film and the second transparent conductive film preferably include a ZnO film, and the metal dopant includes any one of an Al dopant and a Ga dopant. If comprised in this way, by setting content of any one of Al dopant and Ga dopant with respect to the ZnO film | membrane which comprises a 1st transparent conductive film and a 2nd transparent conductive film as mentioned above, it is easy to crystallize While optimizing the balance between resistance and light absorption on the front surface side (light incident side) of the semiconductor substrate, it is possible to suppress a decrease in output due to light absorption loss on the back surface side of the crystalline semiconductor substrate.
[0012]
In the photovoltaic device according to the above aspect, preferably, the amorphous semiconductor film includes a substantially intrinsic first amorphous semiconductor film formed on a crystalline semiconductor substrate, and a first amorphous semiconductor. A second amorphous semiconductor film of the second conductivity type formed on the film, and a substantially intrinsic third amorphous film formed between the back surface of the crystalline semiconductor substrate and the second transparent conductive film. And a first conductive type fourth amorphous semiconductor film formed on the back surface of the third amorphous semiconductor film. If comprised in this way, the photovoltaic device of the double-sided HIT structure which has a high cell characteristic is realizable.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a cross-sectional view showing the structure of a photovoltaic device having a double-sided HIT structure according to an embodiment of the present invention. First, the structure of the photovoltaic device according to the present embodiment will be described with reference to FIG.
[0015]
In the photovoltaic device according to the present embodiment, as shown in FIG. 1, the surface of the n-type single crystal silicon substrate 1 having a resistivity of about 1 Ω · cm and a thickness of about 300 μm and having a (100) plane as the surface. On top, a substantially intrinsic non-doped amorphous silicon film 2 having a thickness of about 5 nm, a p-type amorphous silicon film 3 having a thickness of about 5 nm, and an ITO (indium tin oxide) film having a thickness of about 100 nm. A transparent conductive film 4 made of silver and a metal electrode 5 made of silver having a thickness of several tens of μm are sequentially formed. The n-type single crystal silicon substrate 1 is an example of the “crystalline semiconductor substrate” in the present invention. The non-doped amorphous silicon film 2 is an example of the “amorphous semiconductor film” and “first amorphous semiconductor film” in the present invention, and the p-type amorphous silicon film 3 is “ It is an example of “amorphous semiconductor film” and “second amorphous semiconductor film”. The transparent conductive film 4 is an example of the “first transparent conductive film” and “ITO film” in the present invention.
[0016]
Further, on the back surface of the n-type single crystal silicon substrate 1, a substantially intrinsic non-doped amorphous silicon film 12 having a thickness of about 5 nm and a thickness of about 5 nm are sequentially formed from the side closer to the n-type single crystal silicon substrate 1. An n-type amorphous silicon film 13 having a thickness, a transparent conductive film 14 made of an ITO film having a thickness of about 100 nm, and a metal electrode 15 made of silver having a thickness of several tens of μm are formed. The non-doped amorphous silicon film 12, the n-type amorphous silicon film 13, and the transparent conductive film 14 constitute a so-called BSF structure. The non-doped amorphous silicon film 12 is an example of the “third amorphous semiconductor film” of the present invention, and the n-type amorphous silicon film 13 is the “fourth amorphous semiconductor film” of the present invention. It is an example. The transparent conductive film 14 is an example of the “second transparent conductive film” and “ITO film” in the present invention.
[0017]
Here, in this embodiment, the content of Sn (tin) dopant in the transparent conductive film 4 formed on the surface side of the n-type single crystal silicon substrate 1 is about 1.5 wt% (mass%) or more and about 5 wt%. The content of Sn dopant in the transparent conductive film 14 formed on the back side of the n-type single crystal silicon substrate 1 is set to the following (for example, about 3 wt%). It is less than the dopant content and is set to about 0.5 wt% or more and about 3 wt% or less (for example, about 1 wt%). In addition, the resistance of the transparent conductive film 14 on the back side is increased by reducing the Sn dopant content of the transparent conductive film 14 on the back side. However, since the back side of the n-type single crystal silicon substrate 1 is the same n-type region as the n-type single crystal silicon substrate 1, the n-type single crystal silicon substrate 1 is different from the front side of the n-type single crystal silicon substrate 1. The device itself functions as an area for collecting carriers. For this reason, when the content of Sn dopant in the transparent conductive film 14 on the back surface side is reduced, the resistance of the transparent conductive film 14 on the back surface side increases, so that the carrier mobility in the transparent conductive film 14 on the back surface side increases. Even if it is lowered, the carriers are collected by the n-type single crystal silicon substrate 1, so that the deterioration of the current collection characteristics of the photovoltaic device is suppressed. Therefore, there is no problem even if the Sn dopant content of the transparent conductive film 14 on the back side is reduced.
[0018]
2-4 is sectional drawing for demonstrating the manufacturing process of the photovoltaic apparatus by one Embodiment shown in FIG. Next, the manufacturing process of the photovoltaic device according to the present embodiment will be described with reference to FIGS.
[0019]
First, as shown in FIG. 2, an n-type single crystal silicon substrate 1 having a resistivity of about 1 Ω · cm and a thickness of about 300 μm and having a (100) plane as a surface is washed. Impurities attached to the surface of the silicon substrate 1 are removed.
[0020]
Next, as shown in FIG. 3, a substantially intrinsic non-doped amorphous silicon film 2 having a thickness of about 5 nm is formed on the surface of the n-type single crystal silicon substrate 1 using a high-frequency plasma CVD method, and Then, a p-type amorphous silicon film 3 having a thickness of about 5 nm is sequentially formed. The formation conditions of the non-doped amorphous silicon film 2 and the p-type amorphous silicon film 3 are as follows: formation temperature: about 100 ° C. to about 250 ° C., reaction pressure: about 26.6 Pa to about 79.8 Pa, high frequency power: about 10 W to about 100 W, and frequency: about 13.56 MHz.
[0021]
Thereafter, an n-type single crystal silicon substrate is formed on the back surface of the n-type single crystal silicon substrate 1 using a process similar to the process for forming the non-doped amorphous silicon film 2 and the p-type amorphous silicon film 3 described above. A substantially intrinsic non-doped amorphous silicon film 12 having a thickness of about 5 nm and an n-type amorphous silicon film 13 having a thickness of about 5 nm are formed in order from the side closer to 1.
[0022]
Next, as shown in FIG. 4, a transparent conductive film 4 made of an ITO (indium tin oxide) film having a thickness of about 100 nm is formed on the p-type amorphous silicon film 3 on the surface side by using a magnetron sputtering method. Form. The formation conditions of the transparent conductive film 4 on the surface side are as follows: formation temperature: about 250 ° C., Ar (argon) gas flow rate: about 200 sccm, O 2 (oxygen) gas flow rate: about 50 sccm, power: about 0.5 kW to about 3 kW It is. Further, as a target (not shown), the Sn (tin) dopant content of the transparent conductive film 4 on the surface side is about 1.5 wt% or more and about 5 wt% or less (for example, about 3 wt%). A target made of ITO in which the content of Sn dopant is controlled is used.
[0023]
Thereafter, a transparent conductive film made of an ITO film having a thickness of about 100 nm is formed on the n-type amorphous silicon film 13 on the back side by using a process similar to the process for forming the transparent conductive film 4 on the front side. 14 is formed. At this time, in this embodiment, as a target, the content of Sn dopant in the transparent conductive film 14 on the back surface side is smaller than the content of Sn dopant in the transparent conductive film 4 on the front surface side, and about 0.5 wt%. A target (not shown) made of ITO in which the Sn dopant content is controlled to be about 3 wt% or less (for example, about 1 wt%) is used.
[0024]
Finally, as shown in FIG. 1, metal electrodes 5 and 15 made of silver having a thickness of several tens of μm are formed in predetermined regions on the transparent conductive films 4 and 14 by screen printing, respectively. . Thereby, the photovoltaic device according to the present embodiment is formed.
[0025]
In the present embodiment, as described above, the Sn dopant content of the transparent conductive film 4 formed on the surface side (light incident side) of the n-type single crystal silicon substrate 1 is about 1.5 wt% or more and about 5 wt%. In addition to the following (for example, about 3 wt%), the Sn dopant content of the transparent conductive film 14 formed on the back surface side of the n-type single crystal silicon substrate 1 is changed to the Sn dopant content of the transparent conductive film 4 on the front surface side. The balance between resistance and light absorption on the surface side of the n-type single crystal silicon substrate 1 is optimized by making the amount less than the amount and about 0.5 wt% to about 3 wt% (for example, about 1 wt%). However, an increase in light absorption on the back side of the n-type single crystal silicon substrate 1 can be suppressed. This suppresses a decrease in output due to light absorption loss on the back side of the n-type single crystal silicon substrate 1 while optimizing the balance between resistance and light absorption on the front side of the n-type single crystal silicon substrate 1. Therefore, high cell characteristics can be realized.
[0026]
Next, in order to confirm the effect of the above-described embodiment, the photosensitivity when the content of the Sn dopant in the transparent conductive film on the front surface side and the content of the Sn dopant in the transparent conductive film on the back surface side are respectively changed. The result of measuring the output improvement rate of the power device will be described. Here, the output improvement rate is the cell output of the photovoltaic device in which the Sn dopant content of the transparent conductive film on the front surface side and the Sn dopant content of the transparent conductive film on the back surface side are each set to about 10 wt%. And the ratio.
[0027]
FIG. 5 is a graph showing the output improvement rate of the photovoltaic device when the Sn dopant content of the transparent conductive film on the front surface side is changed, and FIG. 6 is a Sn dopant of the transparent conductive film on the back surface side. It is the graph which showed the output improvement rate of the photovoltaic apparatus at the time of changing content of. When the content of Sn dopant in the transparent conductive film on the front side is changed (FIG. 5), the content of Sn dopant in the transparent conductive film on the back side is set to about 10 wt%, and the transparent conductive on the back side is set. When the content of Sn dopant in the film was changed (FIG. 6), the content of Sn dopant in the transparent conductive film on the surface side was set to about 10 wt%. Further, the Sn dopant content of the transparent conductive film was controlled by controlling the Sn dopant content of ITO as a target in the process of forming the transparent conductive films 4 and 14 described above. The content of Sn dopant in the transparent conductive film was measured using SIMS (Secondary Ion Mass Spectrometer).
[0028]
Referring to FIG. 5, when the Sn dopant content of the transparent conductive film on the surface side is in the range of about 1.5 wt% or more and about 5 wt% or less, the output improvement rate is improved by about 2% or more, and at most about 2 It was found to be improved by 5% (when the Sn dopant content is about 3 wt%). This is because the balance between the resistance and light absorption on the surface side of the n-type single crystal silicon substrate is optimized when the Sn dopant content of the transparent conductive film on the surface side is about 1.5 wt% or more and about 5 wt% or less. It is thought that it is to be done. In addition, referring to FIG. 6, in the range where the Sn dopant content of the transparent conductive film on the back surface side is about 0.5 wt% or more and about 3 wt% or less, the output improvement rate is improved by about 0.5% or more, It has been found that the maximum improvement is about 1% (when the Sn dopant content is about 1 wt%). This is because when the Sn dopant content of the transparent conductive film on the back side is in the range of about 0.5 wt% or more and about 3 wt% or less, the light reflected by the metal electrode on the back side of the n-type single crystal silicon substrate is absorbed. Is considered to be suppressed.
[0029]
Further, the output improvement rate of the photovoltaic device in which the Sn dopant content of the transparent conductive film on the front side and the Sn dopant content of the transparent conductive film on the back side are set to about 3 wt% and about 1 wt%, respectively. As a result, it was found that the output improvement rate was improved by about 3.5%. This is because, in the case of the above Sn dopant content, the balance between the resistance and light absorption on the surface side of the n-type single crystal silicon substrate is optimized, and on the back side of the n-type single crystal silicon substrate, the metal electrode This is probably because the absorption of the light reflected by the light is suppressed.
[0030]
From the above results, the content of Sn dopant in the transparent conductive film formed on the surface side of the n-type single crystal silicon substrate is about 3 wt% (about 1.5 wt% or more and about 5 wt% or less), and n-type By setting the Sn dopant content of the transparent conductive film formed on the back side of the single crystal silicon substrate to about 1 wt% (about 0.5 wt% to about 3 wt%), the surface of the n-type single crystal silicon substrate It was confirmed that a decrease in output caused by light absorption loss on the back side of the n-type single crystal silicon substrate can be suppressed while optimizing the balance between resistance and light absorption on the side.
[0031]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.
[0032]
For example, in the above embodiment, the case where the transparent conductive films 4 and 14 made of an ITO film are used has been described. However, the present invention is not limited to this, and a transparent conductive film made of a ZnO film may be used. In this case, when this inventor confirmed by experiment, while using Al as a dopant with respect to the transparent conductive film which consists of a ZnO film, content of Al dopant of the transparent conductive film which consists of a ZnO film on the surface side, and a back surface side The output improvement rate of the photovoltaic device could be improved by about 2.5% by setting the Al dopant content of the transparent conductive film made of the ZnO film to about 3 wt% and about 1 wt%, respectively. . Moreover, when using the transparent conductive film which consists of a ZnO film, while using Ga as a dopant, content of Ga dopant of the transparent conductive film which consists of a ZnO film on the surface side, and Ga dopant of a transparent conductive film which consists of a ZnO film on the back side The output improvement rate of the photovoltaic device could be improved by about 2.5% by setting the contents of about 3 wt% and about 1 wt%, respectively. The content of the Al dopant or Ga dopant when using a ZnO film as the transparent conductive film is preferably in the range of about 1.5 wt% or more and about 5 wt% or less for the transparent conductive film on the surface side, The content of the transparent conductive film on the back side is less than that of the transparent conductive film on the front side and is preferably in the range of about 0.5 wt% or more and about 3 wt% or less.
[0033]
In the above embodiment, between the n-type single crystal silicon substrate 1 and the p-type amorphous silicon film 3 and between the n-type single crystal silicon substrate 1 and the n-type amorphous silicon film 13, Although the case where the present invention is applied to the HIT structure in which the substantially intrinsic non-doped amorphous silicon films 2 and 12 are respectively formed has been described, the present invention is not limited to this, and the conductive single crystal silicon substrate and The present invention can also be applied to a photovoltaic device having a structure in which a substantially intrinsic non-doped amorphous silicon film is not formed between an amorphous silicon film having conductivity.
[0034]
Further, in the above embodiment, the photovoltaic device having a BSF structure in which the substantially intrinsic non-doped amorphous silicon film 12 and the n-type amorphous silicon film 13 are formed on the back surface of the n-type single crystal silicon substrate 1. Although the example which applies this invention to the transparent conductive film of an apparatus was shown, this invention is applicable not only to this but the transparent conductive film of the photovoltaic apparatus which does not have a BSF structure.
[0035]
In the above embodiment, the case where an amorphous silicon film is used as an example of the amorphous semiconductor film formed on the front surface and the back surface of the crystalline semiconductor substrate has been described. However, the present invention is not limited to this. Instead of the amorphous silicon film, an amorphous semiconductor film made of a silicon-based semiconductor material such as an amorphous SiC film, an amorphous SiGe film, an amorphous SiO x film, or an amorphous SiN film is used. May be.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a photovoltaic device having a double-sided HIT structure according to an embodiment of the present invention.
2 is a cross-sectional view for explaining a manufacturing process of the photovoltaic device according to the embodiment shown in FIG. 1; FIG.
3 is a cross-sectional view for explaining a manufacturing process of the photovoltaic device according to the embodiment shown in FIG. 1. FIG.
4 is a cross-sectional view for explaining a manufacturing process of the photovoltaic device according to the embodiment shown in FIG. 1. FIG.
FIG. 5 is a graph showing the output improvement rate of the photovoltaic device when the content of Sn dopant in the transparent conductive film on the surface side is changed.
FIG. 6 is a graph showing the output improvement rate of the photovoltaic device when the content of Sn dopant in the transparent conductive film on the back side is changed.
[Explanation of symbols]
1 n-type single crystal silicon substrate (crystalline semiconductor substrate)
2 Non-doped amorphous silicon film (amorphous semiconductor film, first amorphous semiconductor film)
3 p-type amorphous silicon film (amorphous semiconductor film, second amorphous semiconductor film)
4 Transparent conductive film (first transparent conductive film, ITO film)
12 Non-doped amorphous silicon film (third amorphous semiconductor film)
13 n-type amorphous silicon film (fourth amorphous semiconductor film)
14 Transparent conductive film (second transparent conductive film, ITO film)

Claims (5)

表面および裏面を有し、前記表面側から光が入射される第１導電型の結晶系半導体基板と、
前記結晶系半導体基板の表面上に形成された非晶質半導体膜と、
前記非晶質半導体膜上に形成され、１．５質量％以上５質量％以下の金属ドーパントが含有されている第１透明導電膜と、
前記結晶系半導体基板の裏面上に形成され、前記第１透明導電膜の金属ドーパントの含有量よりも少ない金属ドーパントが含有されている第２透明導電膜とを備えた、光起電力装置。A first conductive type crystalline semiconductor substrate having a front surface and a back surface, and light is incident from the front surface side;
An amorphous semiconductor film formed on the surface of the crystalline semiconductor substrate;
A first transparent conductive film formed on the amorphous semiconductor film and containing a metal dopant of 1.5% by mass or more and 5% by mass or less;
A photovoltaic device comprising: a second transparent conductive film formed on a back surface of the crystalline semiconductor substrate and containing a metal dopant less than a metal dopant content of the first transparent conductive film. 前記第２透明導電膜の金属ドーパントの含有量は、０．５質量％以上３質量％以下である、請求項１に記載の光起電力装置。The photovoltaic device of Claim 1 whose content of the metal dopant of a said 2nd transparent conductive film is 0.5 mass% or more and 3 mass% or less. 前記第１透明導電膜および前記第２透明導電膜は、ＩＴＯ膜を含み、
前記金属ドーパントは、Ｓｎドーパントを含む、請求項１または２に記載の光起電力装置。The first transparent conductive film and the second transparent conductive film include an ITO film,
The photovoltaic device according to claim 1, wherein the metal dopant includes a Sn dopant. 前記第１透明導電膜および前記第２透明導電膜は、ＺｎＯ膜を含み、
前記金属ドーパントは、ＡｌドーパントおよびＧａドーパントのいずれか一方を含む、請求項１または２に記載の光起電力装置。The first transparent conductive film and the second transparent conductive film include a ZnO film,
The photovoltaic device according to claim 1 or 2, wherein the metal dopant includes one of an Al dopant and a Ga dopant. 前記非晶質半導体膜は、
前記結晶系半導体基板上に形成された実質的に真性な第１非晶質半導体膜と、
前記第１非晶質半導体膜上に形成された第２導電型の第２非晶質半導体膜とを含み、
前記結晶系半導体基板の裏面と前記第２透明導電膜との間に形成された実質的に真性な第３非晶質半導体膜と、
前記第３非晶質半導体膜の裏面上に形成された第１導電型の第４非晶質半導体膜とをさらに備える、請求項１〜４のいずれか１項に記載の光起電力装置。The amorphous semiconductor film is
A substantially intrinsic first amorphous semiconductor film formed on the crystalline semiconductor substrate;
A second conductivity type second amorphous semiconductor film formed on the first amorphous semiconductor film,
A substantially intrinsic third amorphous semiconductor film formed between the back surface of the crystalline semiconductor substrate and the second transparent conductive film;
The photovoltaic device of any one of Claims 1-4 further provided with the 4th amorphous semiconductor film of the 1st conductivity type formed on the back surface of the said 3rd amorphous semiconductor film.
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