JPH05235270A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To easily switch a power source voltage supplied to the whole inner circuit block only by changing a metallize process pattern after the contact by arranging a polysilicon layer in first and second surrounding power source wiring areas arranged internally and externally. CONSTITUTION:The device is provided with first surrounding power source wiring 1 (e.g. a 3V power source), a second surrounding power source wiring 2 (e.g. arranged potential GND), external surrounding power source wiring 8 for supplying an interface block with power source and external surrounding power source wiring 9 (e.g. a 5V power source). A polysilicon layer 3 is arranged on the area of the first surrounding power source wiring or the second surrounding power source wiring 2 regularly and is connected with the areas 1 and 2 by contacts 4 and 5. The connection of the polysilicon layer 3 with an external power source terminal 10 is performed through power source lead wiring 7 connected on a contact 6. Thus, the potentials of the power source wiring 1 and the external power source terminal 10 are resistively divided by the polysilicon layer 3 and is applied on the second surrounding wiring 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device for use in an integrated circuit, and more particularly to an integrated circuit device having an improved arrangement of voltage level conversion circuits for supplying a plurality of power supplies in a CMOS circuit. Note that in this specification, power supply wiring includes a so-called power supply line having a high potential or a low potential and a ground line.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a semiconductor integrated circuit device requiring multiple power supplies has been designed exclusively for each chip. For example, the internal circuit block 1 in the chip
When all 5 are operated at a low voltage and all the interface blocks are operated at a high voltage, circulating power supply wirings 1, 2, 8 and 9 for connecting the internal circuit block portion 15 and the interface block portion to each other are provided. The power supply pads 10 and 12 are drawn out from the wirings 1, 2, 8 and 9, respectively, and low voltage power supply and high voltage power supply are separately provided from outside the chip.

[0003]

That is, the external pad 10 supplies a power supply voltage of 3V to the circuit power supply wiring 1 and the entire internal circuit block 15 from the outside.
2 externally supplies a power supply voltage of 5 V to the circulating power supply wiring 9 and the entire external block. The external pad 11 and the circulating power supplies 2 and 8 are GND circulating power supply wirings. As described above, the external pad 10, the external pad 11, the external pad 12 and at least three types of power supply terminals are required.

The conventional multi-power supply to the macro requires a dedicated design for each chip, so that it takes a lot of time for the design, and errors are likely to occur. Especially, the voltage supplied from outside the chip is high. When all the internal circuit blocks 15 in the chip are operated at a low voltage and all the interface blocks are operated at a high voltage with a potential, or when all the internal circuit blocks 15 in the chip are operated at a low voltage and all the interface blocks are operated at a low voltage. When the number of external terminals of the chip must be increased according to the type of power supply voltage, the chip becomes larger, the number of external terminals increases, and it is required to respond to changes in the circulatory power supply voltage and small step changes. There is a problem that is impossible. In addition, there is a problem in that an error that requires a lot of time provided is likely to occur because it is a dedicated design for each product type.

The object of the present invention is to reduce the chip area, eliminate the number of external connection terminals (pads), and circulate the power supply voltage in a semiconductor integrated circuit device having a circuit block region in which a power supply of different voltages is desired to operate in a chip. It is an object of the present invention to provide a semiconductor integrated circuit device having a possibility of being changed by the fine steps.

[0006]

According to the present invention, an internal circuit block group consisting of semiconductor element groups is arranged on a semiconductor substrate, and a first circuit power supply wiring is arranged outside the internal circuit block group. A second circulating power supply wiring is further wired outside the first circulating power supply wiring, and a polysilicon layer is arranged in the region of the first circulating power supply wiring or the second circulating power supply wiring.
A semiconductor integrated circuit in which the starting point of the polysilicon layer is connected to the first circulating power supply wiring, the intermediate portion is connected to the second circulating power supply wiring, and the end point is connected to another power supply wiring to which a potential is externally applied. Get the device.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a power supply arrangement according to one embodiment of the present invention, and FIG. 3 is an enlarged view showing a circulating power supply region according to one embodiment of the present invention. FIG. 1 shows a first circuit power supply wiring (for example, 3V power supply) 1 for supplying power to the internal circuit block 15, a second circuit power supply wiring (for example, ground potential GND) 2, and an external circuit power supply wiring (for example, ground potential GND) 2 for supplying power to the interface block. , Ground potential GND) 8 and an external circuit power supply wiring (for example, 5 V power supply) 9. The polysilicon layer 3 is regularly arranged in the region of the first circulating power supply wiring 1 or the second circulating power supply wiring 2, and the contact portions 4, 5 are formed.
Connect with. When the polysilicon layer 3 is connected to the external power supply terminal 10, it is connected via the power supply lead wire 7 connected at the contact portion 6. By this, the second
A potential obtained by resistance-dividing the potential of the first peripheral power supply line 1 and the potential of the external power supply terminal 10 with the polysilicon layer 3 is applied to the peripheral power supply line 2. When the polysilicon layer 3 is not used for voltage division, it is left unconnected to anything. In FIG. 1, the external pad (external power supply terminal) 1
5V is supplied to 0 and the ground potential GND is applied to the external pad 11.
Is supplied.

Next, the region of the first circulating power supply wiring 1 or the second circulating power supply wiring 2 will be described with reference to FIG. An internal circuit block group including a semiconductor element group is arranged on a semiconductor substrate, a first circulating power supply wiring 1 is arranged outside the internal block group, and a second circulating power supply wiring is arranged outside the first circulating power supply wiring 1. 2 is placed. In the region of the first circulating power supply wiring 1 or the second circulating power supply wiring 2, the polysilicon layer 3 is formed.
The starting point of the polysilicon layer 3 is connected to the first circulating power supply wiring 1, the middle portion of the polysilicon layer 3 is connected to the second circulating power supply wiring 2, and the end point of the polysilicon layer 3 is It has a structure connected to the external power supply lead-out wiring 7.

FIG. 3A shows an example in which the polysilicon layer 3 is used. The external power supply 7 is supplied with 5V, and the second circuit power supply wiring 2 is divided into 3V by resistance division by the polysilicon layer 3. Here is an example. The ground potential GND is applied to the first circuit power supply line 1. FIG. 3B is an example in which the polysilicon layer 3 is not used for voltage resistance division, and is supplied to the external power supply lead 7 at 5V.
The peripheral power supply wiring 2 of 5 is connected to the external power supply drawer 7 and
V and keep the ground potential GN on the first circulating power supply wiring 1.
D is given. FIG. 3C shows the polysilicon layer 3
In the example in which the external power supply is not connected, the usage is as shown in this figure (c). As described above, according to the present invention, by disposing the polysilicon layer 3 in the region of the first peripheral power supply wiring 1 or the second peripheral power supply wiring 2, it is only necessary to change the artwork pattern in the metallization process after the contact. The power supply voltage supplied to all the internal blocks can be easily switched with a small area.

FIG. 4 is an enlarged view showing a revolving power source region according to another embodiment of the present invention. In the embodiments of FIGS. 1 and 3, the directions of the peripheral power supply wirings 1 and 2 and the direction of the polysilicon layer 3 are the same, but in the present embodiment, the direction of the peripheral power supply wirings 1 and 2 is the direction of the polysilicon layer 3. It is configured to be at a right angle. In the present embodiment, it is possible to form the position where the second circuit power supply line 2 and the polysilicon layer 3 are connected in a wide range, and it is possible to change the voltage of the second circuit power supply line 2 in a wider voltage range. it can.

Further, when the circulating power supply wirings 1 and 2 use the upper layer of the aluminum multi-layer wiring, the wiring of the lower layer of aluminum is used on the polysilicon layer 3 for connection with the polysilicon. Since the upper-layer aluminum wiring used for the circulating power supply wirings 1 and 2 and the lower-layer aluminum wiring on the polysilicon layer form a right angle, the lower-layer aluminum signal wiring can penetrate through the area, and wiring efficiency can be improved. It also has the advantage that

[0013]

As described above, according to the present invention, by arranging the polysilicon layer in the region of the first circulating power wiring or the second circulating power wiring, the pattern of the metallization process after the contact is formed. Only by changing the power supply voltage, it is possible to easily switch the power supply voltage supplied to all the internal circuit blocks with a small area. That is, there is an effect that the power supply voltage supplied to the macro power supply can be changed by changing the processes after the contact by using the same layout as before the contact process. Further, as can be seen from the comparison between the conventional example of FIG. 2 and the embodiment of FIG. 1, the number of output terminals and the number of chips can be reduced by dividing the voltage by resistance division of the polysilicon layer connected to the output terminals. The number of external terminals can be reduced.
Further, by shifting the position of the second circulating power supply wiring to which the polysilicon layer is connected, the voltage of the second circulating power supply wiring can be easily changed in fine steps.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit having power supply wiring according to an embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor integrated circuit having a conventional power supply wiring.

3 (a) to 3 (c) are enlarged plan views showing various relationships between a peripheral power supply line and a polysilicon layer used in one embodiment of the present invention.

4 (a) to 4 (c) are enlarged plan views showing various relationships between a peripheral power supply line and a polysilicon layer used in another embodiment of the present invention.

[Explanation of symbols]

 1, 2, 8, 9 Circular power supply wiring 3 Polysilicon layer 4, 5, 6 Contact section 7 Power supply wiring 10, 11, 12 External pad

Claims (1)

[Claims] 1. An internal block group including a semiconductor element group is arranged on a semiconductor chip, and a first block is provided outside the internal block group.
And a second circulating power source wiring is disposed outside the first circulating power source wiring, and a polysilicon layer is provided in the region of the first circulating power source wiring or the second circulating power source wiring. The starting point of the polysilicon layer is connected to the first circulating power supply wiring, an intermediate portion of the polysilicon layer is connected to the second circulating power supply wiring, and the end of the polysilicon layer is a chip. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to a wiring of a power supply supplied from the outside.