JPH05235209A - Ic package mounting structure - Google Patents
Ic package mounting structureInfo
- Publication number
- JPH05235209A JPH05235209A JP7284492A JP7284492A JPH05235209A JP H05235209 A JPH05235209 A JP H05235209A JP 7284492 A JP7284492 A JP 7284492A JP 7284492 A JP7284492 A JP 7284492A JP H05235209 A JPH05235209 A JP H05235209A
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead
- mounting structure
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣパッケージをプリ
ント基板に実装するＩＣパッケージの実装構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC package mounting structure for mounting an IC package on a printed circuit board.
【０００２】[0002]
【従来の技術】従来の実装構造の対象となるＩＣパッケ
ージ１は図６に示すように、リードフレーム２に搭載さ
れた半導体チップ３が封止樹脂４により被覆され、半導
体チップ２にボンディングワイヤ５を介して接続された
リード６が外部に列状に配列してあった。2. Description of the Related Art As shown in FIG. 6, an IC package 1 to which a conventional mounting structure is applied has a semiconductor chip 3 mounted on a lead frame 2 covered with a sealing resin 4 and a bonding wire 5 attached to the semiconductor chip 2. The leads 6 connected to each other were arranged in a row outside.
【０００３】この種のＩＣパッケージ１をプリント基板
７に実装するには、リード６をプリント基板７に半田付
け８して行っていた。その際、ＩＣパッケージ１はリー
ド６を中心にして左右に倒れる虞れがある不安定な姿勢
で半田付けされるため、従来は、リード６の下端に横方
向に張り出した折曲部６ａを設け、折曲部６ａを半田付
けする構造が採られていた。To mount the IC package 1 of this type on the printed board 7, the leads 6 are soldered 8 to the printed board 7. At that time, since the IC package 1 is soldered in an unstable posture in which there is a risk of tilting left and right around the lead 6, conventionally, a bent portion 6a that extends laterally is provided at the lower end of the lead 6. The structure in which the bent portion 6a is soldered is adopted.
【０００４】[0004]
【発明が解決しようとする課題】この従来の実装方法に
おいては、ＩＣパッケージ１の実装状態を安定させるた
め、リード６に折曲部６ａを設けているため、この折曲
部６ａが電気的な容量（寄生容量）として作用する。In this conventional mounting method, since the bent portion 6a is provided on the lead 6 in order to stabilize the mounted state of the IC package 1, the bent portion 6a is electrically connected. It acts as a capacitance (parasitic capacitance).
【０００５】この寄生容量が存在するため、半導体チッ
プをドライブする能力を上げなければならず、また高速
動作を必要とするシステムには、非常に不利になる。従
って、システム構成上、この容量を低減させることは重
要な課題のひとつである。Due to the existence of this parasitic capacitance, the ability to drive the semiconductor chip must be improved, and it is very disadvantageous for a system which requires high speed operation. Therefore, in terms of system configuration, reducing this capacity is an important issue.
【０００６】本発明の目的は、リードに折曲部を設ける
ことなく、ＩＣパッケージの実装状態を安定させ、しか
も寄生容量を低減したＩＣパッケージの実装構造を提供
することにある。An object of the present invention is to provide an IC package mounting structure that stabilizes the mounting state of the IC package and does not reduce the parasitic capacitance without providing bent portions on the leads.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係るＩＣパッケージの実装構造は、ＩＣパ
ッケージに列状に設けたリードをプリント基板に半田付
けして該ＩＣパッケージをプリント基板に実装するＩＣ
パッケージ実装構造であって、前記ＩＣパッケージは、
該ＩＣパッケージを支持して前記リードをプリント基板
に突き当てた状態に保持する足部を有するものである。In order to achieve the above object, a mounting structure of an IC package according to the present invention is configured such that leads arranged in a row in the IC package are soldered to a printed circuit board to mount the IC package on the printed circuit board. IC to be mounted on
A package mounting structure, wherein the IC package is
It has a foot portion that supports the IC package and holds the lead in a state of abutting against the printed circuit board.
【０００８】また、本発明に係るＩＣパッケージの実装
構造は、ＩＣパッケージに列状に設けたリードをプリン
ト基板に半田付けして該ＩＣパッケージをプリント基板
に実装するＩＣパッケージ実装構造であって、前記ＩＣ
パッケージは、内部に複数の半導体チップを並列に配置
して有し、前記複数の半導体チップに備えたリード列
は、並列に配列してパッケージ外に設けたものである。The IC package mounting structure according to the present invention is an IC package mounting structure in which leads arranged in rows in the IC package are soldered to a printed circuit board to mount the IC package on the printed circuit board. The IC
The package has a plurality of semiconductor chips arranged in parallel inside, and the lead rows provided in the plurality of semiconductor chips are arranged in parallel and provided outside the package.
【０００９】また、本発明に係るＩＣパッケージの実装
構造は、ＩＣパッケージに列状に設けたリードをプリン
ト基板に半田付けして該ＩＣパッケージをプリント基板
に実装するＩＣパッケージ実装構造であって、複数のＩ
Ｃパッケージを有し、該複数のＩＣパッケージは、各Ｉ
Ｃパッケージに備えたリード列を並列に配列した状態に
結束したものである。An IC package mounting structure according to the present invention is an IC package mounting structure in which leads arranged in a row on the IC package are soldered to a printed board to mount the IC package on the printed board. Multiple I
C package, and the plurality of IC packages are
The lead rows provided in the C package are bound together in a parallel array.
【００１０】また、前記複数のＩＣパッケージを結束す
る結束体は、放熱機能を有するものである。Further, the binding body for binding the plurality of IC packages has a heat radiation function.
【００１１】また、前記結束体は、ＩＣパッケージに対
する広い接触面積をもつ放熱面を有するものである。Further, the bundling body has a heat radiating surface having a wide contact area with the IC package.
【００１２】[0012]
【作用】ＩＣパッケージの形状変更或いはＩＣパッケー
ジの配列に工夫を凝らすことにより、寄生容量を増大す
ることなく、ＩＣパッケージの実装状態を安定させる。By changing the shape of the IC package or devising the arrangement of the IC package, the mounting state of the IC package is stabilized without increasing the parasitic capacitance.
【００１３】[0013]
【実施例】以下、本発明の実施例を図により説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】（実施例１）図１（Ａ）は、本発明の実施
例１を示す断面図、（Ｂ）は同斜視図である。(Embodiment 1) FIG. 1A is a sectional view showing Embodiment 1 of the present invention, and FIG. 1B is a perspective view thereof.
【００１５】図１において、本実施例に係るＩＣパッケ
ージの実装構造は、ＩＣパッケージ１の封止樹脂４に、
列状のリード６の両端に位置し、かつＩＣパッケージ１
を支持してリード６をプリント基板７に突き当てた状態
に保持する足部１ａ，１ａを設けてある。In FIG. 1, the mounting structure of the IC package according to the present embodiment is such that the sealing resin 4 of the IC package 1 is
The IC packages 1 are located at both ends of the leads 6 arranged in a row.
Foot portions 1a, 1a for supporting the lead 6 and holding the lead 6 in contact with the printed circuit board 7 are provided.
【００１６】この場合、ＩＣパッケージ１の各リード６
は、直線状に成形されている。In this case, each lead 6 of the IC package 1
Is shaped in a straight line.
【００１７】ＩＣパッケージ１をプリント基板７に実装
するにあたっては、ＩＣパッケージ１の足部１ａ，１ａ
にてＩＣパッケージ１をプリント基板７上に支持し、リ
ード６をプリント基板７に突き当てる。When mounting the IC package 1 on the printed circuit board 7, the legs 1a, 1a of the IC package 1 are mounted.
The IC package 1 is supported on the printed circuit board 7 and the leads 6 are abutted against the printed circuit board 7.
【００１８】この状態で、リード６の直線状下端をプリ
ント基板７に半田付け８する。In this state, the linear lower ends of the leads 6 are soldered 8 to the printed board 7.
【００１９】本実施例によれば、ＩＣパッケージ１をプ
リント基板７上に支持する足部１ａ，１ａが存在するた
め、ＩＣパッケージ１が左右に倒れることがなく、ＩＣ
パッケージの実装状態を安定させることが可能となる。According to this embodiment, since the legs 1a, 1a for supporting the IC package 1 on the printed circuit board 7 are present, the IC package 1 does not fall to the left and right, and the IC
It is possible to stabilize the package mounting state.
【００２０】したがって、従来のようにリード６に寄生
容量の原因となる折曲部を設ける必要がなく、リードを
直線状に成形して寄生容量分をなくすことができる。Therefore, unlike the prior art, it is not necessary to provide the lead 6 with a bent portion that causes a parasitic capacitance, and the lead can be molded linearly to eliminate the parasitic capacitance.
【００２１】（実施例２）図２は、本発明の実施例２を
示す断面図である。(Embodiment 2) FIG. 2 is a sectional view showing Embodiment 2 of the present invention.
【００２２】本実施例は、ＩＣパッケージ１の封止樹脂
４内に複数の半導体チップ３を左右方向に並列に配置し
て設け、各半導体チップ３に備えたリード６列を左右方
向に並列に配列したものである。In this embodiment, a plurality of semiconductor chips 3 are arranged in parallel in the left-right direction within the sealing resin 4 of the IC package 1, and the rows of leads 6 provided in each semiconductor chip 3 are arranged in parallel in the left-right direction. It is arranged.
【００２３】本実施例によれば、複数のリード６列が左
右方向に配列されるため、このリード列によりＩＣパッ
ケージ１が支持されることとなり、ＩＣパッケージの実
装状態が安定する。According to the present embodiment, the plurality of rows of leads 6 are arranged in the left-right direction, so that the IC package 1 is supported by the lead rows, and the mounting state of the IC package is stabilized.
【００２４】さらに、折曲部がリードに不要となり、寄
生容量を低減できる。Further, the bent portion is not required for the lead, and the parasitic capacitance can be reduced.
【００２５】（実施例３）図３は、本発明の実施例３を
示す断面図である。(Embodiment 3) FIG. 3 is a sectional view showing Embodiment 3 of the present invention.
【００２６】本実施例では、複数のＩＣパッケージ１
を、各ＩＣパッケージ１に備えたリード６列を並列に配
列した状態にホルダ９にて結束したものである。In this embodiment, a plurality of IC packages 1
Is bound by a holder 9 in a state in which 6 rows of leads provided in each IC package 1 are arranged in parallel.
【００２７】この場合、ＩＣパッケージの個数は任意の
ものでよく、その組合せ状態は、ＩＣパッケージの実装
状態が安定する形態であれば、任意の形態でよい。In this case, the number of IC packages may be arbitrary, and the combination state may be any form as long as the mounting state of the IC packages is stable.
【００２８】本実施例は、前実施例と同様な効果が得ら
れる。In this embodiment, the same effect as the previous embodiment can be obtained.
【００２９】（実施例４）図４は、本発明の実施例４を
示す断面図である。(Embodiment 4) FIG. 4 is a sectional view showing Embodiment 4 of the present invention.
【００３０】本実施例は、実施例３に示すホルダ９にフ
ィン９ａを設け、ＩＣパッケージ１からの熱を放熱する
機能を付加したものである。In this embodiment, the holder 9 shown in the third embodiment is provided with fins 9a to add a function of radiating heat from the IC package 1.
【００３１】本実施例は、前実施例の効果に加えて、放
熱作用を行うことができる。In this embodiment, in addition to the effect of the previous embodiment, it is possible to perform a heat dissipation action.
【００３２】（実施例５）図５は、本発明の実施例５を
示す断面図である。(Embodiment 5) FIG. 5 is a sectional view showing Embodiment 5 of the present invention.
【００３３】本実施例は、実施例４に示したホルダ９を
ＩＣパッケージ１の上面及び側面に接触させ、ホルダ９
とＩＣパッケージ１との接触面積を拡大したものであ
る。In this embodiment, the holder 9 shown in the fourth embodiment is brought into contact with the upper surface and the side surface of the IC package 1 and the holder 9
The contact area between the IC package 1 and the IC package 1 is enlarged.
【００３４】本実施例によれば、前実施例の効果が得ら
れることに加えて、放熱効率を向上できるという点を有
する。According to this embodiment, in addition to the effect of the previous embodiment, the heat radiation efficiency can be improved.
【００３５】[0035]
【発明の効果】以上説明したように本発明によれば、Ｉ
Ｃパッケージに支持用の足部を設ける、或いはＩＣパッ
ケージに備えたリード列の組合せを選定することによ
り、ＩＣパッケージの実装状態を安定させることがで
き、しかもリードに寄生容量の原因となる折曲部を設け
る必要がない。As described above, according to the present invention, I
By providing a supporting leg in the C package or selecting a combination of lead rows provided in the IC package, it is possible to stabilize the mounting state of the IC package, and moreover, to bend the leads causing parasitic capacitance. There is no need to provide a section.
【００３６】さらに、複数のＩＣパッケージを結束させ
る結束体に放熱機能をもたせることにより、ＩＣパッケ
ージを結束させたことによる熱影響を除去することがで
きる。さらに、結束体とＩＣパッケージとの接触面積を
増大することにより、より放熱効率を向上できる。Furthermore, by providing the bundle for binding a plurality of IC packages with a heat radiation function, it is possible to eliminate the heat effect due to the binding of the IC packages. Further, the heat dissipation efficiency can be further improved by increasing the contact area between the binding body and the IC package.
【図１】（Ａ）は、本発明の実施例１を示す断面図、
（Ｂ）は同斜視図である。FIG. 1A is a sectional view showing a first embodiment of the present invention,
(B) is the same perspective view.
【図２】本発明の実施例２を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図３】本発明の実施例３を示す断面図である。FIG. 3 is a sectional view showing a third embodiment of the present invention.
【図４】本発明の実施例４を示す断面図である。FIG. 4 is a sectional view showing Embodiment 4 of the present invention.
【図５】本発明の実施例５を示す断面図である。FIG. 5 is a cross-sectional view showing a fifth embodiment of the present invention.
【図６】従来例を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional example.
１ ＩＣパッケージ １ａ 足部 ２ リードフレーム ３ 半導体チップ ４ 封止樹脂 ５ ボンディングワイヤ ６ リード ７ プリント基板 ８ 半田付け ９ ホルダ ９ａ フィン 1 IC Package 1a Foot 2 Lead Frame 3 Semiconductor Chip 4 Sealing Resin 5 Bonding Wire 6 Lead 7 Printed Circuit Board 8 Soldering 9 Holder 9a Fin
Claims (5)
プリント基板に半田付けして該ＩＣパッケージをプリン
ト基板に実装するＩＣパッケージ実装構造であって、 前記ＩＣパッケージは、該ＩＣパッケージを支持して前
記リードをプリント基板に突き当てた状態に保持する足
部を有することを特徴とするＩＣパッケージの実装構
造。1. An IC package mounting structure in which leads arranged in a row on an IC package are soldered to a printed circuit board to mount the IC package on the printed circuit board, wherein the IC package supports the IC package. A mounting structure for an IC package, comprising: a foot portion that holds the lead in a state of abutting against the printed circuit board.
プリント基板に半田付けして該ＩＣパッケージをプリン
ト基板に実装するＩＣパッケージ実装構造であって、 前記ＩＣパッケージは、内部に複数の半導体チップを並
列に配置して有し、 前記複数の半導体チップに備えたリード列は、並列に配
列してパッケージ外に設けたことを特徴とするＩＣパッ
ケージの実装構造。2. An IC package mounting structure in which leads arranged in a row on an IC package are soldered to a printed circuit board to mount the IC package on the printed circuit board, wherein the IC package has a plurality of semiconductor chips inside. Are arranged in parallel, and the lead rows provided in the plurality of semiconductor chips are arranged in parallel and provided outside the package.
プリント基板に半田付けして該ＩＣパッケージをプリン
ト基板に実装するＩＣパッケージ実装構造であって、 複数のＩＣパッケージを有し、 該複数のＩＣパッケージは、各ＩＣパッケージに備えた
リード列を並列に配列した状態に結束したものであるこ
とを特徴とするＩＣパッケージの実装構造。3. An IC package mounting structure in which leads arranged in a row on an IC package are soldered to a printed circuit board to mount the IC package on the printed circuit board, the IC package mounting structure having a plurality of IC packages. The IC package is a package structure of an IC package, in which lead rows provided in each IC package are bound together in a parallel array.
構造であって、 前記複数のＩＣパッケージを結束する結束体は、放熱機
能を有することを特徴とするＩＣパッケージの実装構
造。4. The IC package mounting structure according to claim 3, wherein the binding body that binds the plurality of IC packages has a heat dissipation function.
構造であって、 前記結束体は、ＩＣパッケージに対する広い接触面積を
もつ放熱面を有することを特徴とするＩＣパッケージの
実装構造。5. The IC package mounting structure according to claim 4, wherein the binding body has a heat dissipation surface having a wide contact area with the IC package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7284492A JPH05235209A (en) | 1992-02-24 | 1992-02-24 | Ic package mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7284492A JPH05235209A (en) | 1992-02-24 | 1992-02-24 | Ic package mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05235209A true JPH05235209A (en) | 1993-09-10 |
Family
ID=13501108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7284492A Pending JPH05235209A (en) | 1992-02-24 | 1992-02-24 | Ic package mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05235209A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014093411A (en) * | 2012-11-02 | 2014-05-19 | Toshiba Corp | Semiconductor device |
-
1992
- 1992-02-24 JP JP7284492A patent/JPH05235209A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014093411A (en) * | 2012-11-02 | 2014-05-19 | Toshiba Corp | Semiconductor device |
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