JPH05235058A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To increase the sectional area of a gate and to reduce significantly a gate resistance by a method wherein a second gate electrode is patterned by wet etching. CONSTITUTION:An insulating film 12 is formed on the surface of a GaAs substrate 11 and a' first photoresist layer 13 is formed thereon to formed an opening. A thin aluminium layer to form a first gate electrode 15 is deposited from over the opening in the oblige direction. The film 12 is opened using the electrode 15 as a mask and moreover, the surface of the substrate 11 is subjected to recess etching. An aluminium layer to form a second gate electrode 18 is deposited in the vertical direction and this aluminium layer is patterned by a a wet etching method to form the second gate electrode 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a compound semiconductor device capable of reducing the gate resistance by reducing the gate length and greatly increasing the thickness of the gate electrode.

[0002]

2. Description of the Related Art Since gallium arsenide has an electron mobility 4 to 5 times higher than that of silicon, various field effect transistors using gallium arsenide as an active layer are used as high speed and high frequency transistors. As a typical one, a Schottky gate field effect transistor (MESFE
T) and a heterojunction field effect transistor.

Improvement of various characteristics of these transistors is
It is mainly affected by miniaturization of gate length and reduction of gate resistance. However, simply reducing the gate length reduces the gate cross-sectional area and increases the gate resistance, making it difficult to achieve both. Therefore, there is a technique in which the miniaturization of the gate length and the reduction of the gate resistance are made compatible by vapor-depositing the gate electrode in an oblique direction. (For example, Japanese Patent Application No. 2-202024 describes a similar technique.)
This technique will be briefly described with reference to FIG. In FIG. 7, the surface of the active region of the GaAs substrate (1) is covered with the SiN film (2), and ohmic source / drain electrodes made of AuGe / Ni / Au or the like are formed on both sides thereof.
A resist (3) is formed on them. In this state, a first metal layer (4) of Al or the like is obliquely deposited from above the resist (3). Since the first metal layer (4) in the opening of the resist (3) covers only a part of the SiN film (2), the first metal layer (4) is used as a mask for Si.
The N film (2) is removed, and the surface of the substrate (1) is recess-etched.

After that, the gate electrode (5) is vertically vapor-deposited and the resist (3) is lifted off.

[0005]

However, since the above-mentioned method is a lift-off method in which the patterning of the gate electrode (5) utilizes the film thickness of the resist (3), the film thickness of the resist film or more must be formed. However, there is a drawback that there is a limit in reducing the gate resistance.

[0006]

The present invention has been made in view of the above-mentioned conventional problems, and provides a method of manufacturing a compound semiconductor device, which is suitable for mass production and at the same time can further increase the cross-sectional area of the gate electrode. Forming an opening (14) in the first photoresist layer (13), depositing a first gate electrode layer (15) from an oblique direction, and forming the opening (1)
4) a step of recess etching the surface of the active region which is not covered with the first gate electrode (15) and a second thick surface
The step of forming the gate electrode layer (16) of the first photoresist layer (1) and the second photoresist layer (17).
3) until the first and second gate electrode layers (15) are exposed
It comprises a step of selectively etching (18) and a step of removing the first and second photoresist layers (13) and (17).

[0007]

According to the invention, the second gate metal layer (18)
Since it can be performed by a normal photo-etching technique, the film thickness is not limited as in the conventional lift-off method, and therefore the film thickness can be significantly increased. Moreover, the substantial gate length can be reduced by recess etching using oblique deposition.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 to 6 are sectional views showing the manufacturing method of the present invention in the order of steps. Semi-insulating GaAs substrate (1
The surface of 1) is n-GaAs / n ⁺ -G by stacking by epitaxial growth or diffusion by ion implantation.
It has an aAs structure, the n-GaAs layer is the active layer,
^{The +} -GaAs layer becomes the source / drain region. If the device is a heterojunction FET, the surface of the GaAs substrate (11) is undoped GaAs / n-AlGaAs / n ⁺ G
It has an aAs structure. An ohmic electrode made of AuGe / Ni / Au is formed on the surface of the n ⁺ -GaAs.

First, referring to FIG. 1, a GaAs substrate (1
Plasma nitride film (S
ixNy) is formed on the insulating film (12) having a thickness of about 0.1 μ, and the first photoresist layer (13) made of a positive type resist is spin-on coated thereon with a thickness of about 0.5 μ, and a normal lithography technique is used. Insulating film by (12)
An opening (14) having a width of about 0.8 μ is formed to expose the surface of the.

Referring to FIG. 2, the wafer is set to be inclined with respect to the vapor deposition source, and 0.1 μm of aluminum is deposited from above the opening (14) to form the first gate electrode (15). The angle is 60 to 70 ° with respect to the horizontal plane of the wafer, and the direction is toward the source electrode. As a result, a portion of the first resist layer (13) not covered with the first gate electrode (15) is formed in the opening (14) due to the film thickness of the first resist layer (13).
The line width of the non-deposited portion is determined by the first resist layer (13).
Depending on the film thickness and the deposition angle. With the combination of the film thickness of 0.5 μ and 60 to 70 °, the line width of the non-deposited portion is about 0.25 μ.

Referring to FIG. 3, the deposited first gate electrode.
Open the insulating film (12) using the pole (15) as one mask
Then, using the opened insulating film (12) as a mask, the substrate (1
1) Recess etching the surface. In the opening of the insulating film (12)
Is CF_FourRIE using, water-soluble phosphoric acid for recess etching
Use each liquid. In addition, the recess etching of this step is the same as the above n.
⁺Through the -GaAs layer to expose the n-GaAs active layer
Do it to the depth that it comes out.

Referring to FIG. 4, a 1.0 μ thick aluminum layer (16) is now deposited vertically. The aluminum layer (16) buries the opening (14), and has a Schottky contact with the GaAs surface at the recess etched portion with a line width corresponding to the line width of the insulating film (12). Therefore, the line width of the insulating film (12) becomes the effective gate length. Referring to FIG. 5, a negative resist is applied on the aluminum layer (16), exposed and developed to form a second photoresist layer (17), and the second photoresist layer (17) is used as a mask to form the aluminum layer. By selectively etching (16), a second gate electrode (17) having a line width of about 1.0 μ is formed. In this step, a wet method is used to remove the aluminum layer (16) and at the same time, to remove the first gate electrode (15).
The aluminum layer forming the is also removed to expose the surface of the first photoresist layer (13).

Referring to FIG. 6, by removing the first and second photoresist layers (13) and (17), the first gate electrode (15) and the second gate electrode (18) are laminated. The gate structure consisting of the structure is completed. According to the manufacturing method of the present application, since the opening of the insulating film (12) is formed using the first gate electrode (15) obliquely deposited as a mask, the opening of submicron or less can be easily formed. The line width of the opening of the insulating film (12) is substantially equal to that of the second gate electrode (1
Since the gate length is 8), a miniaturized gate length can be realized. On the other hand, since the gate electrode can be formed with a line width thicker than the effective gate length, the gate cross-sectional area can be increased. Moreover, since the second gate electrode (18) can be patterned by the wet etching method, the film thickness can be greatly increased without being restricted by the resist film thickness unlike the lift-off method. Therefore, the gate cross-sectional area can be further increased and the gate resistance can be greatly reduced. Furthermore, since it is not necessary to use a high melting point low resistance material such as Ti as the gate electrode, the process can be simplified.

[0014]

As described above, according to the present invention, a fine gate length can be obtained by utilizing oblique deposition, and at the same time, the thickness of the second gate electrode (18) can be arbitrarily increased. Therefore, there is an advantage that the gate cross-sectional area can be increased and the gate resistance can be significantly reduced. As a result, it is possible to provide a high-performance element in which the minimum noise figure NF is significantly improved.

Further, since the second gate electrode (18) has a single-layer structure of aluminum, the process of the present invention can be carried out only by a simple wet etching process, so that the process can be simplified.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 2 is a second cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a third sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a fourth sectional view for explaining the manufacturing method of the present invention.

FIG. 5 is a fifth cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 6 is a sixth sectional view for explaining the manufacturing method of the present invention.

FIG. 7 is a cross-sectional view for explaining a conventional manufacturing method.

Claims (2)

[Claims] 1. A method of manufacturing a compound semiconductor device, wherein a gate electrode is formed on an active region of a semi-insulating substrate, wherein a step of covering a surface of the active region with an insulating film, and an opening above the active region are provided. A step of forming a first photoresist layer; a step of obliquely depositing an electrode layer serving as a mask from above the first photoresist layer to cover a part of the insulating film in the opening; Removing the insulating film exposed in the opening by using the electrode layer as a selective mask, and further recess etching the surface of the semi-insulating substrate exposed by removing the insulating film; and the electrode serving as the mask Forming a second gate electrode layer on the layer in contact with the recess-etched substrate surface; and forming a second photoresist layer on the second gate electrode layer, A step of removing the masking electrode layer and the second gate electrode layer so as to leave the second gate electrode layer filling the opening, and a step of removing the first and second photoresist layers. A method of manufacturing a compound semiconductor device, comprising: 2. The method of manufacturing a compound semiconductor device according to claim 1, wherein the second gate electrode layer is aluminum.