JPH05234393A - Analysis device for memory defect - Google Patents

Abstract

PURPOSE:To shorten the relief judgment time of the title apparatus as far as possible by a method wherein pieces of information on defects of cells in individual divided regions are read out in synchronization by means of corre sponding judgment means and it is judged whether they are defective of not. CONSTITUTION:A region in which pieces of information on defects in a defect analysis memory 7 have been written is divided into a plurality of regions. After that, a retrieval start signal is sent to a control circuit 5i from a CPU 1; the pieces of information on the defects in cells from a start address up to a finish address in the corresponding divided regions are read out, and it is judged whether they are defective or not. Addresses which have been judged to be defective are stored in defective address storage registers 13Ai, 13Bi. Row addresses and column addresses in the defective cells in the corresponding divided regions are counted by means of defect number counters 11Ai, 11Bi. Whether the direction of the cells to be relieved on the basis of the counters 11Ai, 11B1 as well as on the basis of the number of redundancy columns and redundancy rows in a redundancy circuit is the row direction or the column direction is decided by the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory failure analysis device for analyzing whether or not a memory under test having a redundant circuit is defective, or whether or not it can be repaired by the redundant circuit.

[0002]

2. Description of the Related Art Generally, a memory failure analysis device analyzes the quality of individual memory cells of a memory under test having a redundant circuit to determine whether or not a defective memory cell can be relieved by the redundant circuit. It is a thing. This memory failure analysis device includes an algorithmic pattern generator (hereinafter also referred to as ALPG), a comparator, and a failure analysis memory (hereinafter also referred to as FAM). First, an address signal and a test data signal are sent from the ALPG to a memory under test (hereinafter, also referred to as DUT) having a redundant circuit, and after writing data in a memory cell of the DUT corresponding to the address signal, Read out. Then, the written data and the read data are compared by the comparator, and if they are different, a defective signal is sent to the FAM. This FAM has a memory area of the same size as the memory cell array of the DUT, and each memory cell of the FAM is assigned the same address as the memory cell corresponding to the DUT. Then, when the defective signal is sent from the comparator, the data "1" is written in the corresponding memory element. The FAM memory cell is initialized in advance so that the data of "0" is stored before performing the analysis process.

In this way, based on the address signal and the data signal from the ALPG, it is analyzed whether or not all the memory cells of the DUT are defective, and if it is defective, FA
Data "1" is written in the corresponding memory cell of M. Then, based on the data written in this FAM, it is determined whether the DUT can be repaired by the redundant circuit.

The determination as to whether or not repair is possible will be described for the case where the defect information of two DUT1 and DUT2 having defective cells is written in the FAM as shown in FIG.
Below, the row (X) address is X _i and the column (Y) address is Y
the address of the memory cell is a _j represents the (X _i, Y _j). Now, in the FAM shown in FIG. 8, the address is (X
It is assumed that defective data “1” is written in the cells, which are ₂ , Y ₅ ), (X ₃ , Y ₅ ), and (X ₅ , Y ₅ ). That is, the FAM address is (X ₂ , Y ₅ ),
The memory cell of DUT1 corresponding to the cell of (X ₃ , Y ₅ ) is defective, and the memory cell of DUT 2 corresponding to the cell of FAM address (X ₅ , Y ₅ ) is defective.

The process of determining whether or not the repair is possible is as follows.
The FAM area corresponding to UT1 is performed, and then the FAM area corresponding to DUT2 is performed. DU
For T1, from the cell of address (X ₁ , Y ₁ ) to X
Direction, that is, the address is (X ₂ , Y ₁ ), (X ₃ ,
It is searched whether or not each cell is defective in the order of Y ₁ ), (X ₁ , Y ₂ ), and (X ₂ , Y ₂ ). Then, it is detected that the cell at the 14th address from the address (X ₁ , Y ₁ ), that is, the cell having the address (X ₂ , Y ₅ ) is defective. Then, cells in the X direction, that is, addresses (X ₁ , Y ₅ ), (X ₂ , Y ₅ ), and (X ₃ ,
It is sequentially detected whether or not the cell of Y ₅ ) is defective. Then, the cells in the Y direction, ie (X ₂ , Y ₁ ),
(X ₂ , Y ₂ ), (X ₂ , Y ₃ ), (X ₂ , Y ₄ ),
It is detected whether or not the cells of (X ₂ , Y ₅ ) and (X ₂ , Y ₆ ) are defective. The address operation required for this defect detection is 9 (= 3 + 6) times.

Next, based on the detection result, in the masking direction, that is, to replace the redundant circuit, cells in the row direction (X direction) or cells in the column direction (Y direction) are replaced. Decide what to do. In the case of the DUT 1 shown in FIG. 8, the number of defects in the row direction is 2 and the number of defects in the column direction is 1.
Since the number of cells is one, the cells in the row direction are masked. After that, it is sequentially searched from the cell having the address (X ₃ , Y ₅ ) whether each cell is defective as described above. The cell having the address (X ₃ , Y ₅ ) is regarded as a good cell because it is masked. And the address is (X ₃ , Y ₆ )
When the search up to the cell is completed, the defect search of DUT1 is completed. Since the address operation from the cell having the address (X ₃ , Y ₅ ) to the cell having the address (X ₃ , Y ₆ ) is performed four times, 14 + 9 + 4 = 27 address operations are required for the defect search of the DUT 1.

Next, similar to the DUT1, a defect search for the DUT2 is performed. That is, if the address is (X ₄ , Y
Defects are sequentially searched from the cell in ₁ ) in the X direction, defects are detected after 14 address operations, defects in the X and Y directions are detected, and the masking direction is determined. This X direction,
Further, 9 (= 3 + 6) address operations are required to detect defects in the Y direction. Then, again, the address is (X ₆ ,
The defect search is performed sequentially from the cell of Y ₅ ). The address operation required for the defect search from the cell having the address (X ₆ , Y ₅ ) to the cell having the address (X ₆ , Y ₆ ) is four times. As a result, 27 (= 14) for the DUT2 defect search.
+ 9 + 4) address operations are required. Therefore, since the defect search of DUT1 and DUT2 is serially processed, 54 (= 27 + 27) address operations are required.

On the other hand, when the defect information of the DUT 3 having a defective cell is written as shown in FIG. 9, the defect search is performed with the address (X ₁ , Y ₁ ) as described above.
From the cell in the X direction sequentially, and after 26 address operations,
Defects are detected, defects in the X and Y directions are detected, and the masking direction is determined. In the case shown in FIG. 9, since the number of defects in the row direction is 3 and the number of defects in the column direction is 1,
Mask cells in the row direction.

There are 12 for detecting defects in the X and Y directions.
(= 6 + 6) address operations are required. afterwards,
A defect search is performed sequentially from the cell whose address is (X ₃ , Y ₅ ). The address operation required for the defect search from the cell having the address (X ₃ , Y ₅ ) to the cell having the address (X ₆ , Y ₆ ) is 10 times. Therefore, 48 (= 26 + 12 + 10) address operations are required for defect search of the DUT 3.

[0010]

As described above, in the conventional memory failure analysis apparatus, the failure analysis memory (FA
Since M) is used for serial processing, there is a problem that the defect search and repair determination time increases with the increase in the capacity of semiconductor devices and the increase in the number of simultaneous device measurements. This leads to a reduction in the through top of the semiconductor test apparatus itself, which in turn leads to an increase in device cost due to an increase in test cost. In addition, recently, an analysis apparatus for processing in parallel, which is provided with a plurality of FAMs, each of which has an independent processor, and which processes in parallel, has a problem that the price of the analysis apparatus itself increases. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory failure analysis apparatus capable of shortening the repair determination time as much as possible.

[0011]

A memory failure analysis apparatus according to the present invention comprises a failure analysis memory in which failure information of each cell of a memory under test is written and a failure analysis memory in which failure information is written. Dividing means for dividing the area into a plurality of divided areas; start / end address calculating means for calculating a start address and an end address for defect search of each divided area;
A start address storage register for storing the start address of each divided area, an end address storage register for storing the end address of each divided area, a start signal generating means for generating a search start signal for defect search, and each of the divided areas. Are provided in correspondence with each other, and each operates in conjunction with each other based on the search start signal, and the defective information of the cells in the corresponding divided area from the start address to the end address is read based on a predetermined rule to make the cell defective. A plurality of determining means for determining whether or not, and a plurality of defective address storage means each provided corresponding to the divided area, for storing the address of the cell determined to be defective in the corresponding divided area, Each of them is provided corresponding to a divided area, and a plurality of cells for counting the number of defective cells in the row address direction and the column address direction of defective cells in the corresponding divided area are provided. Whether the direction of the cell to be relieved is the row direction based on the number counting means, the address of the defective cell stored in the defective address storage means, the output of the defective number counting means, and the number of redundant columns and redundant rows of the redundant circuit. Or a deciding means for deciding whether it is in the column direction.

[0012]

According to the memory failure analysis apparatus of the present invention having such a configuration, the failure information of the cells in each divided area is synchronously read by the corresponding determination means to determine whether or not there is a failure. As a result, the relief determination time can be shortened as much as possible.

[0013]

1 shows the configuration of a first embodiment of a memory failure analysis device according to the present invention. The memory failure analysis apparatus according to this embodiment includes a CPU 1 and a start address storage register 3.
_Ai , 3B _i (i = 1, ...) And end address storage registers 4A _i , 4B _i (i = 1, ...) And control circuit 5
_i (i = 1, ...), a failure analysis memory (hereinafter also referred to as FAM) 7, and defect counts 11A _i , 11B _i (i
= 1, ...) and the defective address storage register 13A _i , 1
3B _i (i = 1, ...).

Now, there are two DUT1 and DUT2 in FAM7.
It is assumed that the defect information of is written in the FAM 7 as shown in FIG. The CPU 1 equally divides the area in which the defect information of the FAM 7 is written into a plurality of (four in this embodiment) divided areas FM _i (i = 1, ... 4) (FIG. 4).
), The start address and the end address of FM _i of each divided area are calculated, and each start address storage register 3 is calculated.
A _i , 3 B _i and end address storage registers 4 A _i , 4
The signal is sent to B _i , and a search start signal is sent to the control circuit 5 _i . The start addresses of the divided areas FM ₁ , FM ₂ , FM ₃ , FM ₄ of FM 7 divided as shown in FIG. 4 are (X ₁ , Y ₁ ), (X ₄ , Y ₁ ), (X ₄ , Y ₁ ) (X
₄ and Y ₄ ) and the end address is (X ₃ ,
Y ₃ ), (X ₆ , Y ₃ ), (X ₃ , Y ₆ ), (X ₆ , Y
₆ )

Start address storage registers (hereinafter, also simply referred to as registers) 3A _i and 3B _i store the X (row) address and the Y (column) address of the start address of the divided area FM _i , respectively. That is, the registers 3A ₁ , 3A ₂ ,
3A _3, the 3A _4, the address _{X 1, X 4, X 1} , X 4
Are respectively stored in the registers 3B ₁ , 3B ₂ , 3B ₃ , 3
Addresses Y ₁ , Y ₁ , Y ₄ , and Y ₄ are stored in B ₄ , respectively. Further, end address storage registers (hereinafter, also simply referred to as registers) 4A _i and 4B _i store the X (row) address and the Y (column) address of the end address of the divided area FM _i , respectively. That is, the registers 4A ₁ , 4A ₂ ,
4A _3, the 4A ₄ stored address _{X 3, X 6, X 3} , X 6 are each register _{4B 1, 4B 2, 4B 3} , 4B
The _four addresses _{Y 3, Y 3, Y 6} , Y 6 are stored respectively.

The control circuit 5 _i operates in synchronization with the CPU
Based on the search start signal from 1, the defect search of the divided area FM _i is started. This defect search is performed based on a predetermined rule described later. Defective number counters (hereinafter, also referred to as counters) 11A _i and 11B _i (i = 1, ... 4) count the number of defective cells in the row direction and the column direction, respectively. Bad address storage register (hereinafter also simply referred to as register)
13A _i and 13B _i store the row address and column address of the defective cell, respectively.

Next, the operation of this embodiment will be described with reference to FIGS. First, the area in which the defect information of the FAM 7 is written is equally divided into four by the CPU 1 (see FIG. 4), and the start and end addresses of each divided area FM _i (i = 1, ... 4) are calculated by the CPU 1. The start address is sent to the registers 3A _i and 3B _i , and the end address is sent to the registers 4A _i and 4B _i to be stored therein (see step F21 in FIG. 2). After that, a search start signal is sent from the CPU 1 to each control circuit 5 _i (i = 1, ... 4) (see step F22 in FIG. 2). Then register 3
A _i, the start address of the divided regions FM _i from 3B _i is a register 4A _i, end address each of the control circuits from 4B _i 5
_It is read by _i (see step F23 in FIG. 2), and the defect search is started using the start address as the search address.
Regarding the search address at this time, the search address of the divided area FM ₁ is (X ₁ , Y ₁ ), that of the divided area FM ₂ is (X ₄ , Y ₁ ), and that of the divided area FM ₃ is (X ₁ ,
Y ₄ ), that of the divided area FM ₄ is (X ₄ , Y ₄ ).

In this defect search, the cell data of the search address is read by the control circuit 5 _i (step F in FIG. 2).
24), and whether it is defective or not is determined (see step F25 in FIG. 2). In each divided area, if the searched cell is not defective, the search address is incremented by 1 (see step F26 in FIG. 2).

Here, the incremented search address of the divided area FM ₁ is (X ₂ , Y ₁ ), and the divided area FM ₂
In its (X _5, Y _1), which is divided areas FM ₃ at (X _2, Y _4), divided area FM ₄ becomes (X _5, Y _4). The search address (X ₃ , Y of the divided area FM _{1
When 1} ) is incremented by 1, the new search address becomes (X ₁ , Y ₂ ). Then, each divided area FM
It is determined by the control circuit 5 _i whether or not the new search address of _i (i = 1, ... 4) exceeds the end address (see step F27 of FIG. 2). It is repeated. Division area F
When the search address of M ₁ becomes (X ₂ , Y ₂ ), that is, when the search address of the divided area FM ₂ is (X ₂ , Y ₅ ), the cells of the divided areas FM ₁ and FM ₂ are not defective,
Since the cells in the divided areas FM ₃ and FM ₄ are defective, the control circuits 5 ₃ and 5 ₄ detect that the cells are defective. Then, the control circuit 5 ₃ and 5 ₄ cause the register 13
A _3, 13B _3, and the register 13A _4, 13B ₄ defective address X _2, Y ₅ and X _5, Y ₅ is stored, respectively (see step F28 in FIG. 2). Each control circuit 5 _i
(I = 1, ... 4) operates in conjunction with each other, but the divided area FM
_Since the corresponding cells of ₁ and FM ₂ are not defective, the registers 13A ₁ and 13B ₁ and the registers 13A ₂ and 13B ₂
No address is stored in.

In this way, the control circuits 5 ₁ , 5 ₂ , 5 ₃ ,
If at least one of the 5 ₄ detects a defect, the CP
Registers 13A _i , 13B _i (i = 1, ...
The defective address is read from (4) (step F2 in FIG. 2).
9), and then, proceeding to step F31 of FIG. 3, the cells corresponding to the search address of each divided area FM _i are sequentially searched for defects in the X and Y directions. That is, the divided regions FM _i for sequentially searching for defects in the X direction and the Y direction.
CPU 1 sets the start address and the end address of the register 3A _i , 3B _i and register 4 respectively.
The data is stored in A _i and 4 B _i (see step F31 in FIG. 3). In the case shown in FIG. 4, the search addresses of the divided areas FM ₁ , FM ₂ , FM ₃ , FM ₄ when the defect is detected are (X ₂ , Y ₂ ), (X ₅ , Y ₂ ), (X ₂ , Y
₅ ) and (X ₅ , Y ₅ ), for example, the divided area FM
When searching ₃ for defects in the order of X direction and Y direction, addresses (X ₁ , Y ₅ ), (X ₂ , Y ₅ ), (X ₃ , Y ₅ ),
(X ₂ , Y ₄ ), (X ₂ , Y ₅ ), and (X ₂ , Y ₆ ) are performed in this order. Therefore, the start address in the X direction of the divided area FM ₃ is (X ₁ , Y ₅ ), the end address is (X ₃ , Y ₅ ), and the start address in the Y direction is (X ₂ , Y ₄ ). , The end address is (X ₂ , Y ₆ )
Becomes It should be noted that the other divided areas FM ₁ , FM ₂ and FM ₄
Start addresses in the X direction are (X ₁ , Y ₂ ), (X
₄ , Y ₂ ) and (X ₄ , Y ₅ ), and the end addresses are (X ₃ , Y ₂ ), (X ₆ , Y ₂ ), and (X ₆ , Y ₅ ), respectively. Similarly FM ₁ , FM ₂ and FM
The start addresses in the Y direction of ₄ are (X ₂ , Y ₁ ), (X ₅ ,
Y ₁₎ and (X _5, Y ₄₎ a and end address are each (X _2, Y _3), a (X _5, Y ₃₎ and (X _5, Y _6).

Next, as in the case described above, the CPU 1 sends a search start signal to each control circuit 5 _i (see step F32 in FIG. 3). Then, the start address and end address of each divided area FM _i are read by each control circuit 5 _i (see step F33). First, each control circuit 5 _i
The search address is set to the X-direction start address of the divided area FM _i . After that, the divided area FM corresponding to the search address
The cell data of _i is read (see step F34), and it is determined whether or not there is a defect (see step F35). If it is not defective, the search address is incremented by 1 (see step F37), and the search address is divided into the divided areas FM.
_The control circuit 5 _i determines whether the end address of _i has been exceeded (step F38). If not exceeded,
Returning to step F34, the above is repeated.

When it is determined in step F35 that there is a defect, the counters 11A _i and 11B _i count up (see step F36). And step F
At 37, the search address is incremented by 1 and the above is repeated. When the search address exceeds the end address in the X direction, the same operation is repeated with the start address in the Y direction as the search address. When the end addresses in the X and Y directions are exceeded, the masking direction is determined by the CPU 1 (see step F39). For example, in the case shown in FIG. 4, the divided area FM
_{Since 1} and FM ₃ are obtained by dividing the measured memory DUT1 and divided regions FM ₂ and FM ₄ are obtained by dividing the measured memory DUT2, a defective cell in the row direction (column address Y ₅ ) of the DUT1. 2 and the number of defective cells in the column direction (row address X ₂ ) is 1, the CPU 1 determines to mask the cells in the row direction. In addition,
As for the memory under test DUT2, since the number of defective cells is 1 in both the row direction and the column direction, either direction can be used for masking.

When the masking direction is determined, the process returns to step F21 shown in FIG. Then, each divided area FM
The start address and end address of _i (i = 1, ... 4) are determined by the CPU 1, and are respectively registered in the registers 3A _i , 3B.
_i and the registers 4A _i and 4B _i are stored (see step F21). The start address at this time is obtained by incrementing 1 to the search address of the cell detected as defective in step F25. That is, the start addresses of the divided areas FM ₁ , FM ₂ , FM ₃ , FM ₄ are (X ₃ , Y ₂ ), (X ₆ , Y ₂ ), (X ₃ ,
Y ₅ ), (X ₆ , Y ₅ ). The end addresses are (X ₃ , Y ₃ ), (X ₆ , Y ₃ ), (X ₃ , Y ₆ ),
(X ₆ , Y ₆ ).

Next, from the CPU 1 to each control circuit 5 _i (i =
When a search start signal is sent to 1, ... 4), each control circuit 5
start address and end address of the divided regions FM _i by _i is read (see step F 23), the failure search starts start address as the search address, continued failure search until the search address exceeds the ending address, if it exceeds Stop the defect search. The address operation necessary for the defect search in the case shown in FIG. 4 is five address operations until detecting that the cell of the address (X ₂ , Y ₅ ) is defective.
Address operation 6 (= 3 +) for defect search in X direction and Y direction
The total is 15 times, which is 3) times and 4 times the address operation of the defect search until the end address after the defect search in the X and Y directions is completed. On the other hand, when the conventional memory failure analysis device performs it, it is 54 times as described in the conventional technique. As a result, by using the device of this embodiment, the number of address operations for defect search can be reduced as much as possible, and the repair determination time can be shortened.

Next, the configuration of the second embodiment of the present invention is shown in FIG. The memory failure analysis apparatus of this embodiment is the same as the memory failure analysis apparatus of the first embodiment except that the coupling means 15A, 15
B, address comparators 17A and 17B, and count 19
A, 19B and defective address registers 21A _j , 21B
_j (j = 1, ...) And the defect count register 22A _j ,
22B _j (j = 1, ...) Is newly provided.
The configurations of these new ones will be described with reference to FIGS. FIG. 7 is a diagram in which the area of the FAM7 in which the defect information of one memory under test DUT3 is written is divided into four.
It is the same as the first embodiment until the control circuits 5 ₃ and 5 ₄ detect a defect when the search address of the divided area FM ₃ is (X ₂ , Y ₅ ). When it is detected as defective, each control circuit 5 _i (i = 1, ... 4) is searched for defects in the row direction by fixing the address as in the first embodiment, and then by fixing the X address and column. Search for defects in the direction. At this time, in the FAM shown in FIG. 7, the Y ₅ address of the divided area FM ₃
Since the Y ₅ address of the divided area FM ₄ is the same Y ₅ address in the DUT 3, it must be regarded as one address.

This is performed by the coupling means 15B. or,
The combining unit 15A determines whether the row address of the cell of a certain divided area and the row address of the row of the cell of another divided area are regarded as the same address in the DUT 3. Further, the minimum column address is determined by the address comparator 17B from the same row address of the cell in which the defect is detected, and the minimum row address is determined by the address comparator 17A from the same column address. The defective address registers 21A _j and 21B _j (j = 1, ...) Store the row address and the column address determined by the address comparators 17A and 17B for each memory under test. Counts 19A and 19B are in row (X) direction and column (Y)
The number of defects in the row and column directions, which are regarded as having the same row address and column address when the defect search in the direction is performed, is counted.
Defect count registers 22A _j , 22B _j (j = 1,
...) stores the count value for each measured memory counted by the counters 19A and 19B.

Next, the operation will be described. Each divided area FM
The defects for each _i (i = 1, ... 4) are counted (see step F61 in FIG. 6). The address comparators 17A and 17B compare the same addresses to determine the minimum address (see step F62 in FIG. 6). Then, the count addition value is stored in the defect count registers 22A _j and 22B _j (see step F63 in FIG. 6).
Then, the CPU 1 reads the count value from the defect count registers 22A _j and 22B _j and determines the masking direction. As in the case of the first embodiment, the address operation required when searching for a defect in the FAM in which the defect information shown in FIG. 7 is written using this second embodiment is 15 times. It is possible to obtain the same effect as that of the embodiment.

[0028]

As described above, the relief determination time can be shortened as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of the first embodiment.

FIG. 3 is a flowchart illustrating the operation of the first embodiment.

FIG. 4 is a schematic diagram in which a defect analysis memory in which defect information of two measured memories is fetched is divided into four.

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a flowchart illustrating the operation of the second embodiment.

FIG. 7 is a schematic diagram in which a defect analysis memory in which defect information of one measured memory is taken is divided into four.

FIG. 8 is a schematic diagram showing a defect analysis memory in which defect information of two measured memories is fetched.

FIG. 9 is a schematic diagram showing a failure analysis memory in which failure information of one measured memory is taken.

[Explanation of symbols]

1 CPU 3A _i , 3B _i (i = 1, ...) Start address storage register 4A _i , 4B _i (i = 1, ...) End address storage register 5 _i (i = 1, ...) Control circuit 7 Failure analysis memory 11A _i , 11B _i (i = 1, ...) Defect number counter 13A _i , 13B _i (i = 1, ...) Defect address storage register

Claims (1)

[Claims] 1. A defect analysis memory in which defect information of each cell of a memory under test is written, and a dividing means for dividing an area of the defect analysis memory in which defect information is written into a plurality of divided areas. A start / end address calculating means for calculating a start address and an end address for defect search of each divided area, a start address storage register for storing the start address of each divided area, and an end address of each divided area And an end address storage register for storing a start address and a start signal generating means for generating a search start signal for a defect search, each of which is provided corresponding to the divided area, and each operates in association with the search start signal. Then, the defect information of the cells in the corresponding divided area from the start address to the end address is read based on a predetermined rule to determine whether the cell is defective. And a plurality of defective address storage units each of which is provided corresponding to the divided area and stores the address of a cell determined to be defective in the corresponding divided area, and each of the divided address storage units. A plurality of defect number counting means provided corresponding to the regions and for counting the number of defective cells in the row address direction and the column address direction of the defective cells in the corresponding divided regions; and the defective cells stored in the defective address storage means. Address, the output of the defective number counting means, and the determining means for determining whether the direction of the cell to be relieved is the row direction or the column direction based on the number of redundant columns and redundant rows of the redundant circuit. A memory failure analysis device characterized by the above.