JP2002202350A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor tester which further improves throughput by especially noting test characteristics of a flash memory. SOLUTION: In the semiconductor tester for simultaneously testing a plurality of flash memories of devices to be tested each with the prescribed number of defective blocks, there are arranged a memory means having the prescribed number of defective blocks previously stored, a counter for accumulate the number of defective blocks per device, and a coincidence detection means which detects coincidence between the accumulated number per device of the counter and the prescribed number of the memory means to output a signal forbidding a test signal to the device involved. The testing is completed sequentially starting from the device with the most of the number of defective blocks and finally, and is ended with the stage where any defective cell is detected in the defective block of the device with the least of the number of defective blocks in terms of the prescribed number of defective blocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus capable of simultaneously testing a plurality of devices under test of a flash memory at a high speed.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, an outline of the semiconductor test apparatus will be described with reference to a block diagram shown in FIG. The main part of the semiconductor test apparatus comprises a main frame 20 including a timing generator 4, a pattern generator 5, a waveform shaper 6, a logic comparator 7, and a fail memory unit 8, a driver DR, a comparator Test head 30 with CP
Is composed. However, the semiconductor test apparatus simultaneously tests the DUTs 91 of a plurality of devices under test, but only one is shown for simplicity of the drawing, and there are a large number of drivers DR and comparators CP corresponding to each pin of the DUT 91. There is a simplified display.

In the main frame 20, a pattern generator 5 generates logical data in synchronization with a basic clock signal output from the timing generator 4.

The waveform shaper 6 uses the logic data from the pattern generator 5 and the clock signal from the timing generator 4 to generate a test data signal, an address signal, and a control signal (/ W).
E, / RE, / CE) and outputs a signal to the test head 30.

In the driver DR of the test head 30, a test signal is set to a predetermined logic voltage and applied to an input pin of the DUT 91.

The output signal from the output pin of the DUT 91 is
After comparing the voltages with the comparison voltage of the comparator CP, the voltage is output to the logic comparator 7 of the main frame 20 as a logic signal.

The logical comparator 7 compares the logical output signal of the comparator CP and the expected value from the pattern generator 5 with the timing of the strobe signal from the timing generator 4.
The pass / fail judgment is performed by logical comparison, and the judgment result is output to the fail memory unit 8.

In the fail memory unit 8, the DU
The judgment result for each test cycle of T91 is stored in correspondence with the cell address of the device under test, a fail analysis is performed, and a mask signal is output to the logical comparator 7 and the waveform shaper 6.

Next, a configuration example and features of a flash memory as a device under test will be described. As shown in FIG. 4, for example, a flash memory of 64 Mbits (8 M × 8 bits) stores 8 chips in one chip on a wafer.
Each block is composed of 1024 blocks, each block is composed of 16 pages, and each page is composed of 512-bit cells.

The flash memory can be written / read in blocks. Therefore, the flash memory has less than a specified number of defective blocks (BAD B
LOCK) can be shipped as a good product.
For example, depending on product specifications, 10
Non-defective blocks within 10 within 24 blocks are considered non-defective.

On the other hand, the semiconductor test apparatus has a function of simultaneously testing a plurality of devices under test, thereby improving the test throughput. However, in the case of a flash memory, the defect occurrence rate in the previous process is high. ４4 simultaneous tests are common.

Next, the operation of a conventional flash memory will be described with reference to FIG. FIG.
As shown in (1), the main part of the fail memory unit 8 includes an address fail memory 81, a compact fail memory 82, a bad block memory 83, a bad block counter 84, and an OR gate 87.

An address fail memory 81 is provided for each device under test to be tested simultaneously, has the same memory capacity as the device under test, and writes 1 to an address corresponding to a fail cell of the device under test. Further, failure analysis can be performed by reading the contents of this memory.

The compact fail memory 82 is provided for each device to be tested at the same time, has a storage capacity of 1 bit width corresponding to the number of blocks of the DUT, and stores fail information compressed in units of blocks.

A defective block memory (BBM) 83 is provided for each device to be tested simultaneously, has a storage capacity of 1 bit width corresponding to the number of blocks of the DUT, and copies the contents of the compact fail memory 82 to a plurality of units. Stores the OR of the test results.

The bad block counter 84 is provided for each device under test to be tested at the same time, and is capable of receiving a read output from the bad block memory 83 and counting and accumulating bad blocks for each device under test.

When testing a plurality of DUTs 91 at the same time,
If a failure occurs in one block of a certain DUT 91, the fail signal from the logical comparator 7 is masked (MAS) into the waveform shaper 6 and the logical comparator 7 via the OR gate 87.
K) The signal is fed back.

In the waveform shaper 6, the mask signal is converted to AN
This signal is supplied to one end of the D gate 62 as a gate signal, the output of the RS flip-flop 61 is inhibited, and the control signal (/ WE,
/ RE, / CE) is not output. Also, the mask signal is set to A
A gate signal is applied to one end of the ND gate 72 to prohibit the output of the logical comparison result.

A test end flag (Fla) for each DUT
g) is received by the AND gate 88, and the test end flags of all the DUTs being tested at the same time are output to end the test.

Next, three conventional test methods for improving the throughput by focusing on the test characteristics of the flash memory will be described. First, when writing in a write test, the flash memory outputs a write end signal from the DUT when all the cells have been written. However, if there is a write failure, the test waits until the test times out. Time is wasted.

Therefore, the first method is to use two DUTs 1,
In the case where the DUT 2 is simultaneously tested, as shown in FIG. 6, when there is a defective block (a block indicated by diagonal lines) in the first test, the defective block memory (BBM) corresponding to the defective block has one DUT. In the second and subsequent tests, the control signal and the output of the logical comparison are masked and subjected to a simultaneous test, thereby eliminating the time-out waiting time and shortening the test time.

Secondly, in a flash memory, a block is determined to be defective by a specified number or more of defective cells in a certain block. For example, if the specified number is set to one, a defective cell in the middle of a test of a block ( When F) occurs, it is not necessary to perform the test in the subsequent test times.

In the second method, when a specified number of defects (F) occur in a cell in the middle of a test of a block, a control signal for testing the block and a logical comparison output are compared with a logical comparator 7.
(MASK) by the output of. If all of the blocks of the same number in the DUT being tested at the same time are defective, the test of that block is terminated by the logical sum of the fail output of the logical comparator 7 and the defective block memory 83, and Proceed to the test for the next block that is not marked. For example, as shown in FIG. 7, when the cell of the block 3 of the DUT 2 becomes defective first and the cell of the block 3 of the DUT 1 also becomes defective next, since the block 3 does not need to be tested, the next normal Proceed to the test of Block 4.

Third, in the previous process, all blocks are basically tested because there is no information on defective blocks in the flash memory. However, DUTs having a specified number of defective blocks need to be tested. Absent. In addition, each DUT
Performs a plurality of tests, such as a blank test, a write of 0 / read of 0, and a write of 1 / read, but the defective device under test does not need to be tested in subsequent times. Therefore, the third method is to prohibit all test signals from rejecting the DUT in the next and subsequent tests in a DUT in which the number of defective blocks is accumulated for each DUT by the defective block counter 84 and exceeds the specified value. Then, a test signal is given only to the other DUTs to perform a simultaneous test.

As described above, there is a method capable of simultaneously testing a plurality of flash memories at a high speed, but there is a demand in the market for a flash memory semiconductor test apparatus with further improved throughput.

[0026]

As described above, there is a market demand for improving the throughput of a semiconductor test apparatus for testing a flash memory. The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus capable of performing a test with further improved throughput by focusing on the test characteristics of a flash memory.

[0027]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor test apparatus for simultaneously testing a plurality of devices under test of a flash memory having a prescribed number of defective blocks. Storage means for previously storing the specified number of devices, a counter for accumulating the number of defective blocks for each device, detecting coincidence between the accumulated number of the counter for each device and the specified number of the storage means, and And a coincidence detecting means for outputting a signal prohibiting the test signal of the above, and the test is sequentially completed from the device having the largest number of defective blocks, and finally to the specified number of defective blocks of the device having the smallest defective block. A gist of the present invention is a semiconductor test apparatus characterized by terminating a test at the stage of detecting a defective cell.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. Overview of semiconductor test equipment,
The configuration and main features of the flash memory of the device under test have been described in the prior art, and a description thereof will be omitted.

Next, the operation of a case where a plurality of flash memories are tested simultaneously by the semiconductor test apparatus of the present invention will be described with reference to the essential configuration of the fail memory unit. As shown in FIG. 1, the main part of the fail memory unit 8 includes a conventional configuration including an address fail memory 81, a compact fail memory 82, a bad block memory 83, a bad block counter 84, and an OR gate 87. 85 and a matching circuit 86 are additionally provided.

However, the bad block counter 84 stores the bad block memory 83 or the compact fail memory 8
2 is a counter that receives the read output of No. 2 and counts and accumulates defective blocks for each device under test. In addition, each operation of the same configuration block as that of the related art has been described in the related art, and thus the description is omitted.

The register 85 is a storage means for preliminarily storing a specified number of blocks which are defective according to the specifications of the flash memory of the device under test by a test program.

The coincidence circuit 86 is provided with the bad block counter 8
When the accumulated number of 4 matches the specified number stored in the register 85, a mask signal for inhibiting the subsequent control signal and logical comparison is output, and a test end flag of the device under test is set.

Next, the operation of simultaneously testing two flash memories by the semiconductor test apparatus of the present invention shown in FIG. 1 will be described with reference to FIG. However, for simplicity, FIG. 1 shows only one flash memory as the DUT 91. In general, a flash memory test is performed in a plurality of times such as a blank test, a write of 0 / read of 0, and a write of 1 / read in each manufacturing process from a pre-process in a wafer state to a final process after packaging. Perform a test to determine good / defective products.

Then, as shown in FIG.
Assuming that two flash memories T1 and DUT2 are tested simultaneously, the number of blocks in each flash memory is 1024, and a DUT having 10 or more defective blocks is defined as a defective product. In addition, in each block, if there is one defective cell, the block is determined to be defective.

For example, in the first simultaneous test, DU
Assume that the number of defective blocks in T1 is block 2,..., Block 1023, that is, a total of eight, and the number of defective blocks in DUT2 is block 1,.

Further, as shown in FIG. 2B, in the second simultaneous test, the block 3 of the DUT 1 becomes a new failure and becomes a ninth block failure, and the block 502 becomes a new defective cell. Is generated and the tenth block is defective, and the block 504 of the DUT 2 has a new defective cell and becomes the tenth block defective.

In the semiconductor test apparatus of this embodiment, all the conventional methods are inherited, so that the method described in the prior art can be implemented. Therefore, the block which failed in the first test is tested by masking the control signal of each DUT and the output of the logical comparison in the second test in the second and subsequent tests.

When a specified number of defects occur in the cells in the middle of the test of the block, the control signal and the logical comparison output of the block are masked by the output of the logical comparator 7. If a defect is detected in the same block of the DUT that is being tested at the same time, the test of that block is terminated, and the test is advanced to the next block that is not defective.

Further, the number of defective blocks is integrated for each DUT by the defective block counter 84, and the number of defective blocks exceeding the specified value is calculated.
The UT prohibits all test signals in order to reject the DUT in the number of times of the next and subsequent tests.

In the present invention, in addition to the above test methods,
As shown in FIG. 2B, in the DUT1, a second test is performed on a block that has not failed in the first test,
The cell in the middle of the test in block 502 that passed (P: PASS) in the first test is defective (F: FAIL)
Is newly generated, the defective block counter 84 shown in FIG. 1 is run in a state where the first failure count is counted, and the count is incremented by one by reading and outputting the defective block from the compact fail memory 82.

When the cumulative number of the bad block counter 84 matches the specified number of the register 85, the DUT 1
Is set, and the logical comparison and the control signal are masked for the cells and blocks after the detection of the defective cell in the block 502 so as not to affect the test of the DUT 2 during the simultaneous test.

Similarly, as shown in FIG.
In DUT2, which is being tested at the same time as T1, a second test of a block that did not fail in the first test is performed. If a defective cell is generated during the test of block 504 and a tenth block is defective, The defective block counter 84 shown in FIG. 2 is run in a state where the first failure count is counted, and the count is incremented by one by reading and outputting the defective block from the compact fail memory 82.

When the cumulative number of the bad block counter 84 matches the specified number of the register 85, the DUT 2
Are set, and the end flags of all the DUTs are set by the logical sum of the test end flag of the DUT 1 and the test end flag of the DUT 1 and the simultaneous test is ended.

That is, in the semiconductor test apparatus of the present invention, among a plurality of DUTs being tested at the same time, the test is sequentially completed from the DUT with the largest number of defective blocks, and finally the specified number of the DUTs with the fewest defective blocks When the defective cells of the defective block have occurred, the testing of all the DUTs can be completed, and the process can proceed to the sequence of the DUTs to be simultaneously tested.

[0045]

The present invention is embodied in the form described above, and has the following effects. That is,
The semiconductor test apparatus according to the present invention includes a plurality of D
In the UT, the test is sequentially completed from the DUT having the largest number of defective blocks, and finally the DUT having the smallest number of defective blocks is completed.
When the defective cells of the specified number of defective blocks of the UT have occurred, the tests of all the DUTs are completed, and then the DUs to be simultaneously tested
Since the process proceeds to the sequence of T, there is an effect that the test throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a semiconductor test apparatus of the present invention.

FIG. 2 is an example of a configuration diagram of a block defect of a flash memory.

FIG. 3 is a block diagram of a semiconductor test apparatus.

FIG. 4 is a specific configuration diagram of a flash memory.

FIG. 5 is a main block diagram of a conventional semiconductor test apparatus.

FIG. 6 is an example of a configuration diagram of a block defect of a flash memory.

FIG. 7 is an example of a configuration diagram of a block defect of a flash memory.

[Explanation of symbols]

 Reference Signs List 4 timing generator 5 pattern generator 6 waveform shaper 7 logical comparator 8 fail memory unit 20 main frame 30 test head 61 RS flip-flop 62 AND gate 71 EX-OR gate 72 AND gate 81 address fail memory 82 compact fail memory 83 Bad block memory 84 Bad block counter 85 Register 86 Matching circuit 87 OR gate 88 AND gate 91 DUT

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 R P

Claims (1)

[Claims] 1. A semiconductor test apparatus for simultaneously testing a plurality of devices under test of a flash memory in which the number of defective blocks is specified, a storage means for storing a specified number of defective blocks in advance, and a device for storing the number of defective blocks in a device. A counter that accumulates each time, and coincidence detection means that detects a coincidence between the accumulated number of each device of the counter and the specified number of the storage means, and outputs a signal that inhibits a test signal of the device. A semiconductor test apparatus characterized in that a test is sequentially completed from a device having a large number of defective blocks, and the test is terminated when a defective cell is detected in a specified number of defective blocks of a device having the least number of defective blocks. .