JPH05233841A - Input/output buffer for microcomputer - Google Patents

Abstract

PURPOSE:To avoid a Hi-Z state unfixing the input level of a logic element connected to a bus line when reducing energy consumption by stopping clocks. CONSTITUTION:The input terminal of a logic circuit 111 at an output buffer 11 is connected to the output terminal of a data selector 2, and the output terminal of a logic circuit 112 is connected to input an output permit signal 10 to an output permit signal input terminal 113 and to input a clock stop signal 6 to a clock stop signal input terminal 114. The output terminal of the output buffer 11 is connected to an input/output terminal 5 and one input terminal of a logic circuit 121 at an input buffer 12, and the logic circuit 121 outputs an input signal through an inverter 123. The output terminal of a logic circuit 122 to input a clock stop signal 7 and an output permit signal 9 is connected to the other input terminal of the logic circuit 121. An output data signal 7, input signal 8, clock stop signal 7 and the inverse of the clock stop signal 7 are respectively connected to the input terminal of the data selector 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to an output buffer used for a bus driver of a microcomputer or an input / output interface.

[0002]

2. Description of the Related Art FIG. 3 is an equivalent circuit diagram of an input / output buffer of a conventional microcomputer. I / O buffer 31
The output buffer 11 includes an input end, an output end, and an output control terminal 115, and the output end is connected to the input / output terminal 5 and the input buffer 1.
The output permission signal 10 is connected to the output control terminal 115 via the inverter 311. The input permission signal 9 is connected to the other input terminal of the input buffer 121, and the output is used as the input signal 8. Further, outside the input / output terminal 5, a pull-up resistor 32 and a latch circuit 33 are provided.
External circuit 51.

The inverter 311 and the output buffer 11
The input / output buffer 31 of the conventional microcomputer configured from the input buffer 121 is generally a so-called three-state buffer having three states of input, output and high impedance (hereinafter, referred to as Hi-Z).
It is used as an input / output buffer for microcomputers and input / output interface devices. That is, when the output permission signal 10 is “1”, the output data signal 7 is output to the external circuit 51 via the input / output terminal 5, and the input permission signal 9 is output.
When is "0", the data signal from the external circuit 51 is input to the inside through the input / output terminal 5. When the output permission signal 10 is "0", the input / output buffer 31 is in the Hi-Z state. However, in recent years, microcomputers and their peripheral devices often stop their clocks in order to reduce power consumption. Therefore, the three-state buffer may stop in the Hi-Z state. At this time, if there is no logic gate in the output state with respect to the bus line that connects the three-state buffer in the internal circuit of the microcomputer or its peripheral device, the bus line is in the Hi-Z state, CM
OS (Complementary MetalOxi)
Even if the circuit is composed of a de-semiconductor), the potential of the bus line gradually approaches the intermediate potential of the CMOS due to the stray capacitance of the bus line with the passage of time, and the P-channel type of the logic gate that inputs the signal from the bus line Both the insulated gate field effect transistor (hereinafter simply referred to as P-channel type transistor) and the N-channel type insulated gate field effect transistor (hereinafter simply referred to as N-channel type transistor) become conductive at the same time so that a current flows, which results in power consumption. This has led to an increase in consumption. Conventionally, for such power consumption,
By adding a pull-up resistor 32 or a latch circuit 33 for holding a logical value to the output terminal of the output buffer, the potential of the bus line in the Hi-Z state is either high level or low level. The method of setting to.

[0004]

The input / output buffer 31 of the conventional microcomputer described above is pulled up so that the potential of the bus line gradually becomes the intermediate potential of the CMOS in the Hi-Z state when the clock is stopped. Resistance 32,
Alternatively, it is avoided by the holding latch circuit 33. In the former case, when the output logic value of the bus line when the clock is stopped becomes “0”, the power line is pulled through the pull-up resistor to the ground line through the N-channel transistor of the output buffer having the logic value “0”. Since the current flows, the current is always consumed while the output logical value of the bus line is "0". Further, when the holding latch circuit is used, the output voltage of the output buffer 11 is inverted and then the output voltage of the holding latch circuit 33 is inverted when the potential of the bus line is inverted even in the normal operation state. Therefore, transiently, there occurs a moment when the N-channel transistor of the output buffer 11 and the P-channel transistor of the output side of the holding latch circuit 33 become conductive at the same time, and similarly the output buffer 1
1 P-channel transistor and holding latch circuit 33
There is a moment when the N-channel transistors on the output side of are simultaneously turned on, and every time the output potential of the latch circuit is inverted,
It has a drawback that a through current flows through the route.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art so that in the clock stop state,
Avoid power consumption due to the Hi-Z state of the bus line,
Another object of the present invention is to provide an input / output buffer of a microcomputer that can avoid unnecessary power consumption when the potential of the bus line is inverted even in a normal operation state.

[0006]

A feature of the present invention is that an output data signal from a central processing unit is controlled by an output permission signal to an external circuit, an output buffer, an input signal input from the external circuit, and In an input / output buffer consisting of an output signal input from the output buffer and an input buffer for controlling the input by an input permission signal,
A means for holding the state of the output data of the input / output buffer when the clock is stopped is provided by using the clock stop signal and the data selector.

The means connects an output end of the data selector to an input end of a first logic circuit having an output control terminal of the output buffer, and outputs an output enable signal and a clock stop signal to the output control terminal. And an output end of the second logic circuit which receives as input, and an output end of the first logic circuit is connected to the input / output terminal and the third buffer of the input buffer.
Is connected to one input end of the logic circuit, and the output end of the third logic circuit is connected to the input end of the data selector via the first inverter, and the other end of the third logic circuit is connected. The output end of the fourth logic circuit, which receives the clock stop signal and the input enable signal, can be connected to the input end of the.

The data selector has an AND-OR logic function. One of the input terminals of the first AND circuit receives the clock stop signal via the second inverter, and the other input terminal receives the output data signal. The clock stop signal is connected to one input terminal of the AND circuit and the input signal is connected to the other input terminal, and the output terminals of the first and second AND circuits are connected to the input terminal of the OR circuit. The output terminal of the OR circuit can be connected to the output terminal of the data selector.

It is possible to have means for generating the clock stop signal by a clock stop signal generation circuit that receives a clock.

The clock stop signal generation circuit includes a P-channel type insulated gate field effect transistor and an N-channel type insulated gate field effect transistor which receive a clock as an input, and the source of the P-channel type insulated gate field effect transistor is a power source. The drain is connected to the ground line through the first capacitor and the first resistor, and the drain is connected to one input end of the fifth logic circuit through the third inverter, and The source of the N-channel insulated gate field effect transistor is connected to the ground line, the drain is connected to the power supply line via the second capacitor and the second resistor, and the drain is connected to the fourth inverter and the fifth inverter. Connected to the other input terminal of the fifth logic circuit, and the output of the fifth logic circuit can be used as the clock stop signal. .

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the input / output buffer of the microcomputer of the present invention.
As shown in FIG. 1, it comprises an input / output buffer 1, a data selector 2, a CPU 3, an inverter 4, and an input / output terminal 5.
An external circuit 51 is connected to the input / output terminal 5. The input / output buffer 1 is composed of an output buffer 11 and an input buffer 12. The output buffer 11 is composed of a first logic circuit 111 having an output control terminal 115 and a second logic circuit 112. The input end of the first logic circuit 111 is connected to the output end of the data selector 2 to control the output. The output terminal of the second logic circuit 112 is connected to the terminal 115. The second
The output permission signal 10 is input to the output permission signal input terminal 113 of the logic circuit 112 of FIG.
The clock stop signal 6 is input to the. Output buffer 1
The output end of 1 is the input / output terminal 5 and the third end of the input buffer 12.
Connected to one input end of the logic circuit 121, and the output of the third logic circuit 121 outputs the input signal 8 via the inverter 123. The output terminal of the fourth logic circuit 122 is connected to the other input terminal of the third logic circuit 121. Fourth
The clock stop signal 6 is input to the clock stop signal terminal 124 of the logic circuit 122, and the output enable signal 9 is input to the input enable signal terminal 125. One input terminal of the first AND circuit of the data selector 2 has an output data signal 7
, The other input end receives the clock stop signal 6 through the inverter 4, one input end of the second AND circuit receives the clock stop signal 7, and the other input end receives the input signal 8. Connecting.

Next, the operation of the first embodiment will be described. The output permission signal 10 that issues output permission to the output buffer 11 and the input permission signal 9 that issues input permission to the input buffer 12 do not depend on the stop operation of the clock and issue the input / output permission as a normal operation state. It is a signal. The clock stop signal 6 output when the power control unit or the like connected to the microcomputer stops the clock of the microcomputer has a logical value "0" in a normal operation state. At this time, the data selector 2 selects the output data signal 7 from the inside of the microcomputer.
Therefore, the output buffer 11 outputs the data of the output data signal 7 from the input / output terminal 5 at the timing when the output permission signal 10 becomes "1". Further, at the timing when the input permission signal 9 input to the input signal permission terminal 125 of the input buffer 12 becomes "1", the data input from the external circuit 51 connected to the microcomputer via the input / output terminal 5 is fetched inside. It will be.

Next, the operation when the clock is stopped will be described. When the clock is stopped, the clock stop signal 6 becomes "1". Therefore, the input buffer 12 is in the output enable state, and the data selector 4 has the input signal 8
Select. At this time, even if the external circuit 51 connected to the microcomputer outputs the data to the input / output terminal 5, the input data is input to the input buffer 1
2, the data selector 2 and the output buffer 11 are fed back, so that the output of the output buffer 11 holds either the high level potential or the low level potential depending on the state of the data given to the input / output terminal 5. , Hi-Z state, and does not become indefinite. Therefore, a through current does not flow between the output buffer 11 and the external circuit 51, and there is no unnecessary power consumption. Further, even when the microcomputer itself is in the output state, the output buffer 11 feeds back and holds the output data at that time through the same path as described above, so that the input / output terminal 5 does not enter the Hi-Z state. And it doesn't become indefinite.

Next, a second embodiment will be described. The difference from the first embodiment is that the input / output buffer 1 itself is
By adding the clock stop signal generation circuit 40,
Since the clock stop signal 400 is generated, it is not necessary to input the clock stop signal from the outside. The input / output buffer 1 itself is the same as that of the first embodiment, so its explanation is omitted. Therefore, the clock stop signal generation circuit 40 will be described here. FIG. 2 is an equivalent circuit diagram of the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.
The gates of the P-channel type MOS transistor 405 and the N-channel type MOS transistor 410 have the clock signal 5
Connect to enter 0. The P channel type MOS
The source of the transistor 405 is connected to the power supply line, and the drain of the transistor 405 is connected to the input of the third inverter 402 and the capacitor 406.
The other terminal of the capacitor 406 is connected to the ground line via the resistor 407, and the output of the inverter 402 is connected to one input terminal of the fifth logic circuit 401. Next, the N-channel type MOS
The source of the transistor 410 is connected to the ground line, and the drain of the transistor 410 is connected to the input of the fourth inverter 404 and the capacitor 409.
The other terminal of the capacitor 409 is connected to the power supply line 40 via the resistor 408, while being connected to one terminal of
Further, the output of the fourth inverter 404 is connected to the other input terminal of the logic circuit 401 via the fifth inverter 403. The output of the fifth logic circuit 401 is connected to the input / output buffer 1 and the clock stop signal input terminal of the data selector 2.

Next, the operation of the second embodiment will be described. The clock stop signal generation circuit 40 includes a detection circuit when the clock stops at "1" and a clock of "0".
The operation is the same except that the logic value is inverted. First, the case where the clock stops at "1" will be described. When the clock 50 repeats the inversion operation in the normal operation state, the P-channel type MOS transistor 405 becomes conductive while the clock 50 is "0", so that the capacitor 40
6 is charged and the P-channel type MOS transistor 405 is non-conducting during the period when the clock 50 is "1",
The discharging operation is performed according to the time determined by the time constant of the capacitor 406 and the resistor 407. As a result of the discharging operation, when the input level of the third inverter 402 becomes lower than the threshold voltage, the output level of the third inverter 402 becomes "1".
Becomes However, since the clock 50 repeats the inversion operation, the recharge operation is performed before the output level of the third inverter 402 is inverted to "1". Therefore, when the clock 50 is stopped at "1", the input level of the third inverter 402 becomes equal to or lower than the threshold voltage due to the discharge operation, and the third inverter 4
The output level of 02 is inverted to "1". Therefore, the clock stop signal 400 output from the fifth logic circuit 401 becomes "1". In addition, even when the clock stops at "0", the N-channel type MO that has the opposite relation of the charge and discharge described above.
S transistor 410, capacitor 409 and resistor 408
The same operation is performed by the fourth inverter 4
04, through the fifth inverter 403, the output level of the fifth inverter 403 is inverted to "1". Therefore, the clock stop signal 40 output from the fifth logic circuit 401 is output.
0 becomes "1". In this embodiment, the clock stop signal 400 is used to perform feedback control of the input / output buffer as described in the first embodiment.

[0017]

As described above, in the input / output buffer of the microcomputer of the present invention, the output buffer 11, the input buffer 12 and the data selector 2 which are connected to the input / output terminal 5 form a feedback circuit. In the stop state, the potential of the bus line is held at either a high level or a low level depending on the state of the output data of the output buffer 11. Therefore, in addition to avoiding power consumption due to the bus line entering the Hi-Z state, the conventional pull-up resistor and the holding latch circuit are not used even in the normal operating state. This has an effect that a through-current does not flow when the potential of the bus line is inverted and unnecessary power consumption is prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an input / output buffer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an input / output buffer according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional input / output buffer.

[Explanation of symbols]

1, 20 Input / output buffer 2 Data selector 3 Central processing unit (CPU) 4 Second inverter 5 Input / output terminal 6,400 Clock stop signal 7 Output data signal 8 Input signal 9 Input enable signal 10 Output enable signal 11 Output buffer 12 Input buffer 21 First AND circuit 22 Second AND circuit 23 OR circuit 30 Power line 40 Clock stop signal generation circuit 50 Clock 51 External circuit 111 First logic circuit 112 Second logic circuit 113 Output enable signal input terminal 114 , 124 clock stop signal input terminal 115 output control terminal 121 third logic circuit 122 fourth logic circuit 123 first inverter 125 input permission signal input terminal 202 third inverter 203 fifth inverter 204 fourth inverter 205 P-channel insulated gate Field effect transistor 206 the first capacitor 207 first resistor 208 and the second resistor 209 a second capacitor 210 N-channel insulated gate field effect transistor

Claims (5)

[Claims] 1. An output data signal from a central processing unit,
An input buffer that controls an output to an external circuit by an output enable signal, and an input buffer that controls an input signal input from the external circuit and an output signal input from the output buffer by an input enable signal. An input / output buffer of a microcomputer, wherein the output buffer includes means for holding a state of output data of the input / output buffer when the clock is stopped, using a clock stop signal and a data selector. 2. The means connects an output end of the data selector to an input end of a first logic circuit having an output control terminal of the output buffer, and an output enable signal and a clock are provided at the output control terminal. The output terminal of the second logic circuit, which receives the stop signal as an input, is connected, and the output terminal of the first logic circuit is connected to the input / output terminal and one input terminal of the third logic circuit of the input buffer. And to the third
The output end of the logic circuit is connected to the input end of the data selector through the first inverter, and the clock stop signal and the input enable signal are input to the other input end of the third logic circuit. The input / output buffer of the microcomputer according to claim 1, wherein the output terminal of the fourth logic circuit for input is connected. 3. The data selector has an AND-OR logic function, wherein one input terminal of the first AND circuit receives the clock stop signal via a second inverter and the other input terminal receives the output data signal. The clock stop signal is connected to one input terminal of the second AND circuit and the input signal is connected to the other input terminal thereof, and the output terminals of the first and second AND circuits are connected to the input terminal of the OR circuit. 3. The input / output buffer of the microcomputer according to claim 2, wherein the output terminal of the OR circuit is an output terminal of the data selector. 4. The input / output buffer of a microcomputer according to claim 1, further comprising means for generating the clock stop signal by a clock stop signal generation circuit which receives a clock as an input. 5. The clock stop signal generation circuit includes a P-channel type insulated gate field effect transistor and an N-channel type insulated gate field effect transistor which receive a clock, and the source of the P-channel type insulated gate field effect transistor. Is connected to the power supply line, the drain is connected to the ground line via the first capacitor and the first resistor, and the drain is connected to one input end of the fifth logic circuit via the third inverter. The source of the N-channel insulated gate field effect transistor is connected to the ground line, the drain is connected to the power supply line through the second capacitor and the second resistor, and the drain is the fourth inverter and the fifth inverter. 5. The other input terminal of the fifth logic circuit is connected via the above, and the output of the fifth logic circuit is used as the clock stop signal. Input / output buffer of the described microcomputer.