JPH0523117B2 - - Google Patents
Info
- Publication number
- JPH0523117B2 JPH0523117B2 JP58195979A JP19597983A JPH0523117B2 JP H0523117 B2 JPH0523117 B2 JP H0523117B2 JP 58195979 A JP58195979 A JP 58195979A JP 19597983 A JP19597983 A JP 19597983A JP H0523117 B2 JPH0523117 B2 JP H0523117B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- time
- luminance signal
- circuit
- color difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000006835 compression Effects 0.000 claims description 7
- 238000007906 compression Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 2
- 101150046378 RAM1 gene Proteins 0.000 description 2
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 2
- RRLHMJHRFMHVNM-BQVXCWBNSA-N [(2s,3r,6r)-6-[5-[5-hydroxy-3-(4-hydroxyphenyl)-4-oxochromen-7-yl]oxypentoxy]-2-methyl-3,6-dihydro-2h-pyran-3-yl] acetate Chemical compound C1=C[C@@H](OC(C)=O)[C@H](C)O[C@H]1OCCCCCOC1=CC(O)=C2C(=O)C(C=3C=CC(O)=CC=3)=COC2=C1 RRLHMJHRFMHVNM-BQVXCWBNSA-N 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100328887 Caenorhabditis elegans col-34 gene Proteins 0.000 description 1
- 101000863856 Homo sapiens Shiftless antiviral inhibitor of ribosomal frameshifting protein Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/86—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback the individual colour picture signal components being recorded sequentially and simultaneously, e.g. corresponding to SECAM-system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/87—Regeneration of colour television signals
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は映像信号を記録再生する装置に係り、
特に映像信号中の輝度信号とクロマ信号を時分割
多重して記録再生するに好適な装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an apparatus for recording and reproducing video signals,
In particular, the present invention relates to a device suitable for recording and reproducing time-division multiplexing of luminance signals and chroma signals in a video signal.
従来の輝度信号とクロマ信号を時分割多重して
記録再生する技術にタイムプレツクスがある。タ
イムプレツクスは輝度信号を4/5に時間圧縮し、
クロマ信号を1/5に時間圧縮した後これらを時分
割多重する方式である。
Timeplex is a conventional technology for recording and reproducing luminance signals and chroma signals by time division multiplexing. Timeplex time compresses the luminance signal to 4/5,
This method compresses the time of the chroma signal to 1/5 and then time-division multiplexes the signals.
タイムプレクス方式の欠点は輝度信号の帯域幅
を確保しにくいことである。タイムプレクス方式
では再生時に5/4倍に時間伸長するため、時間圧
縮伸長を行なわない方式に比べ帯域幅が８割とな
つてしまう。 The disadvantage of the time-plex method is that it is difficult to secure the bandwidth of the luminance signal. In the timeplex method, time is expanded by 5/4 times during playback, so the bandwidth is 80% of that of a method that does not perform time compression and expansion.
本発明の目的は、従来技術の欠点をなくし、輝
度信号の再生帯域幅を劣化させることなく、輝度
信号とクロマ信号を時分割多重して記録再生する
映像信号の記録再生装置を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a video signal recording and reproducing device that time-division multiplexes a luminance signal and a chroma signal and records and reproduces them without degrading the reproduction bandwidth of the luminance signal. .
本発明においては、ライン毎に時間圧縮されな
い輝度信号と時間圧縮された輝度信号を切替えた
信号を記録媒体に記録し再生する。又、ハードウ
エアを簡単にするため、信号の配列を時間圧縮さ
れない輝度信号、水平同期信号、クロマ零レベ
ル、時間圧縮された第１の色差信号、時間圧縮さ
れた輝度信号、時間圧縮された第２の色差信号、
時間圧縮されない輝度信号、……の順とする。再
生装置においては、上記信号をそのまま復調した
だけではライン毎に広帯域の輝度信号と狭帯域の
輝度信号か交互に生じてしまう。これを補償する
ため、広帯域の輝度信号を1H遅延させ、遅延信
号の高城成分を狭帯域の輝度信号に加算する。
In the present invention, a signal in which a luminance signal that is not time-compressed and a luminance signal that is time-compressed are switched for each line is recorded on a recording medium and reproduced. In order to simplify the hardware, the signal arrangement is divided into a non-time compressed luminance signal, a horizontal synchronization signal, a chroma zero level, a time compressed first color difference signal, a time compressed luminance signal, and a time compressed first color difference signal. 2 color difference signals,
Luminance signals that are not time-compressed are in this order. In the reproducing device, if the above-mentioned signal is simply demodulated, a wideband luminance signal and a narrowband luminance signal will be generated alternately for each line. To compensate for this, the wideband luminance signal is delayed by 1H, and the Takagi component of the delayed signal is added to the narrowband luminance signal.
以下、本発明の一実施例を第１〜第５図を用い
て説明する。第１図は本発明をビデオテープレコ
ーダに用いた場合の記録回路の一例を示すブロツ
ク図、第２図は第１図の各部の波形とRAMの動
作を示す図である。
Hereinafter, one embodiment of the present invention will be described using FIGS. 1 to 5. FIG. 1 is a block diagram showing an example of a recording circuit when the present invention is applied to a video tape recorder, and FIG. 2 is a diagram showing the waveforms of each part of FIG. 1 and the operation of the RAM.
第１図において、１はビデオ信号の発生装置で
あり、第２図に示すＹ，Ｕ，Ｖを出力する。２は
スイツチ回路であり、Ｕ，Ｖが入力され、出力に
はライン毎にＵとＹが交互に現われる。３，４は
アナログ信号をデジタル信号に変換するADコン
バータ、５は同期分離回路、６は位相比較回路、
７は5120H VCO（H：水平同期周波数）、８は
１／５分周器、９は1/4分周器、１０は1/256分周器
である。６，７，８，９，１０はPLL回路を構
成し、水平同期信号に位相同期したクロツク信
号、1024H、256Hを発生する。１１は1/4分周
器であり1280Hを出力する。１２，１３，１４，
１５は時間軸変換用RAMであり、RAM１，
RAM２は書込みクロツクを256Hとし、読出し
クロツクを1280Hとし、時間軸を1/5に圧縮する
色差信号用時間圧縮回路である。RAM３は書込
みクロツクを1024Hとし、読み出しクロツクを
1280Hとし時間軸を4/5に圧縮する輝度信号用時
間圧縮回路である。RAM４は書込みクロツク、
読み出しクロツクとも1024Hとした輝度信号用
1H遅延回路である。（1Hは１水平走査期間）
第２図におけるＡ，Ｂ，Ｃ，ＤはRAM１，
２，３，４の動作状態を夫々示す。Highの期間
が読出し期間を示し、Lowが書込み期間を示す。 In FIG. 1, reference numeral 1 denotes a video signal generator, which outputs Y, U, and V shown in FIG. 2 is a switch circuit to which U and V are input, and U and Y appear alternately on each line at the output. 3 and 4 are AD converters that convert analog signals to digital signals, 5 is a synchronous separation circuit, 6 is a phase comparison circuit,
7 is a 5120H VCO (H: horizontal sync frequency), 8 is a 1/5 frequency divider, 9 is a 1/4 frequency divider, and 10 is a 1/256 frequency divider. 6, 7, 8, 9, and 10 constitute a PLL circuit, which generates clock signals 1024H and 256H whose phase is synchronized with the horizontal synchronization signal. 11 is a 1/4 frequency divider and outputs 1280H. 12, 13, 14,
15 is RAM for time axis conversion, RAM1,
The RAM 2 is a time compression circuit for color difference signals that has a write clock of 256H, a read clock of 1280H, and compresses the time axis to 1/5. RAM3 has a write clock of 1024H and a read clock of 1024H.
This is a time compression circuit for luminance signals that compresses the time axis to 4/5 as 1280H. RAM4 is the write clock,
For luminance signal with both readout clocks set to 1024H
It is a 1H delay circuit. (1H is 1 horizontal scanning period) A, B, C, D in Figure 2 are RAM1,
2, 3, and 4 are shown, respectively. A high period indicates a read period, and a low period indicates a write period.
第１図において、１６はRAM１，２，３，４
の出力を合成する信号合成回路、１７はデジタル
信号をアナログ信号に戻すDAコンバータであ
り、出力に第２図Ｓの波形を得る。Ｓの波形の特
徴は図から判るように、時間圧縮されない輝度信
号（Yo-2，Yo……）と4/5に時間圧縮された輝度
信号（Yo-3，Yo-1，……）がライン毎に交互に
現われる。1/5に時間圧縮された２つの色差信号
Ｕ，Ｖは時間圧縮された輝度信号の前後に隣接し
て配置される。水平同期信号は１ラインおきに配
置され、水平同期信号とＵ信号の間に50％IREの
信号を付加し、これを色差信号の零レベル判別と
する。 In Figure 1, 16 is RAM 1, 2, 3, 4
A signal synthesis circuit 17 synthesizes the outputs of , and 17 is a DA converter that returns the digital signal to an analog signal, obtaining the waveform shown in FIG. As can be seen from the figure, the characteristics of the waveform of S are the luminance signals that are not time-compressed (Y o-2 , Yo ... ) and the luminance signals that are time-compressed to 4/5 (Y o-3 , Yo -1 , ) appear alternately on each line. The two color difference signals U and V, which are time-compressed to 1/5, are placed adjacent to and before and after the time-compressed luminance signal. The horizontal synchronization signal is arranged every other line, and a 50% IRE signal is added between the horizontal synchronization signal and the U signal, and this is used to determine the zero level of the color difference signal.
以上のような信号形式とすることで以下の長所
を得る。 By using the signal format as described above, the following advantages are obtained.
(1)時間軸変換用RAMを４個で済ませることが
できる。(2)時間軸変換に伴う遅延時間を1Hとす
ることができ、垂直ブランキング期間の時間軸圧
縮を止めやすい。(3)Ｙ，Ｕ，Ｖの遅延時間がほぼ
揃い色ずれを生じにくい。 (1) Only four RAMs are required for time axis conversion. (2) The delay time associated with time axis conversion can be reduced to 1H, making it easy to stop time axis compression during the vertical blanking period. (3) Y, U, and V delay times are almost the same, making color shift less likely to occur.
１８〜２５は従来のビデオテープレコーダと同
じ信号処理回路であり、１８は同期尖端をクラン
プする回路、１９は入力信号レベルが小さいほど
エンフアシス量の増すダイナミツクエンフアシス
回路、２０はエンフアシスにより生じるオーバー
シユートを制限するクリツプ回路、２１は周波数
変調回路、２２は書込みアンプ、２３は２チヤン
ネルのロータリトランス、２４は２個のビデオヘ
ツド、２５はビデオテープである。 18 to 25 are the same signal processing circuits as in conventional video tape recorders, 18 is a circuit that clamps the synchronization peak, 19 is a dynamic emphasis circuit that increases the amount of emphasis as the input signal level becomes smaller, and 20 is generated by emphasis. A clip circuit for limiting overshoot, 21 a frequency modulation circuit, 22 a write amplifier, 23 a two-channel rotary transformer, 24 two video heads, and 25 a video tape.
第３図は本発明をビデオテープレコーダに用い
た場合の再生回路の一例を示すブロツク図、第４
図は第３図の各部の波形図、第５図はRAM５，
６，７，８の動作状態を示す図である。 FIG. 3 is a block diagram showing an example of a playback circuit when the present invention is used in a video tape recorder, and FIG.
The figure is a waveform diagram of each part in Figure 3, Figure 5 is RAM5,
It is a figure which shows the operating state of 6, 7, and 8.
第３図において、２３〜３１は従来のビデオテ
ープレコーダの再生回路であり、２６は２チヤン
ネルのヘツドアンプ、２７はヘツドスイツチ回
路、２８はFMイコライズ回路、２９はリミタ、
３０はFM復調回路、３１はダイナミツクデイエ
ンフアシス回路である。 In FIG. 3, 23 to 31 are playback circuits of a conventional video tape recorder, 26 is a two-channel head amplifier, 27 is a head switch circuit, 28 is an FM equalization circuit, 29 is a limiter,
30 is an FM demodulation circuit, and 31 is a dynamic de-emphasis circuit.
ダイナミツクデイエンフアシス回路３１の出力
には第４図Ｓの波形が再生され、同期分離回路３
２によりH／２の周波数を持つ水平同期信号が抜き
出される。３３〜３８はPLLを構成しており、
３３は位相比較器、３４は1/2分周器、３５は1/2
５６分周器、３６は1/4分周器、３７は1/5分周器、
３８は1/4分周器、３９は5120HのVCOである。 The waveform S shown in FIG. 4 is reproduced at the output of the dynamic de-emphasis circuit 31,
2, a horizontal synchronizing signal having a frequency of H/2 is extracted. 33 to 38 constitute the PLL,
33 is a phase comparator, 34 is a 1/2 frequency divider, and 35 is a 1/2
56 frequency divider, 36 is 1/4 frequency divider, 37 is 1/5 frequency divider,
38 is a 1/4 frequency divider, and 39 is a 5120H VCO.
５７はADコンバータでありアナログ信号Ｓを
デジタル信号に変換する。４０〜４３は時間軸復
元用RAMであり、PLL回路からクロツク信号が
供給される。RAM５は書込みクロツク、読み出
しクロツクとも1024Hし、書込み、読み出しの
タイミングを第５図Ｅに示す1H遅延回路である。
RAM６は書込みクロツクを1280H、読み出しク
ロツクを1024Hとし書込み、読み出しタイミン
グを第５図Ｅとする5/4倍の時間軸伸長回路であ
る。RAM７、RAM８は書込みクロツクを
1280Hとし読み出しクロツクを256Hとし、書
込み、読み出しタイミングを第５図Ｇ，Ｈとする
５倍の時間軸伸長回路である。４４，４５，４６
は1H遅延回路、４７，４８，４９，５０はデジ
タル信号をアナログ信号に戻すDAコンバータで
ある。 57 is an AD converter that converts the analog signal S into a digital signal. Reference numerals 40 to 43 are RAMs for time axis restoration, to which a clock signal is supplied from the PLL circuit. The RAM 5 has a write clock and a read clock of 1024H, and is a 1H delay circuit whose write and read timings are shown in FIG. 5E.
The RAM 6 is a 5/4 time axis expansion circuit with a write clock of 1280H and a read clock of 1024H for writing and read timing as shown in FIG. 5E. RAM7 and RAM8 use the write clock.
This is a five-fold time axis expansion circuit in which the clock is 1280H, the read clock is 256H, and the write and read timings are G and H in FIG. 44, 45, 46
is a 1H delay circuit, and 47, 48, 49, and 50 are DA converters that return digital signals to analog signals.
４７の出力には第４図のYWに示す一ラインお
きの広帯域な輝度信号を得、４８の出力には第４
図YNWに示すライン毎に帯域幅の異なる輝度信号
を得る。 The output of 47 is a broadband luminance signal of every other line shown in YW in Figure 4, and the output of 48 is a wideband luminance signal of 4th line.
Obtain luminance signals with different bandwidths for each line shown in Figure YNW .
HPF５１と加算回路５２はYNWとYWからライ
ン毎に帯域幅の変らない信号Y′を得るため、YW
の高域成分をYNWに加算している。 The HPF 51 and the adder circuit 52 use Y NW and Y W to obtain a signal Y' whose bandwidth does not change for each line from Y NW and Y W.
The high frequency component of is added to Y NW .
５２の出力信号は水平同期信号が不完全であ
り、同期付加回路５３によりPLLからのH信号
を加算されY′信号となる。５４，５５，５６は
信号の出力端子である。 The output signal 52 is an incomplete horizontal synchronization signal, and is added with the H signal from the PLL by the synchronization addition circuit 53 to become the Y' signal. 54, 55, and 56 are signal output terminals.
本発明によれば従来の時分割多重方式の欠点で
あつた輝度信号の帯域幅劣化が全くなく、広帯域
な輝度信号と高品位なクロマ信号を同時に再生す
ることが可能となるし、また、水平同期信号が２
ライン同期となつて時間軸基準の検出精度が劣化
し、これにより、時間軸圧縮された輝度信号が、
時間軸伸長する際、ジツターによつて大きく影響
されやすいが、本願発明では、かかる時間軸圧縮
された輝度信号の前に時間軸基準となる水平同期
信号が配置されるので、時間軸圧縮された輝度信
号に対するジツターの影響を低減できる。
According to the present invention, there is no bandwidth deterioration of the luminance signal, which was a drawback of the conventional time division multiplexing method, and it is possible to simultaneously reproduce a wideband luminance signal and a high-quality chroma signal. Sync signal is 2
Due to line synchronization, the detection accuracy based on the time axis deteriorates, and as a result, the time axis compressed luminance signal becomes
When expanding the time axis, it is likely to be greatly affected by jitter, but in the present invention, the horizontal synchronization signal serving as the time axis reference is placed before the time axis compressed luminance signal, so that the time axis compressed luminance signal is The influence of jitter on the luminance signal can be reduced.
第１図は本発明の記録回路の一例を示すブロツ
ク図、第２図は第１図の各部の波形とRAMの動
作を示す図、第３図は本発明の再生回路の一例を
示すブロツク図、第４図は第３図の各部の波形を
示す図、第５図は第３図のRAMの動作を示す図
である。
１２，１３，１４，１５……時間軸圧縮用
RAM、３，４，５７……ADコンバータ、１７，
４７，４８，４９，５０……DAコンバータ、４
０，４１，４２，４３……時間軸伸長用RAM。
FIG. 1 is a block diagram showing an example of the recording circuit of the present invention, FIG. 2 is a diagram showing the waveforms of each part of FIG. 1 and the operation of the RAM, and FIG. 3 is a block diagram showing an example of the reproducing circuit of the present invention. , FIG. 4 is a diagram showing waveforms of each part in FIG. 3, and FIG. 5 is a diagram showing the operation of the RAM in FIG. 3. 12, 13, 14, 15...For time axis compression
RAM, 3, 4, 57...AD converter, 17,
47, 48, 49, 50...DA converter, 4
0, 41, 42, 43...RAM for time axis expansion.
Claims (1)
を記録媒体に記録再生する映像信号の記録再生装
置において、 該輝度信号を所定の圧縮比で時間軸圧縮する第
１の手段と、 該第１、第２の該色差信号を所定の圧縮比で時
間軸圧縮する第２の手段と、 該第１の手段からの時間軸圧縮された輝度信号
と、該第２の手段からの時間軸圧縮された該第
１、第２の色差信号と、時間軸圧縮されない輝度
信号と、水平同期信号とを時分割多重し、先頭が
水平同期信号で該時間軸圧縮された第１の色差信
号と該時間軸圧縮された輝度信号とが時分割多重
された１つおきのラインと、該時間軸圧縮された
第２の色差信号と該時間軸圧縮されない輝度信号
とが時分割多重された他の１つおきのラインとか
らなる時分割多重信号を出力する第３の手段と を備え、該時分割多重信号を記録再生することを
特徴とする映像信号の記録再生装置。[Scope of Claims] 1. In a video signal recording and reproducing apparatus that records and reproduces at least a luminance signal and first and second color difference signals on a recording medium, the first apparatus compresses the luminance signal in a time axis at a predetermined compression ratio. means; second means for compressing the time axis of the first and second color difference signals at a predetermined compression ratio; a time axis compressed luminance signal from the first means; and the second means. The time-axis compressed first and second color difference signals, the luminance signal that is not time-axis compressed, and the horizontal synchronization signal are time-division multiplexed, and the horizontal synchronization signal starts from the time-axis compressed first color difference signal. The second color difference signal and the time-axis compressed luminance signal are time-division multiplexed, and the time-axis compressed second color difference signal and the non-time-axis compressed luminance signal are time-division multiplexed. and a third means for outputting a time division multiplexed signal consisting of every other line of the video signal, and recording and reproducing the time division multiplexed signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195979A JPS6089192A (en) | 1983-10-21 | 1983-10-21 | Recording and reproducing device of video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195979A JPS6089192A (en) | 1983-10-21 | 1983-10-21 | Recording and reproducing device of video signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6089192A JPS6089192A (en) | 1985-05-20 |
| JPH0523117B2 true JPH0523117B2 (en) | 1993-03-31 |
Family
ID=16350183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58195979A Granted JPS6089192A (en) | 1983-10-21 | 1983-10-21 | Recording and reproducing device of video signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089192A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5033732A (en) * | 1973-07-26 | 1975-04-01 | ||
| JPS535926A (en) * | 1976-07-02 | 1978-01-19 | Bosch Gmbh Robert | Method and device for transmitting and*or recording color television signal |
| JPS55149586A (en) * | 1979-05-09 | 1980-11-20 | Sony Corp | Recording method for color video signal |
| JPS5664585A (en) * | 1979-10-31 | 1981-06-01 | Nippon Telegr & Teleph Corp <Ntt> | Process system for color television signal |
-
1983
- 1983-10-21 JP JP58195979A patent/JPS6089192A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5033732A (en) * | 1973-07-26 | 1975-04-01 | ||
| JPS535926A (en) * | 1976-07-02 | 1978-01-19 | Bosch Gmbh Robert | Method and device for transmitting and*or recording color television signal |
| JPS55149586A (en) * | 1979-05-09 | 1980-11-20 | Sony Corp | Recording method for color video signal |
| JPS5664585A (en) * | 1979-10-31 | 1981-06-01 | Nippon Telegr & Teleph Corp <Ntt> | Process system for color television signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6089192A (en) | 1985-05-20 |
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